WO2012119401A1

WO2012119401A1 - Method and device for testing signal timing sequence

Info

Publication number: WO2012119401A1
Application number: PCT/CN2011/078632
Authority: WO
Inventors: 豆全亮; 王有
Original assignee: 华为技术有限公司
Priority date: 2011-08-19
Filing date: 2011-08-19
Publication date: 2012-09-13
Also published as: CN102439465A; CN102439465B

Abstract

Provided are a method and device for testing a signal timing sequence, relating to the technical field of testing. In the present invention, if a rising-edge sampling is carried out on a signal to be tested, then when the signal to be tested is at a rising edge, a control module controls to output a high level, and an enable module outputs a predetermined signal; when a clock signal is at a rising edge, the control module controls to output a low level, and the enable module stops outputting the predetermined signal; if a falling-edge sampling is carried out on the signal to be tested, then when the signal to be tested is at a rising edge, the control module controls to output a high level, and the enable module outputs a predetermined signal; and when the clock signal is at a falling edge, the control module controls to output a low level, and the enable module stops outputting. The number of rising edges of the predetermined signal successively outputted by the enable module is counted, and the establishment time and retention time of the timing sequence of the signal to be tested are determined according to the counted number of rising edges of the predetermined signal. The automatic testing of the signal timing sequence is realized with high accuracy, improving the working efficiency of testing the signal timing sequence, and reducing the development cost of hardware.

Description

Method and device for testing signal timing

Technical field

The present invention relates to the field of testing technologies, and in particular, to a method and apparatus for testing signal timing.

Background of the invention

Appropriate signal timing is a prerequisite for ensuring normal operation of the hardware. If the signal timing does not meet the requirements of the device, it will inevitably lead to abnormal hardware operation. The setup time and hold time in the signal timing are important parameters of the signal timing test. As shown in Figure 9, for a device that uses the rising edge of the clock, the time from the active level of the measured signal to the rising edge of the clock signal is the settling time of the measured signal; the rising edge of the clock signal The time between the effective level cutoff point of the measured signal is the hold time.

At present, the signal timing test method usually uses the two channels of the oscilloscope to simultaneously test the measured signal and the clock signal, and measures the phase difference between the measured signal and the clock signal, thereby obtaining the signal setup time and the hold time. However, the oscilloscope test has a large workload and a long test time. Especially in some special environments, such as high temperature test, it is very difficult and inaccurate to manually test the signal timing using an oscilloscope, which leads to low hardware development efficiency and impossible signal timing test. .

Summary of the invention

A signal timing test method and device according to an embodiment of the present invention does not require an oscilloscope, and realizes automatic test of signal timing, and has high accuracy, thereby providing work efficiency of signal timing test and reducing hardware development cost.

Embodiments of the present invention provide a method for testing signal timing, including:

If the test signal is subjected to rising edge sampling, the control module controls the output high level when the signal to be tested is at the rising edge; when the clock signal is at the rising edge, the control module controls the output low level; or

If the test signal is subjected to falling edge sampling, when the signal to be tested is at the rising edge, the control module controls the output high level; when the clock signal is at the falling edge, the control module controls the output low level;

When the control module outputs a high level, the enabling module outputs a predetermined signal; when the control module outputs a low level, stopping outputting the predetermined signal; the frequency of the predetermined signal is N times of the clock signal, and N is positive Integer

The number of rising edges of the predetermined signal continuously output by the statistic enabling module is determined, and the settling time and the holding time of the timing of the signal to be tested are determined according to the counted number of rising edges of the predetermined signal.

Embodiments of the present invention provide a signal timing testing apparatus, including:

a control module, configured to: if the test signal is subjected to rising edge sampling, when the signal to be tested is at a rising edge, the control output is high; when the clock signal is at a rising edge, the control outputs a low level; or, if used to treat When the test signal is sampled on the falling edge, the control output is high when the signal to be tested is at the rising edge; the output is low when the clock signal is at the falling edge; the enable module is used when the control module outputs a high level The enable module outputs a predetermined signal; when the control module outputs a low level, stopping outputting of the predetermined signal; the frequency of the predetermined signal is N times of the clock signal, and N is a positive integer;

The timing acquisition module is configured to count the number of rising edges of the predetermined signal continuously output by the enabling module, and determine the setup time and the hold time of the signal timing to be tested according to the counted number of rising edges of the predetermined signal.

The embodiment of the invention realizes the automatic test of the signal timing through the control module, the buffer module and the timing acquisition module, and has high accuracy, thereby improving the working efficiency of the signal timing test and reducing the hardware development cost. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic flowchart diagram of a method for testing signal timing according to an embodiment of the present invention;

2 is a schematic structural diagram of a device for testing signal timing according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a circuit structure of a control module 21 in a signal timing test apparatus according to an embodiment of the present invention; FIG. 4 is still another circuit structure of a control module 21 in a signal timing test apparatus according to an embodiment of the present invention; FIG. 5 is a schematic structural diagram of a phase-locked loop frequency multiplying circuit for obtaining an input signal of a buffer module 22 by using a clock signal in a signal timing testing apparatus according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a circuit structure of a counting sub-module 231 in a signal timing testing apparatus according to an embodiment of the present invention; FIG. 7 is a latching of a counting sub-module 231 in a signal timing testing apparatus according to an embodiment of the present invention; Schematic diagram of circuit and parallel-serial conversion circuit structure;

FIG. 8 is a clock signal CLK, an input signal Hclk, and test signals data0, Q _{0 according to an} embodiment of the present invention.

Waveforms of 0, _3⁄4 , and 0 ₃ ;

FIG. 9 is a schematic diagram showing the setup time and the hold time of the signal timing when the rising edge sampling is used in the prior art. Mode for carrying out the invention

The present invention provides a test method for signal timing, as shown in FIG. 1, including:

11. If the test signal is subjected to rising edge sampling, the control module controls the output high level when the signal to be tested is at the rising edge; when the clock signal is at the rising edge, the control module controls the output low level; or

If the test signal is subjected to falling edge sampling, the control module controls the output high level when the signal to be tested is at the rising edge; when the clock signal is at the falling edge, the control module controls the output low level.

12. When the control module outputs a high level, the enabling module outputs a predetermined signal; when the control module outputs a low level, stopping outputting the predetermined signal; the frequency of the predetermined signal is N times of the clock signal, N Is a positive integer.

Specifically, the predetermined signal is obtained by the phase locked loop frequency multiplying circuit of the clock signal.

The steps 11 and 12 are specifically implemented to enable the module to output a predetermined signal while the signal to be tested is on the rising edge to the rising edge of the clock signal when the rising edge of the signal to be tested is performed; when the falling edge of the signal to be tested is performed At the time of sampling, the enable module outputs a predetermined signal while the signal to be tested is at the rising edge until the clock signal is at the falling edge.

13. Counting the number of rising edges of the predetermined signal continuously output by the enabling module, and determining the settling time and the holding time of the signal timing to be tested according to the counted number of rising edges of the predetermined signal.

Further, if the number of rising edges of the predetermined signal continuously output by the statistic enabling module is m, and the period of the clock signal is υι, the settling time of the signal to be tested is ^c//, and the holding time is (1 - "- ji.

N N The embodiment of the present invention provides a signal timing testing device, as shown in FIG. 2, including:

The control module 21 is configured to: if the signal to be tested is subjected to rising edge sampling, when the signal to be tested is at a rising edge, the control outputs a high level; when the clock signal is at a rising edge, the control outputs a low level; or, if The falling edge of the test signal is sampled. Then, when the signal to be tested is on the rising edge, the control output is high; when the clock signal is on the falling edge, the control output is low. Further, if the test signal is subjected to rising edge sampling, the control module 21 includes a one-shot and a D flip-flop as shown in FIG. 3, and the B-port input clock signals CLK, R and C of the one-shot The port input power voltage VCC, the A port is grounded to GND, and the port is connected to the CLR port of the D flip-flop; the test signal is input from the CI port of the D flip-flop, the D port of the D flip-flop is input with the power supply voltage of the SET port, and the D flip-flop The beta port is the output of the control module. Specifically, when the CLR port of the D flip-flop is high, the β port of the D flip-flop outputs the signal to be tested input by the C1 port, and when the CLR port of the D flip-flop is low (only the one-shot of the monoflop) When the clock signal input to the port port has a rising edge and the port of the monoflop triggers a low level, that is, the CLR port of the D flip-flop is low level, the signal to be tested input by the C1 port of the D flip-flop is High level or low level, the β port of the D flip-flop always outputs low level. Therefore, the beta port of the D flip-flop can output a high level only when the beta port of the D flip-flop outputs the signal to be tested input by the C1 port and the signal to be tested is high. Therefore, only when the rising edge of the signal to be tested occurs and the clock signal is at the rising edge, the output of the control module outputs a high level, thereby triggering the enabling module 22.

If the test signal is subjected to falling edge sampling, the control module 21 includes an inverter, a monostable flip-flop and a D flip-flop as shown in FIG. 4. The input end of the inverter is connected to the clock signal CLK, and the output terminal and the single The Β port of the steady state flip-flop is connected, the R and C ports are input with the power supply voltage VCC, the port is connected to the ground GND, and the port is connected to the CLR port of the D flip-flop; the test signal is input from the CI port of the D flip-flop, the D flip-flop The D port and the SET port input the power supply voltage, and the β port of the D flip-flop is the output end of the control module. Specifically, when the CLR port of the D flip-flop is high, the β port of the D flip-flop outputs the signal to be tested input by the C1 port, and when the CLR port of the D flip-flop is low (only the clock of the inverter input) The signal is on the falling edge, the rising edge of the signal input from the Β port of the monoflop, the port of the monoflop triggers the low level, that is, the CLR port of the D flip flop is low), regardless of the D trigger. Whether the signal to be tested input by the C1 port of the device is high level or low level, the β port of the D flip-flop always outputs a low level. Therefore, the β port of the D flip-flop can output a high level only when the β port of the D flip-flop outputs the signal to be tested input from the C1 port and the signal to be tested is high. Therefore, the output of the control module will be triggered only when the rising edge of the signal to be tested and the falling edge of the clock signal are at a high level, thereby enabling the triggering of the enabling module 22.

The enabling module 22 is configured to: when the control module 21 outputs a high level, the enabling module outputs a predetermined signal; when the control module 21 outputs a low level, the output of the predetermined signal is stopped; the frequency of the predetermined signal is the clock The signal is multiplied by ,, and Ν is a positive integer.

Specifically, the enable port of the enable module 22 is connected to the output port of the control module 21, and when the control module 21 outputs a high level, the enable module 22 outputs a predetermined signal, and when the control module 21 outputs a low level, the enable module 22 The output of the predetermined signal is stopped, so that when the control module 21 outputs a high level, it is the setup time period in the signal timing of the signal to be tested. The predetermined signal HCLK outputted in the enabling module 22 is obtained by a phase-locked loop frequency multiplying circuit. The specific phase-locked loop frequency multiplying circuit is shown in FIG. 5, and the clock signal CLK is passed through the low-pass filtering from the phase detector input. After the device outputs a voltage signal, the voltage signal reaches the final stable state under the control of the voltage controlled oscillator and the 1/Ν frequency divider, that is, the frequency of the HCLK is exactly N times the frequency of the clock signal CLK.

The timing acquisition module 23 is configured to count the number of rising edges of the predetermined signal continuously output by the enabling module 22, and determine the setup time and the hold time of the signal timing to be tested according to the counted number of rising edges of the predetermined signal. Specifically, the timing acquisition module 23 includes a counting submodule 231 and an operation submodule 232.

The counting sub-module 231 is configured to count the number of rising edges of the predetermined signal continuously output by the enabling module 22.

Specifically, if the test signal is subjected to rising edge sampling, the counting submodule 231 may include (n+1) bit counters composed of (n+1) T flip-flops as shown in FIG. 6, and n is a positive integer, n The specific number can be determined based on the number of rising edges estimated in advance. The counting sub-module 231 is used to increase the output of the (n+1)-bit counter connected in parallel when the predetermined signal output from the enabling module 22 is at the rising edge. Alternatively, the counting sub-module 231 may further include a latch circuit and a parallel-serial conversion circuit as shown in FIG. 7, wherein 0, AI, ... are all D flip-flops, which constitute a data latch circuit, at the clock When the rising edge of the signal occurs, the output of the (n+1)-bit counter connected in parallel is latched. The clock signal is synchronized with the clock signal in the control module. Select one selector 0, 51... B _n , D flip-flop C0, CI... C« and D flip-flops D1 and D2 form a parallel-to-serial conversion circuit. When the rising edge of the clock signal occurs, the output of D1 makes 0, 51... Β"output Q ₀ , Q _x ...

Q _n , finally, Cn will continuously output H serial data SDA under the driving of the clock signal line SCL, which is the number of rising edges of the predetermined signal. If the test signal is sampled on the rising edge, the principle is the same, only the output of the parallel (n+1)-bit counter is latched when the falling edge of the clock signal occurs, and the clock signal is also synchronized with the clock signal in the control module.

The operation sub-module 232 is configured to determine a setup time and a hold time of the timing of the signal to be tested according to the number of rising edges of the predetermined signal counted by the counting sub-module 231.

Further, if the counting sub-module 231 counts that the number of rising edges of the predetermined signal continuously output by the enabling module is m, and the period of the clock signal is 1 UI, the setup time of the signal to be tested is, and the holding time is (1 -) UI.

N N

In the embodiment of the present invention, N is 10, n = 3, and the period of the clock signal is taken as an example, the clock signal CLK, the predetermined signal Hclk output by the enabling module, and the signals to be tested data0, β. The waveforms of , , , and ft are shown in Fig. 8. From the figure, β is known. The number of rising edges of the predetermined signal recorded by Q, Q, and 0 ₃ is 0110, which is 6, so the test signal is established.

—UI = 0.6UI, hold time is (1 - 0.6) UI = 0AUI.

10

When the rising edge of the signal to be tested is sampled by the control module, the control module controls whether a high level is output during a rising edge of the signal to be tested until the rising edge of the clock signal, or when the falling edge of the signal to be tested is sampled, The control module controls to output a high level when the rising edge of the signal to be tested reaches a falling edge of the clock signal; and enables the output frequency of the module to be N times of the clock signal under the enable driving of the high level output of the control module, timing The acquisition module determines the setup time and the hold time in the timing of the test signal by obtaining the number of rising edges of the signal whose frequency is N times the clock signal and the period of the clock signal. The above embodiment can realize automatic test of the timing and is accurate. High degree of efficiency improves the efficiency of signal timing testing and reduces hardware development costs. The test device for the above signal timing can be integrated inside the chip for automatic test of signal timing, for example, integrated synchronous random access memory SDRAM.

It should be noted that, in the above node embodiment, each module included is only divided according to functional logic, but it is not It is to be limited to the above-mentioned division as long as the corresponding functions can be realized; in addition, the specific names of the respective functional modules are only for the purpose of facilitating mutual differentiation, and are not intended to limit the scope of protection of the present invention.

In addition, those skilled in the art may understand that all or part of the steps in implementing the above method embodiments may be performed by a program to instruct related hardware, and the corresponding program may be stored in a computer readable storage medium. The storage medium may be a read only memory, a magnetic disk or an optical disk or the like.

The above is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of it within the technical scope disclosed by the embodiments of the present invention. Variations or substitutions are intended to be covered by the scope of the invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

Rights request

A method for testing signal timing, characterized in that it comprises:

The test method according to claim 1, wherein the predetermined signal output by the enabling module is obtained by a clock signal through a phase locked loop frequency multiplier circuit.

The test method according to claim 1, wherein determining the setup time and the hold time of the signal sequence to be tested according to the number of rising edges of the predetermined signal includes:

If the number of rising edges of the predetermined signal continuously output by the statistical enable module is m, and the period of the clock signal is 1 UI, the setup time of the signal to be tested is ^, and the hold time is ( ) υι.

N N

4. A signal timing test apparatus, comprising:

The test apparatus according to claim 4, wherein the predetermined signal output by the enabling module is obtained by a clock signal through a phase locked loop frequency multiplier circuit.

The test apparatus according to claim 4, wherein, if the test signal is subjected to rising edge sampling, the control module comprises a monostable flip-flop and a D flip-flop, and the B of the monostable flip-flop Port input clock signal, R and C ports input power supply voltage, A port is grounded, port is connected to CLR port of D flip-flop; the test signal is input from CI port of D flip-flop, D port of D flip-flop and input of SET port The power supply voltage, the beta port of the D flip-flop is the output end of the control module; if the test signal is subjected to falling edge sampling, the control module includes an inverter, a monostable flip-flop and a D flip-flop, and the inverter The input is connected to the clock signal CLK, the output is connected to the Β port of the monoflop, and the R and C ports are input. Voltage VCC, A port is grounded to GND, β port is connected to the CLR port of the D flip-flop; the test signal is input from the CI port of the D flip-flop, the D port of the D flip-flop is input with the power supply voltage of the SET port, and the D flip-flop is β. The port is the output of the control module.

The test apparatus according to claim 4, wherein the timing acquisition module comprises a counting submodule and an operation submodule,

The counting sub-module is configured to perform statistics on the number of rising edges of the predetermined signal continuously output by the enabling module; the operation sub-module is configured to determine, according to the number of rising edges of the predetermined signal, which is counted by the counting sub-module Test setup time and hold time of signal timing.

The test device according to claim 7, wherein the operation sub-module is specifically configured to: if the counting sub-module counts, the number of rising edges of the predetermined signal continuously output by the enabling module is m, and The period of the clock signal is 1 £//, and the settling time of the signal to be tested is ^, and the holding time is (ω).

Ν Ν