CN105759195A - Setup-hold time test system and setup-hold time test method based on fine phase modulation - Google Patents
Setup-hold time test system and setup-hold time test method based on fine phase modulation Download PDFInfo
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- CN105759195A CN105759195A CN201610100844.2A CN201610100844A CN105759195A CN 105759195 A CN105759195 A CN 105759195A CN 201610100844 A CN201610100844 A CN 201610100844A CN 105759195 A CN105759195 A CN 105759195A
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The invention belongs to the technical field of integrated circuit, and specifically relates to a setup-hold time test system and a setup-hold time test method based on fine phase modulation. According to the invention, the setup-hold time is tested by making use of the fine phase modulation function of a phase-locked loop and using two phase-adjustable clock signals. First, two phase-difference-adjustable clock signals are generated through the fine phase modulation function of a phase-locked loop; second, the two clock signals are respectively connected to a to-be-tested signal end and a clock end of a to-be-tested module; and third, the phase difference between the two clock signals is changed constantly to test the setup-hold time of a to-be-tested signal. According to the invention, the setup-hold time of a to-be-tested signal in a chip can be tested with only one phase-locked loop with the fine phase modulation function and a clock network channel which can reach the port of the to-be-tested module. The system and the method are of very good application value in such aspects as FPGA chip electrical parameter test and ASIC chip electrical parameter test. The system and the method have the advantages of low test cost, strong anti-interference performance, good portability, high universality, and the like.
Description
Technical field
The invention belongs to technical field of integrated circuits, be specifically related to in IC chip sheet inner module set up the system and method that the retention time tests.
Background technology
In synchronous circuit, the time of setting up of signal refers to that signal is before clock effectively arrive by edge, it is necessary to the time remained stable for；The retention time of signal refers to that signal is after clock effectively arrive by edge, it is necessary to the time remained stable for.
Foundation and retention time are the performance parameters that chip is very crucial.In the design phase of chip, set up the retention time plays very important effect to static timing analysis；Carrying out system design stage at application chip, setting up the retention time also determines the workable peak frequency of system.
About setting up the retention time, it is common to method of testing be all produce two to postpone controlled signal edges, be coupled with signal end and the clock end of module to be measured, the delay by constantly changing useful signal edge is poor, and that measures signal sets up the retention time.In actual test, it is generally adopted ATE (AutomaticTestEquipment, ATE) and tests.Such way is faced with the problems such as testing cost height, professional technique requirement property is strong, off-chip interference is big, and the test and excitation of ATE enters chip only by I/O mouth, it is impossible to directly test sheet inner module.
For ASIC(ApplicationSpecificIntegratedCircuit) chip, owing to the function of chip internal is comparatively single, for internal Time-Series analysis, is more pay attention in chip design stage.Complete the design to asic chip and test as chip designer after, what chip application person need not pay close attention to resource in chip slapper too much sets up the retention time.
Field programmable gate array (FieldProgrammableGateArray, FPGA), is that one can after chip manufacturing completes, moreover it is possible to changed the chip of its function by the mode programmed according to user's request1.For different application, the function within fpga chip is Protean.Fpga chip application person can use hardware description language easily, according to self-demand, fpga chip is configured to the function oneself needed2.Fpga chip designs for system and provides a kind of brand-new theory, certainly also brings more acute challenge for system designer.For the application person of fpga chip, merely ensure that fpga chip normal operation is inadequate, in addition it is also necessary to consider that whether the sequential of chip internal is correct3.This is accomplished by the retention time of setting up of fpga chip unit is done an accurate test, to facilitate eda tool more reliably to carry out Time-Series analysis.Current domestic and foreign literature is relatively fewer for the research setting up retention time test of FPGA sheet inner module signal.How at low cost, the retention time test of setting up being conveniently carried out FPGA internal resource is a good problem to study.
List of references:
[1]PereiraIG,DiasLA,deSouzaCP.AShift-RegisterBasedBISTArchitectureforFPGAGlobalInterconnectTestingandDiagnosis[J].JournalofElectronicTesting,2015,31(2):207-215.
[2]KuonI,TessierR,RoseJ.FPGAarchitecture:Surveyandchallenges[J].FoundationsandTrendsinElectronicDesignAutomation,2008,2(2):135-253.
[3]ChenD,CongJ,PanP.FPGAdesignautomation:Asurvey[J].FoundationsandTrendsinElectronicDesignAutomation,2006,1(3):139-169.
[4]JiaC,MilorL.ADLLdesignfortestingI/Osetupandholdtimes[J].VeryLargeScaleIntegration(VLSI)Systems,IEEETransactionson,2009,17(11):1579-1592.
[5]AlteraCorporation.StratixIIIDeviceHandbook[EB/OL].https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/stx3/stratix3_handbook.pdf,2011.
[6]XilinxCorporation.Virtex-4UserGuide[EB/OL].http://www.xilinx.com/support/documentation/user_guides/ug070.pdf,2008.。
Summary of the invention
It is an object of the invention to provide that a kind of portability is good, cost is low, strong interference immunity IC chip internal module set up the system and method that the retention time tests.
Provided by the invention IC chip internal module set up its typical test system that the retention time surveys, its typical circuit is as it is shown in figure 1, include: fine phase modulation module, clock network, circuit under test module, arbitration circuit module and control circuit module；Wherein, fine phase modulation module is used for producing adjustable two signals of phase contrast: the first signal and secondary signal (i.e. signal 1 and signal 2)；Two signals receive any circuit under test module in chip by clock network；The output response of circuit under test module is received in arbitration circuit module；Output response is processed by arbitration circuit module, to determine the result of test；Control circuit module is for controlling the co-ordination of fine phase modulation module, circuit under test module, arbitration circuit module.
The present invention utilizes the fine phase modulation function of phaselocked loop, by the clock signal of two phase-adjustable, carries out setting up the test of retention time.First, by the fine phase modulation function of phaselocked loop, produce two adjustable clock signals of phase contrast；Then, by clock network, two clock signals are coupled with measured signal end and the clock end of module to be measured；Finally, being constantly changing the phase contrast of two clock signals, that measures measured signal sets up the retention time.
The technological core point of the present invention is in that: utilize the edge equivalence of two clock signals to set up two effective edges in retention time test, the delay that two effective edges in retention time test are set up in the phase contrast equivalence utilizing phaselocked loop two clocks of adjustment is poor, a signal is utilized to be transferred to each signal port time approximately equalised characteristic through clock network, it is achieved the test of low cost.
Set up the test of retention time, particularly may be divided into:
(1) " 1 " sets up the time: for guaranteeing that register capture arrives data " 1 ", and efficient clock must remain stable for the time of " 1 " in advance along the front data port that arrives；
(2) " 1 " retention time: for guaranteeing that register capture arrives data " 1 ", after the arrival of efficient clock edge, data port must remain stable for the time of " 1 "；
(3) " 0 " sets up the time: for guaranteeing that register capture arrives data " 0 ", and efficient clock must remain stable for the time of " 0 " in advance along the front data port that arrives；
(4) " 0 " retention time: for guaranteeing that register capture arrives data " 0 ", after the arrival of efficient clock edge, data port must remain stable for the time of " 0 "；
Described fine phase modulation module can with utilizing existing delay phase-locked loop DLL in chip4, phase-locked loop (PhaseLockedLoop, PLL)5, digital dock administrative unit (DigitalClockManager, DCM)6Etc. completing.The ready-made module that can be used for producing accurate phase modulation function is not had, it is possible to do one and there is the PLL of accurate phase modulation function in chip as test IP kernel in fruit chip.Two clock signals with certain phase contrast that fine phase modulation module produces can be received special clock network and be communicated to module measured signal port to be measured.So-called special clock network, refers to the interconnection circuit net being specifically designed to transfer clock signal in chip.This circuit network is responsible for demands such as the different physical locations in clock signal transmission to chip, clock network circuit general satisfaction low-power consumption, high output, altofrequencies.As it is shown on figure 3, be the XC4VLX15 type fpga chip of Xilinx company6Clock network Organization Chart, clock signal first by special clock input signal cable be transferred in 32 global drive devices any one or more, then be transferred to the different physical locations of chip by MUX and some special drive circuits by global drive device.
The difference of special clock network interconnection circuit and normal signal interconnection circuit be mainly reflected in following some:
(1) in identical clock source signals arrival chip, the delay difference of different physical locations is little, is generally less than 0.1ns；
(2) shake of signal is little；
(3) Duty Cycle Distortion of signal is little；
(4) frequency of signal is high, is typically in more than 500MHz；
Skew and jitter in the chips is minimum for the propagation path of clock signal, both can reduce measurement error, it is also possible to improve the stability of test.Measured signal is any signal port that the clock network in chip can arrive.
Disclosure is particularly well suited to the resource in FPGA is tested, because the PLL with fine phase modulation function is very general at modern FPGA, clock network also almost may be coupled to any one port of any one module in sheet.Arbitration circuit and control circuit do not need extra chip area, it is only necessary to the configurable logic block (CLB) configured in a bottom sheet by hardware description language can realize.The schematic diagram of a kind of implementation of arbitration circuit is as shown in Figure 9.A kind of implementation of the state machine of control circuit as shown in Figure 10, illustrates and sees applicating example.Module to be measured can be the programmable logic block (ConfigurableLogicBlock, CLB) in FPGA, digital signal processor (DigitalSignalProcessor, DSP), block storage (BlockRAM, BRAM) etc..
The retention time is set up for the trigger in the CLB in the XC4VLX200 chip testing Xilinx company.Fine phase modulation module can use the digital dock administrative unit (DigitalClockManager, DCM) in chip to realize.As shown in Figure 2, clock signal is first input into first Clock Managing Unit DCM_FX_1, by in the input of frequency-doubled signal second Clock Managing Unit DCM_FX_2 of input of first Clock Managing Unit DCM_FX_1 output, frequency-doubled signal is passed to simultaneously the input of following two Clock Managing Unit DCM_PS_1 and DCM_PS_2 through clock network.Two Clock Managing Unit DCM_PS_1 and DCM_PS_2 are by output feedack to respective FB end, output clock and input clock is made to keep the phase place of a locking, it is possible to configure at FPGA change this phase place afterwards by controlling the number control signal of DCM_PS_1 and DCM_PS_2.The signal 1 of phase-adjustable is received on the measured signal of module to be measured by Clock Managing Unit DCM_PS_1；Clock Managing Unit DCM_PS_2 produces signal 2, receives the clock end of module to be measured.Clock Managing Unit DCM_PS_2 can regulate the Phase delay of signal 2, compensates with the skew that the difference to signal 1 and the walked path of signal 2 causes.
Set up the retention time for the data port D that tests a d type flip flop below, illustrate the testing procedure setting up the retention time.
One, the test of time is set up about " 1 " of the data port D of d type flip flop.Connect the D end of trigger by fine phase modulation module signal 1 out, signal 2 connects CLK end, as shown in Figure 4.When testing " 1 " of data port D of d type flip flop and setting up the time, the control of signal 1 and signal 2 is as it is shown in figure 5, the dash area of rising edge clock represents foundation and the retention time of D respectively, and the state machine of the control circuit of test is as shown in Figure 10.Specifically comprise the following steps that
(1), as shown in Fig. 5 (a), time initial, the phase alignment of D and CLK, now the state machine of control circuit is in IDLE state；
(2) than CLK, the phase place furnishing of D being shifted to an earlier date 1/4 phase place, as shown in Fig. 5 (b), the state machine of control circuit toggles between IniPS and IniPS_Adj.In IniPS state, whether the more current phase place of control circuit is identical with expectation phase place, and namely D shifts to an earlier date 1/4 phase place, if it is not, then enter IniPS_Adj state, and a mobile minimum phase shift unit, return IniPS, until moving to expectation phase place.When moving to expectation phase place, what trigger was stable collects data " 1 "；
(3) controlling DCM_PS_1, make the phase place of signal 1 move right, as shown in Fig. 5 (c), the state machine of control circuit toggles between ChkPS and ChkPS_Adj.In ChkPS state, when D is introduced into metastable state, now do not have sequential to run counter to, jump in ChkPS_Adj state, carry out the phase shift of a unit, return to ChkPS state.When D enters between metastable zone, owing to the time of setting up is unsatisfactory for, what trigger cannot be stable collects 1, and output at least there will be once " 1 " and the saltus step of " 0 ", and setting up the time of " 1 " exactly now measured, state machine jumps to RtnPS；
(4) as shown in Fig. 5 (d), the phase place of signal 1 moving on to initial 0 phase place, wait and testing next time, wherein during RtnPS state, comparing whether phase shift resets, RtnPS_Adj carries out the phase shift of a unit.Phase place resets after successfully, and state machine jumps back to IDLE state；
Above-mentioned steps (3), arbitration circuit is responsible for the saltus step of " 1 " and " 0 " that automatically detects that circuit under test exports, and one realizes method as shown in Figure 9.Initial_Q is the output valve of a depositor.When its value is signal 1 than signal 2 1/4 phase place in advance, as shown in Fig. 5 (b), the output response of circuit under test.Now, what circuit under test can be stable adopts " 1 ".FF_Arb is a d type flip flop with asynchronous resetting function, and CLR is only in above-mentioned steps (3), and the output signal 1 of DCM_PS_1 is adjusted to after stablizing, and CLR is invalid.When the sampling of trigger to be measured enters metastable state, to I haven't seen you for ages, experience once " 1 " arrives the saltus step of " 0 " to the output response Q in Fig. 4.So the clock end of the FF_Arb trigger in Fig. 9 there will be efficient clock, and Chk_Q exports " 1 ", it was shown that detecting that the time of setting up of circuit under test runs counter to, otherwise Chk_Q maintains " 0 " always.The value of Chk_Q is returned to control module, carries out the decoding of test result.
Two, about " 1 " retention time of the data port D of d type flip flop test time.As shown in Figure 6, the dash area of rising edge clock represents foundation and the retention time of D respectively, specifically comprises the following steps that in the control of signal 1 and signal 2
(1) as shown in Figure 6 (a), time initial, the phase alignment of D and CLK；
(2) the phase place furnishing of D is shifted to an earlier date 1/4 phase place than CLK, as shown in Figure 6 (b).Now, what trigger was stable collects data " 1 "；
(3) DCM_PS_1 is controlled, make the phase place of signal 1 to moving to left, as shown in Figure 6 (c), when D enters between metastable zone, owing to the retention time is unsatisfactory for, trigger cannot be stable collect 1, output at least there will be once " 1 " and the saltus step of " 0 ", what now measure is exactly the retention time of " 1 "；
(4) as shown in Fig. 6 (d), the phase place of signal 1 is moved on to initial 0 phase place, wait and testing next time.
Three, the test of time is set up about " 0 " of the data port D of d type flip flop.The control of signal 1 and signal 2, as it is shown in fig. 7, the dash area of rising edge clock represents foundation and the retention time of D respectively, specifically comprises the following steps that
(1) as shown in Figure 7 (a), time initial, the phase alignment of D and CLK；
(2) the phase place furnishing of D is postponed 1/4 phase place than CLK, as shown in Figure 7 (b) shows.Now, what trigger was stable collects data " 0 "；
(3) DCM_PS_1 is controlled, the phase place making signal 1 moves right, as shown in Fig. 7 (c), when D enters between metastable zone, owing to the time of setting up is unsatisfactory for, trigger cannot be stable collect 0, output at least there will be once " 0 " and the saltus step of " 1 ", now measure be exactly " 0 " set up the time；
(4) as shown in Fig. 7 (d), the phase place of signal 1 is moved on to initial 0 phase place, wait and testing next time.
Four, about " 0 " retention time of the data port D of d type flip flop test time.As shown in Figure 8, the dash area of rising edge clock represents foundation and the retention time of D respectively, specifically comprises the following steps that in the control of signal 1 and signal 2
(1) as shown in Figure 8 (a), time initial, the phase alignment of D and CLK；
(2) the phase place furnishing of D is postponed 1/4 phase place than CLK, as shown in Figure 8 (b) shows.Now, what trigger was stable collects data " 0 "；
(3) DCM_PS_1 is controlled, make the phase place of signal 1 to moving to left, as shown in Fig. 8 (c), when D enters between metastable zone, owing to the retention time is unsatisfactory for, trigger cannot be stable collect 0, output at least there will be once " 0 " and the saltus step of " 1 ", what now measure is exactly the retention time of " 0 "；
(4) as shown in Fig. 8 (d), the phase place of signal 1 is moved on to initial 0 phase place, wait and testing next time.
More than be the present invention an application, the present invention be possible not only to test data terminal D set up the retention time, it is also possible to that tests the signal such as synchronous enabled end CE, synchronous reset set SR sets up the retention time, as long as clock network can arrive above-mentioned signal.
The measuring accuracy of the present invention is relevant with the minimum precision of fine phase modulation module, sets up the time and retention time sum can not more than half clock cycle of signal 1.
Technique effect
The present invention when not needing externally measured instrument, can utilize the fine phase modulation module of chip internal, it is achieved to the test setting up the retention time of resource in any sheet of chip, the retention time of setting up being especially suitable for the internal resource to fpga chip tests.The method is compared to general test method, and it is portable good to have, the features such as cost is low, strong interference immunity.Certainty of measurement is only relevant with the precision of fine phase modulation module, and the DCM maximum clock frequency such as the XC4VLX200 of Xilinx company is 500MHz, and phase modulation precision can reach 7.8ps(2ns/256).
Accompanying drawing explanation
Fig. 1 is test system block diagram.
Fig. 2 manages module by digital dock to configure fine phase modulation module.
Fig. 3 special clock network architecture diagram.
Fig. 4 is module to be measured.
Fig. 5 sets up the method for testing of time for " 1 ".
Fig. 6 is the method for testing of " 1 " retention time.
Fig. 7 sets up the method for testing of time for " 0 ".
Fig. 8 is the method for testing of " 0 " retention time.
Fig. 9 is a kind of implementation of arbitration circuit.
A kind of state machine that Figure 10 is control circuit realizes.
Detailed description of the invention
The implementation of the present invention has a variety of, and detailed description of the invention is as follows:
The present invention realizes block diagram as shown in Figure 1 substantially.Produced the clock signal 1 of two phase-adjustable and signal 2 by fine phase modulation module, the measured signal end of slowdown monitoring circuit such as by special clock network, signal 1 is connect, such as the data terminal D of d type flip flop, signal 2 is received the clock end of slowdown monitoring circuit.The outfan of circuit under test is received the input of arbitration circuit.Control circuit is responsible for fine phase modulation module is carried out phase modulation, arbitration circuit is controlled, when phase modulation is stable, the arbitration result of circuit under test is analyzed.Control circuit controls the automatic test of circuit.
Set up the time for " 1 " testing d type flip flop, fine phase modulation module circuit diagram as in figure 2 it is shown, module to be measured as shown in Figure 4, arbitration circuit is as shown in Figure 9.First signal 1 is adjusted to ratio signal 2 1/4 phase place in advance, and locks, such as Fig. 5 (b).Again the phase place of signal 1 is turned right tune, as shown in Fig. 5 (c), along with the phase place of signal 1 and signal 2 is constantly close, when " 1 " of D data set up the time do not meet time, output Q will at least occur once that " 0 " arrives the saltus step of " 1 ".Now arbitration circuit can be obtained by being timely detected the saltus step of Q.In time saltus step being detected, control circuit just can control fine phase modulation module, circuit under test, arbitration circuit return to original state, waits and testing next time, and outputs test result.
Such scheme is the one in implementation, according to system block diagram as shown in Figure 1, the implementation of modules can redesign as required, can use DLL or PLL in chip such as fine phase modulation module, and arbitration circuit, control circuit can also flexible design according to demand.
The present invention realizes especially facilitating in FPGA, has the features such as testing cost low, strong interference immunity, portable good, highly versatile；The test IP kernel in asic chip can also be made, the resource in sheet is tested.
Claims (9)
1. the retention time of setting up based on fine phase modulation tests system, it is characterised in that including: fine phase modulation module, clock network, circuit under test module, arbitration circuit module and control circuit module；Wherein, described fine phase modulation module is used for producing adjustable two signals of phase contrast and signal 1 and signal 2；Two signals receive any circuit under test module in chip by clock network；The output response of circuit under test module is received in arbitration circuit module；Output response is processed by arbitration circuit module, to determine the result of test；Control circuit module is for controlling the co-ordination of fine phase modulation module, circuit under test module, arbitration circuit module.
2. the retention time of setting up based on fine phase modulation according to claim 1 tests system, it is characterised in that by the fine phase modulation function of phaselocked loop, produce two adjustable clock signals of phase contrast；By clock network, two clock signals are coupled with measured signal end and the clock end of module to be measured；Being constantly changing the phase contrast of two clock signals, that measures measured signal sets up the retention time.
3. according to claim 1 and 2 based on fine phase modulation set up the retention time test system, it is characterised in that described set up the retention time test, be divided into:
(1) " 1 " sets up the time；
(2) " 1 " retention time；
(3) " 0 " sets up the time；
(4) " 0 " retention time.
4. the retention time of setting up based on fine phase modulation according to claim 1 and 2 tests system, it is characterized in that, described fine phase modulation module utilizes existing delay phase-locked loop in chip, phase-locked loop, digital dock administrative unit to realize, or tests IP kernel with a PLL with accurate phase modulation function to conduct in chip.
5. the retention time of setting up based on fine phase modulation according to claim 1 and 2 tests system, it is characterised in that described circuit under test module is the programmable logic block in FPGA, digital signal processor or block storage.
6. the retention time of setting up based on fine phase modulation according to claim 1 and 2 tests system, it is characterised in that described fine phase modulation module adopts the digital dock administrative unit in chip to realize；Clock signal is first input into first Clock Managing Unit DCM_FX_1, by in the input of frequency-doubled signal second Clock Managing Unit DCM_FX_2 of input of first Clock Managing Unit DCM_FX_1 output, frequency-doubled signal is passed to simultaneously the input of following two Clock Managing Unit DCM_PS_1 and DCM_PS_2 through clock network；Two Clock Managing Unit DCM_PS_1 and DCM_PS_2 are by output feedack to respective FB end, make to export clock and keep a phase place locked with input clock, and the control signal passing through two Clock Managing Unit DCM_PS_1 and DCM_PS_2 of control has configured at FPGA and changed this phase place afterwards；First signal of phase-adjustable is received on the measured signal of module to be measured by the 3rd Clock Managing Unit DCM_PS_1；4th Clock Managing Unit DCM_PS_2 produces signal 2, receives the clock end of module to be measured；4th Clock Managing Unit DCM_PS_2 regulates the Phase delay of signal 2, compensates with the skew that the difference to signal 1 and the walked path of signal 2 causes.
7. one kind based on described in claim 1-6 test system set up retention time method of testing, it is characterised in that concretely comprise the following steps:
First, by the fine phase modulation function of phaselocked loop, produce two adjustable clock signals of phase contrast；
Then, by clock network, two clock signals are coupled with measured signal end and the clock end of module to be measured；
Finally, by being constantly changing the phase contrast of two clock signals, that measures measured signal sets up the retention time.
8. according to claim 7 set up retention time method of testing, it is characterised in that set up the retention time include data terminal D set up the retention time, synchronous enabled end CE signal set up the retention time, synchronous reset set SR signal set up the retention time.
9. according to claim 7 set up retention time method of testing, it is characterised in that for a d type flip flop data port D set up retention time test, wherein:
The testing procedure that " 1 " sets up the time is as follows:
(1), time initially, the phase alignment of D and CLK, now the state machine of control circuit is in IDLE state；
(2) than CLK, the phase place furnishing of D being shifted to an earlier date 1/4 phase place, the state machine of control circuit toggles between IniPS and IniPS_Adj；In IniPS state, whether the more current phase place of control circuit is identical with expectation phase place, and namely D shifts to an earlier date 1/4 phase place, if it is not, then enter IniPS_Adj state, and a mobile minimum phase shift unit, return IniPS, until moving to expectation phase place；When moving to expectation phase place, what trigger was stable collects data " 1 "；
(3) controlling DCM_PS_1, make the phase place of signal 1 move right, the state machine of control circuit toggles between ChkPS and ChkPS_Adj；In ChkPS state, when D is introduced into metastable state, now do not have sequential to run counter to, jump in ChkPS_Adj state, carry out the phase shift of a unit, return to ChkPS state；When D enters between metastable zone, owing to the time of setting up is unsatisfactory for, what trigger cannot be stable collects 1, and output at least there will be once " 1 " and the saltus step of " 0 ", and setting up the time of " 1 " exactly now measured, state machine jumps to RtnPS；
(4) phase place of signal 1 moving on to initial 0 phase place, wait and testing next time, wherein during RtnPS state, comparing whether phase shift resets, RtnPS_Adj carries out the phase shift of a unit；Phase place resets after successfully, and state machine jumps back to IDLE state；
Testing procedure during " 1 " retention time is as follows:
(1) time initially, the phase alignment of D and CLK；
(2) than CLK, the phase place furnishing of D being shifted to an earlier date 1/4 phase place, now, what trigger was stable collects data " 1 "；
(3) control DCM_PS_1, make the phase place of signal 1 to moving to left, when D enters between metastable zone, owing to the retention time is unsatisfactory for, trigger cannot be stable collect 1, output at least there will be once " 1 " and the saltus step of " 0 ", what now measure is exactly the retention time of " 1 "；
(4) phase place of signal 1 is moved on to initial 0 phase place, wait and testing next time；
Testing procedure when " 0 " sets up the time is as follows:
(1) time initially, the phase alignment of D and CLK；
(2) than CLK, the phase place furnishing of D being postponed 1/4 phase place, now, what trigger was stable collects data " 0 "；
(3) control DCM_PS_1, make the phase place of signal 1 move right, when D enters between metastable zone, owing to the time of setting up is unsatisfactory for, trigger cannot be stable collect 0, output at least there will be once " 0 " and the saltus step of " 1 ", now measure be exactly " 0 " set up the time；
(4) phase place of signal 1 is moved on to initial 0 phase place, wait and testing next time；
Testing procedure during " 0 " retention time is as follows:
(1) time initially, the phase alignment of D and CLK；
(2) than CLK, the phase place furnishing of D being postponed 1/4 phase place, now, what trigger was stable collects data " 0 "；
(3) control DCM_PS_1, make the phase place of signal 1 to moving to left, when D enters between metastable zone, owing to the retention time is unsatisfactory for, trigger cannot be stable collect 0, output at least there will be once " 0 " and the saltus step of " 1 ", what now measure is exactly the retention time of " 0 "；
(4) phase place of signal 1 is moved on to initial 0 phase place, wait and testing next time.
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Cited By (11)
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| CN108120919A (en) * | 2017-12-27 | 2018-06-05 | 北京华峰测控技术股份有限公司 | A kind of integrated circuit time parameter test circuit and method |
| CN108804371A (en) * | 2018-05-28 | 2018-11-13 | 电子科技大学 | A kind of synchronization automatic correcting method that multi-channel high-speed data receives |
| CN110033819A (en) * | 2018-01-11 | 2019-07-19 | 中芯国际集成电路制造(上海)有限公司 | SRAM establishes retention time test circuit |
| CN112117995A (en) * | 2020-09-30 | 2020-12-22 | 成都华微电子科技有限公司 | FPGA (field programmable Gate array) on-chip clock duty ratio test method and clock self-test FPGA |
| CN112733478A (en) * | 2021-04-01 | 2021-04-30 | 芯华章科技股份有限公司 | Apparatus for formal verification of a design |
| CN113012750A (en) * | 2019-12-18 | 2021-06-22 | 中移物联网有限公司 | Testing device and method for memory chip |
| CN113361084A (en) * | 2021-05-26 | 2021-09-07 | 飞腾信息技术有限公司 | Chip design method, device, apparatus, readable storage medium and program product |
| WO2021238829A1 (en) * | 2020-05-29 | 2021-12-02 | 中兴通讯股份有限公司 | Timing unit establishing time measuring method and measuring circuit |
| WO2021238838A1 (en) * | 2020-05-29 | 2021-12-02 | 中兴通讯股份有限公司 | Method and circuit for measuring retention time of time sequence unit |
| CN114152864A (en) * | 2021-11-29 | 2022-03-08 | 江苏捷策创电子科技有限公司 | Method and device for multi-chip parallel test |
| CN114199519A (en) * | 2021-10-31 | 2022-03-18 | 昆山丘钛光电科技有限公司 | Testing device and system |
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| CN108120919B (en) * | 2017-12-27 | 2019-12-13 | 北京华峰测控技术股份有限公司 | integrated circuit time parameter testing circuit and method |
| CN108120919A (en) * | 2017-12-27 | 2018-06-05 | 北京华峰测控技术股份有限公司 | A kind of integrated circuit time parameter test circuit and method |
| CN110033819A (en) * | 2018-01-11 | 2019-07-19 | 中芯国际集成电路制造(上海)有限公司 | SRAM establishes retention time test circuit |
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| CN108804371A (en) * | 2018-05-28 | 2018-11-13 | 电子科技大学 | A kind of synchronization automatic correcting method that multi-channel high-speed data receives |
| CN108804371B (en) * | 2018-05-28 | 2021-07-30 | 电子科技大学 | Synchronous self-correcting method for receiving multichannel high-speed data |
| CN113012750B (en) * | 2019-12-18 | 2023-08-15 | 中移物联网有限公司 | Testing device and method for memory chip |
| CN113012750A (en) * | 2019-12-18 | 2021-06-22 | 中移物联网有限公司 | Testing device and method for memory chip |
| WO2021238829A1 (en) * | 2020-05-29 | 2021-12-02 | 中兴通讯股份有限公司 | Timing unit establishing time measuring method and measuring circuit |
| WO2021238838A1 (en) * | 2020-05-29 | 2021-12-02 | 中兴通讯股份有限公司 | Method and circuit for measuring retention time of time sequence unit |
| CN112117995A (en) * | 2020-09-30 | 2020-12-22 | 成都华微电子科技有限公司 | FPGA (field programmable Gate array) on-chip clock duty ratio test method and clock self-test FPGA |
| CN112733478A (en) * | 2021-04-01 | 2021-04-30 | 芯华章科技股份有限公司 | Apparatus for formal verification of a design |
| CN113361084A (en) * | 2021-05-26 | 2021-09-07 | 飞腾信息技术有限公司 | Chip design method, device, apparatus, readable storage medium and program product |
| CN113361084B (en) * | 2021-05-26 | 2023-02-07 | 飞腾信息技术有限公司 | Chip design method, device, apparatus, readable storage medium and program product |
| CN114199519A (en) * | 2021-10-31 | 2022-03-18 | 昆山丘钛光电科技有限公司 | Testing device and system |
| CN114199519B (en) * | 2021-10-31 | 2024-04-16 | 昆山丘钛光电科技有限公司 | Testing device and system |
| CN114152864A (en) * | 2021-11-29 | 2022-03-08 | 江苏捷策创电子科技有限公司 | Method and device for multi-chip parallel test |
| CN114152864B (en) * | 2021-11-29 | 2024-05-03 | 江苏捷策创电子科技有限公司 | Multi-chip parallel test method and device |
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