CN1790286A - PCI test card and test method thereof - Google Patents
PCI test card and test method thereof Download PDFInfo
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- CN1790286A CN1790286A CN 200410093202 CN200410093202A CN1790286A CN 1790286 A CN1790286 A CN 1790286A CN 200410093202 CN200410093202 CN 200410093202 CN 200410093202 A CN200410093202 A CN 200410093202A CN 1790286 A CN1790286 A CN 1790286A
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Abstract
The invention discloses a PCI test card, which comprises the following parts: signal generator, datum clock generator, phase-locked loop, control circuit and display unit, wherein the signal generator produces the needed test signal; the datum clock generator forms the datum clock signal; the phase-locked loop divides the datum clock signal into several phases equally, which moves the signal forwards or backwards once or several phases; the display unit displays the present moving signal; the control circuit generates the control signal and phase moving direction and number. The invention can test the establishing time and keep the time limit directly, which improves the test precision and efficiency.
Description
Technical field
The present invention relates to computing machine peripheral equipment field, particularly relevant a kind of PCI test card and method of testing thereof.
Background technology
In the current Circuits System (as mainboard), because the difference of chip selection, design philosophy and device difference, be different with the tolerance limit of retention time the Time Created of each Circuits System signal, and these parameters have important directive significance for the stability of weighing system.
Existing P CI (Peripheral component interconnection) test card is often tested at the PCI agreement, measure pci signal and whether satisfy agreement, and can on oscillograph, demonstrate the situation of change of signal, as the batch testing device in No. the 02117679th, the Chinese patent.Perhaps as test chart, as the single step error correction device in No. the 00134858th, the Chinese patent, whether the investigation system moves when power-on self-test normally.These methods for designing all can not detect the tolerance limit of some time parameter of pci signal.
For the tolerance limit of the Time Created and retention time of under existence conditions, measuring each Circuits System signal, generally adopt the oscillograph test, and its waveform signal is understood calculating, draw the time tolerance parameter.But this need of work has special technician to calculate the deciphering waveform, and in general the staff to read oscillographic waveform accurate inadequately, if adopt the oscillograph of advanced high precision then the price comparison costliness, adopt the human interpretation waveform to calculate the method for Time Created, retention time tolerance limit in a word at present, waste time and energy and cost dearly.
Summary of the invention
The object of the present invention is to provide a kind of PCI test card,, solve prior art and can't directly measure the problem of pci signal time to overcome above-mentioned the deficiencies in the prior art.
For achieving the above object, the invention provides a kind of PCI test card, comprise: signal generator, reference clock generator, phaselocked loop, control circuit and display unit, wherein signal generator produces required test signal, reference clock generator produces reference clock signal, phaselocked loop grades this signal and is several phase places, and pass through its phase shift function signal is moved one or several phase places one by one forward or backward, display unit shows the current signal number of institute's travel(l)ing phase forward or backward, and control circuit produces the direction and the phase place number of control signal and signal displacement.
Wherein, described signal generator produces required test signal; Reference clock generator produces reference clock signal; Control circuit can be controlled by the computer system that installs application software additional by the user; Display unit can be with the time stack of each phase delay of being moved and direct display delay time.Several phase places that are divided at signal are under the situation of five equilibrium, and the time that display unit can multiply by the number of phases that is shifted delay superposes and the direct display delay time.Described signal generator, phaselocked loop and control circuit are made of programmable logic device (PLD), and this programmable logic device (PLD) is FPGA (Field programmable GatesArray, a field programmable gate array); Described reference clock generator is made of quartz crystal oscillator; Described display unit is LED (light-emitting diode, a light emitting diode).
Another object of the present invention is to provide a kind of method of testing of pci system, solve prior art and can't directly measure the problem of the Time Created of pci signal.
For achieving the above object, the method for testing that the invention provides a kind of pci system may further comprise the steps: a. provides test signal and reference clock signal; B. with phaselocked loop reference clock signal is divided into several phase places; C. the clock signal in the test signal is moved forward one by one the five equilibrium phase place of or several reference clocks, till test signal is invalid; D. write down the number of test signal phase place that clock signal shifted forward in test signal when invalid.
The time that the number of the phase place that clock signal moved when further, utilizing test signal invalid in the test signal multiply by each phase place can calculate tolerance limit Time Created of signal; Calculate test signal point ineffective time apart from the time period between the next rising edge of clock signal, income value is the minimum Time Created of signal.
A further object of the present invention is to provide a kind of method of testing of pci system, solves prior art and can't directly measure the problem of the retention time of pci signal.
For achieving the above object, the invention provides a kind of method of testing of pci system, may further comprise the steps: a. provides test signal and reference clock signal; B. with phaselocked loop reference clock signal is divided into several phase places; C. the clock signal in the test signal is moved one by one backward the five equilibrium phase place of or several reference clocks, till test signal is invalid; D. write down test signal when invalid clock signal in the test signal to the number of the phase place of backward shift.
The time that the number of the phase place that clock signal was shifted when further, utilizing test signal invalid in the test signal multiply by each phase place can calculate the retention time tolerance limit of signal; Calculate test signal point ineffective time apart from the time period between the negative edge of current test signal, income value is the minimum hold time of signal.
The present invention is by carrying out tolerance limit and minimum Time Created and the minimum hold time of phase shift with the Time Created that records signal and retention time to signal.The present invention does not need special technician's operation, and measuring accuracy is higher, and the result need not complicated deciphering and calculates, and can read from instrument, thereby have higher testing efficiency.In addition, test card according to the present invention is simple in structure, has preferable reliability, and equipment price is also relatively more cheap.
The present invention is further illustrated below in conjunction with accompanying drawing and embodiment.
Description of drawings
Fig. 1 is the structural representation of one embodiment of the present of invention.
Fig. 2 is the phaselocked loop inner structure synoptic diagram of one embodiment of the present of invention.
Fig. 3 is the test philosophy synoptic diagram of tolerance limit Time Created.
Fig. 4 is the test philosophy synoptic diagram of retention time tolerance limit.
Embodiment
Relevant detailed description of the present invention and technology contents, existing as follows with regard to accompanying drawings: at first consult Fig. 1, Fig. 1 is the structural representation of one embodiment of the present of invention.PCI test card in the present embodiment, signal generator, phaselocked loop and control circuit are made of a slice FPGA, the required signal of test that signal generator produces comprises measured signal, and the phaselocked loop that adopts FPGA itself the to have gate array that is used as delaying time carries out exporting after the phase shift to signal.Display unit is a slice LED.Described reference clock generator is made of quartz crystal oscillator, produces reference clock signal, and reference clock signal is used for frequency multiplication.This PCI test card is inserted in the PCI slot of computer system in use.The user can control FPGA by the application program in the computer system and produce test required clock signal and test signal, the suitable PCI equipment of FPGA here, another function of FPGA is to utilize its phaselocked loop that signal is carried out the phase place five equilibrium, and the steering order phaselocked loop carries out phase shift to signal, thereby realizes time-delay.Display unit shows the number of the reference clock phase shifts of current signal institute warp, also the number of reference clock phase place can be converted into time delay and the direct display delay time.
Have multichannel output as Fig. 2 for the phaselocked loop inside of one embodiment of the present of invention, each road is provided with corresponding phase-shift circuit.Be provided with the output of m road as the embodiment among Fig. 2, wherein the first via is with clock signal phase shift N/clock; The second the tunnel with clock signal phase shift N/two clocks, by that analogy until N/m clock of m road phase shift.Phaselocked loop is divided into the N branch with clock signal, and the value of this N is specifically determined according to the precision of test.The value of this m should satisfy makes it enough greatly so that can make system work as machine, and the m value should be as far as possible little on this basis, saves cost to simplify circuit.M should be less than N obviously.Phaselocked loop just can obtain different clock phase shift time delayed signals according to the different clock signal output circuit of the Instruction Selection of FPGA like this.Certainly in some other embodiment for simplify circuit or other purpose also can with clock signal not equal portions cut apart, for example the time-delay difference does not wait between the adjacent circuit.
In test, the tester can start the phaselocked loop phase shift function by application program, and the PC system informs that by pci bus FPGA begins to carry out the phase shift test.FPGA informs that on the one hand phaselocked loop begins to enable phase shift function, begins on the other hand ceaselessly to send data to the PC system.Application program can move a phase place to clock signal earlier forward or backward, increases one by one one by one afterwards.LED can show the number of current travel(l)ing phase.When the time of measured signal tolerance limit during less than the requiring of PCI agreement, system can work as machine automatically, and pci bus quits work.LED shows the number of travel(l)ing phase when machine always.
Present embodiment satisfies the PCI agreement with the hardware description language programming in FPGA, so the pci card of design can directly be inserted in the PCI slot, pci signal carries out phase shift processing and comparative analysis by FPGA.If test signal occurred by effectively becoming invalid situation under the situation of clock signal delay, operating system is worked as machine, has just measured corresponding Time Created of tolerance limit and retention time tolerance limit.
Followingly according to the test philosophy synoptic diagram method of testing provided by the invention is introduced, analyzes: at first see also Fig. 3, Fig. 3 is the test philosophy synoptic diagram of tolerance limit Time Created.Wherein, it as a rule is the minimum signal Time Created of PCI agreement regulation Time Created of the needs that mark among the figure; Be meant in the test process that system is when machine, according to definition Time Created, the time value of being surveyed the Time Created that when machine, provides; Be meant when pci clock does not pass through phase shift the Time Created that provides under the normal condition, according to definition Time Created, the time value of being surveyed; Difference Time Created of (when the machine state) when Time Created and invalidating signal when Time Created, tolerance limit was meant operate as normal.In the process of test tolerance limit Time Created, the fixing test signal, the clock signal that allows FPGA produce realizes phase shift forward through phase-locked loop circuit, when the number of the travel(l)ing phase in phaselocked loop reaches certain number, test signal is invalid by effectively becoming at rising edge clock, as clock signal being shown forward during phase shift 1/N among Fig. 3 respectively, test signal is effective at this rising edge clock signal, clock signal is forward during phase shift 2/N, test signal is still effective at this rising edge clock signal, forward during phase shift m/N, test signal is in the appearance of rising edge of clock signal invalid situation up to clock signal, and the test signal of this moment is exactly an invalid signals.So at this moment, the rising edge of invalid signals is exactly the minimum Time Created of signal up to the scope of this rising edge of clock signal, and test signal from clock signal through the original signal of phase shift to the time that invalid signals occurs be exactly the time of travel(l)ing phase the phaselocked loop, just Time Created tolerance limit.Like this, just measured tolerance limit Time Created of signal, also just correspondingly measured minimum Time Created.That is to say Time Created tolerance limit equal the clock signal of test signal when invalid the number of phase shift time delay of multiply by each phase place forward.Like this, if know clock signal when test signal is invalid the number of phase shift forward, just measured tolerance limit Time Created of signal, also just correspondingly measured minimum Time Created.
See also Fig. 4, Fig. 4 is the test philosophy synoptic diagram of retention time tolerance limit.Wherein, the retention time of the needs that mark among the figure as a rule is the minimum signal retention time of PCI agreement regulation; The retention time that provides when machine is meant in the test process, and system is when machine, according to retention time definition, the time value of being surveyed; The retention time that provides under the normal condition is meant when pci clock does not pass through phase shift, according to retention time definition, the time value of being surveyed; The retention time difference of (when the machine state) when retention time and invalidating signal when the retention time, tolerance limit was meant operate as normal.Measuring the retention time during tolerance limit, the fixing test signal, the enable clock signal is realized phase shift backward through phase-locked loop circuit, and is when the number of the travel(l)ing phase in phaselocked loop reaches certain number, invalid by effectively becoming in the test signal of certain rising edge clock.Clock signal is shown backward during phase shift 1/N among Fig. 4 respectively, test signal is effective at this rising edge clock signal, clock signal is backward during phase shift 2/N, test signal is still effective at this rising edge clock signal, up to clock signal backward during phase shift m/N, test signal is in the appearance of rising edge of clock signal invalid situation, and the test signal of this moment is exactly an invalid signals.The time that the number of the phase shift backward of the clock signal institute warp when at this moment, utilizing test signal invalid multiply by each phase delay can calculate the retention time tolerance limit of signal.Calculate test signal point ineffective time apart from the time period between the negative edge of this test signal, income value is the minimum hold time of signal.
The above introduction only is preferred embodiment of the present invention, can not limit scope of the invention process with this.The variation that is equal to that those skilled in the art in the present technique field are done according to the present invention, for example each step among the above embodiment is made up, or add components and parts beyond the components and parts that the present invention mentions, testing process is done equivalent variations or apparent and easy to know derivation, and the improvement known of those skilled in that art, all should still belong to the scope that patent of the present invention contains.
Claims (16)
1, a kind of PCI test card, it is characterized in that it comprises: reference clock generator, phaselocked loop, control circuit, reference clock generator produces reference clock signal, phaselocked loop is several phase places with this signal halves, and by its phase shift function with signal be shifted forward or backward one by one one or several phase places, the generation of control circuit control test signal and the direction of test signal displacement and the phase place number that moves.
2, PCI test card as claimed in claim 1 is characterized in that described control circuit has the test required measured signal of signal generator to produce; The required reference clock signal of test that described reference clock generator produces.
3, PCI test card as claimed in claim 1 is characterized in that control circuit can be controlled by the computer system that installs application program additional by the user.
4, PCI test card as claimed in claim 1 is characterized in that described test card also has a display unit showing the current signal number of institute's travel(l)ing phase forward or backward,
5, PCI test card as claimed in claim 4 is characterized in that described display unit can be with the time stack of each phase delay of being shifted and direct display delay time.
6, PCI test card as claimed in claim 4 is characterized in that several phase places that described reference clock is divided into are five equilibriums.
7, PCI test card as claimed in claim 6 is characterized in that described display unit can multiply by the number of phases that is shifted the time stack of delay and direct display delay time.
8, PCI test card as claimed in claim 1 or 2 is characterized in that described phaselocked loop and control circuit are made of programmable logic device (PLD); Reference clock generator is provided by crystal oscillator.
9, PCI test card as claimed in claim 8 is characterized in that described programmable logic device (PLD) is FPGA.
10, PCI test card as claimed in claim 4 is characterized in that described display unit is LED.
11, a kind of method of testing of pci system: it is characterized in that may further comprise the steps:
A. provide test signal and reference clock signal;
B. with phaselocked loop this reference clock signal is divided into several five equilibrium phase places;
C. the clock signal in the test signal is shifted forward one by one the five equilibrium phase place of or several reference clocks, till test signal is invalid;
D. write down the number of the phase place that clock signal moved forward in the test signal of test signal when invalid.
12, the time that the method for testing of pci system as claimed in claim 11, the number of the phase place that clock signal was shifted in the test signal when it is characterized in that utilizing test signal invalid multiply by each five equilibrium phase place can calculate tolerance limit Time Created of signal.
13, the method for testing of pci system as claimed in claim 11 is characterized in that calculating test signal point ineffective time apart from the time period between the next rising edge of clock signal, and income value is the minimum Time Created of signal.
14, a kind of method of testing of pci system is characterized in that may further comprise the steps:
A. provide test signal and reference clock signal;
B. with phaselocked loop this reference clock signal is divided into several five equilibrium phase places;
C. the clock signal in the test signal is moved one by one backward the five equilibrium phase place of or several reference clocks, till test signal is invalid;
D. write down test signal when invalid clock signal in the test signal the number of the phase place that moves backward.
15, the time that the method for testing of pci system as claimed in claim 14, the number of the phase place that clock signal was shifted when it is characterized in that utilizing test signal invalid in the test signal multiply by each phase delay can calculate the retention time tolerance limit of signal.
16, the method for testing of pci system as claimed in claim 14 is characterized in that calculating test signal point ineffective time apart from the time period of working as between the previous rising edge of clock signal, and income value is the minimum hold time of signal.
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| CNB2004100932021A CN100397356C (en) | 2004-12-17 | 2004-12-17 | PCI test card and test method thereof |
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| CNB2004100932021A CN100397356C (en) | 2004-12-17 | 2004-12-17 | PCI test card and test method thereof |
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| CN100397356C CN100397356C (en) | 2008-06-25 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944965A (en) * | 2009-07-01 | 2011-01-12 | 川崎微电子股份有限公司 | Do not using the method and apparatus that receives bursty data under the external detection RST |
| CN102214123A (en) * | 2010-04-02 | 2011-10-12 | 广达电脑股份有限公司 | Test method, computer device using test method and computer test system using test method |
| CN101666855B (en) * | 2009-05-06 | 2011-12-28 | 四川和芯微电子股份有限公司 | Universal test system and method of integrated circuit |
| CN102109875B (en) * | 2009-12-28 | 2015-05-20 | 北京普源精电科技有限公司 | Signal generator with pulse signal generation function, and method for generating pulse signal |
| US9203351B2 (en) | 2013-03-15 | 2015-12-01 | Megachips Corporation | Offset cancellation with minimum noise impact and gain-bandwidth degradation |
| CN105759195A (en) * | 2016-02-24 | 2016-07-13 | 复旦大学 | Setup-hold time test system and setup-hold time test method based on fine phase modulation |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3818843A1 (en) * | 1988-06-03 | 1989-12-07 | Standard Elektrik Lorenz Ag | METHOD AND CIRCUIT ARRANGEMENT FOR RECOVERY OF A BIT CLOCK FROM A RECEIVED DIGITAL MESSAGE SIGNAL |
| DE69804431T2 (en) * | 1997-12-22 | 2002-12-12 | Koninklijke Philips Electronics N.V., Eindhoven | AUSGANGSZEITBASISKORRELATOR |
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- 2004-12-17 CN CNB2004100932021A patent/CN100397356C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101666855B (en) * | 2009-05-06 | 2011-12-28 | 四川和芯微电子股份有限公司 | Universal test system and method of integrated circuit |
| CN101944965A (en) * | 2009-07-01 | 2011-01-12 | 川崎微电子股份有限公司 | Do not using the method and apparatus that receives bursty data under the external detection RST |
| CN101944965B (en) * | 2009-07-01 | 2014-11-05 | 株式会社巨晶片 | Method and apparatus for receiving burst data without using external detection signal |
| CN102109875B (en) * | 2009-12-28 | 2015-05-20 | 北京普源精电科技有限公司 | Signal generator with pulse signal generation function, and method for generating pulse signal |
| CN102214123A (en) * | 2010-04-02 | 2011-10-12 | 广达电脑股份有限公司 | Test method, computer device using test method and computer test system using test method |
| CN102214123B (en) * | 2010-04-02 | 2013-12-04 | 广达电脑股份有限公司 | Test method, computer device using test method and computer test system using test method |
| US9203351B2 (en) | 2013-03-15 | 2015-12-01 | Megachips Corporation | Offset cancellation with minimum noise impact and gain-bandwidth degradation |
| CN105759195A (en) * | 2016-02-24 | 2016-07-13 | 复旦大学 | Setup-hold time test system and setup-hold time test method based on fine phase modulation |
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| CN100397356C (en) | 2008-06-25 |
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Owner name: HUANDA COMPUTER (SHANGHAI) CO., LTD. Free format text: FORMER OWNER: SHANGHAI HUANDA COMPUTER TECHNOLOGY CO., LTD. Effective date: 20091127 |
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Effective date of registration: 20091127 Address after: No. three, 213 Road, Zhabei District, Shanghai Patentee after: MiTAC International Corp. Address before: No. 1486, building 2, Nanjing West Road, Shanghai, Jingan District Patentee before: Huanda Computer Science-Technology Co., Ltd., Shanghai |
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