CN103499739A - Frequency measurement method based on FPGA - Google Patents

Frequency measurement method based on FPGA Download PDF

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Publication number
CN103499739A
CN103499739A CN201310439616.4A CN201310439616A CN103499739A CN 103499739 A CN103499739 A CN 103499739A CN 201310439616 A CN201310439616 A CN 201310439616A CN 103499739 A CN103499739 A CN 103499739A
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CN
China
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signal
frequency
measurement
counter
counting
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CN201310439616.4A
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Chinese (zh)
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符云越
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浪潮电子信息产业股份有限公司
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Priority to CN201310439616.4A priority Critical patent/CN103499739A/en
Publication of CN103499739A publication Critical patent/CN103499739A/en

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Abstract

The invention provides a frequency measurement method based on an FPGA. A standard reference clock is adopted to count the number of pulses of a measured signal in a unit time (1s) and the number of the pulses of the measured signal in the unit time (1s) is the frequency of the signal. Due to the fact that the starting moment of a gate and the finishing moment of the gate are random for the signal, a pulse period quantization error can be produced, and measurement accuracy needs to be analyzed further: the pulse period of a signal to be measured is set to be Tx, the frequency is set to be Fx, and when the measuring time T equals to 1s, the measurement accuracy & meets the equation that &=Tx/T=1/Fx. The fact that measurement accuracy in a direct frequency measurement method is relevant to the frequency of the signal is known, the higher the frequency of the signal to be measured is, the higher the measurement accuracy is, and otherwise, the lower the frequency of the signal to be measured is, the lower the measurement accuracy is. The direct frequency measurement method is only suitable for measurement of the signal at the higher frequency and can not meet the demand that the measurement accuracy remains unchanged in the whole measurement frequency band. In order to overcome the defect of inaccuracy in low-frequency-band measurement, gating signals and the measured signal are used for carrying out dual control on enable signals of the counter, and therefore accuracy is improved.

Description

A kind of frequency measurement method based on FPGA
Technical field
The present invention relates to electric design automation (EDA) field, relate in particular to a kind of frequency measurement method based on FPGA or the method for designing of digital frequency meter.
Background technology
Be accompanied by the development of integrated circuit (IC) technology, electric design automation (EDA) becomes important design means gradually, has been widely used in many fields such as simulation and digital circuitry.Electric design automation is a kind of technology that realizes electric system or electronic product the Automation Design, the development of it and electronic technology, microelectric technique is closely related, it has absorbed most of newest research results of computer science, using high performance computing machine as workbench, promoted engineering development.
Digital frequency meter is a kind of basic surveying instrument.It is widely used and the fields such as space flight, electronics, observing and controlling.The frequency measurement with constant-precision methods such as employing have measuring accuracy and keep constant, the characteristics that do not change with the variation of measured signal.At first this paper summarized the general situation of development of EDA technology, connotation, the relative merits of FPGA/CPLD exploitation, and the history of VHDL language and advantage thereof, summarized eda software platform QUARTUS II; Then introduced the General Principle of frequency measurement, utilize the equal precision measurement principle, use the VHDL programming by FPGA, the 8 bit digital formula equal precision frequency meters that utilized FPGA (field programmable gate array) chip design, the measurement range of this frequency meter is 0-100MHZ, utilize QUARTUS II Integrated Development Environment edited, comprehensively, wave simulation, and download in the CPLD device, through side circuit, test, emulation and experimental result show, this frequency is in respect of higher practicality and reliability.
Summary of the invention
The purpose of this invention is to provide a kind of frequency measurement method based on FPGA.
The objective of the invention is to realize in the following manner, adopt the reference clock of a standard, in the inner umber of pulse to measured signal of unit interval (1s), counted, be the frequency of signal, because the starting and ending of gate is random for signal constantly, will have the quantization error of a recurrence interval, further analysis to measure accuracy: establishing the measured signal recurrence interval is Tx, frequency is Fx, when Measuring Time is T=1s, and accuracy of measurement accuracy of measurement &=Tx/T=1/Fx, the accuracy of measurement of known direct frequency measurement method is relevant with the frequency of signal: when the measured signal frequency is higher, accuracy of measurement is also higher, otherwise accuracy of measurement is also lower, the direct frequency measurement method is only suitable for the signal that survey frequency is higher, can not meet the remain unchanged requirement of frequency of measuring accuracy in whole measurement frequency range, the inaccurate problem of measuring for overcoming low-frequency range, employing gate-control signal and measured signal are carried out dual control to the enable signal of counter, improved accuracy, when gate-control signal is 1, enable signal is not 1, while only having the rising edge arrival of measured signal, Enable Pin just starts to send useful signal, two counters start counting simultaneously, when gate-control signal becomes 0, enable signal is not to change immediately, but when arriving, the next rising edge of measured signal just becomes 0, counter stops counting, therefore the error of measuring mostly is a standard time clock cycle most, when the signal that adopts 100MHz during as standard signal, error is 0.01 μ s to the maximum, concrete steps are as follows:
1) utilize serial bus data transmission method, calculate measured signal pulse number in p.s., require count enable signal TSTEN can produce the periodic signal of 1 second pulsewidth, and the ENA Enable Pin of each counter cnt10 of frequency meter is carried out to synchro control, when TSTEN is high level, allow counting; During low level, stop counting, and the number that keeps it to count, during stopping counting, at first need the upper jumping of a latch signal LOAD along the count value in front 1 second latchs in 32 latch REG32B by counter, and translate and stablize demonstration by outside code translator, after latch signal, must carry out zero clearing to counter by reset signal CLR_CNT, for the counting operation in next second is prepared;
2) when system works, the input signal of 1 Hz that pulse producer provides, carry out the conversion of signal through frequency measurement control signal generator, produce count signal, measured signal produces the square wave of same frequency by signal transformation circuit, send into counting module, counting module is counted the square wave of input, count results is sent in latch, guarantee that system stability shows data, show that decoder driver circuit converts the count results of binary representation to the decimal system result that can correspondingly show at liquid crystal display;
3) the frequency measurement with constant-precision method such as frequency meter employing, it is constant that measuring accuracy keeps, the variation with measured signal does not change, under the requirement of Quick Measurement, guarantee the frequency measurement of degree of precision, must adopt higher standard-frequency signal, single-chip microcomputer is subject to the restriction of clock frequency own and some ordering calculations, frequency measurement speed is slower, can't meet high speed, high-precision frequency measurement requirement; And adopt high integration, on-site programmable gate array FPGA at a high speed to provide assurance for realizing high speed, high-precision frequency measurement;
Be not fixing value the gate time of 4) equal precision measurement method, but the integral multiple in measured signal cycle, with measured signal, synchronize, therefore, keep away except measured signal is counted to produce ± 1 word error, and reached the equal precision measurement in whole test frequency range, in measuring process, there are two counters respectively standard signal and measured signal to be counted simultaneously, given first gate opening signal, it is preset gate rising edge signal, this hour counter does not start counting, but the rising edge signal of by the time measured signal is while arriving, counter just really starts counting, then preset closing gate signal, be the negative edge signal then, counter does not stop counting immediately, but the rising edge signal of by the time measured signal just finishes counting while arriving, complete the one-shot measurement process, can find out, actual gate time t with preset gate time t1 strictly do not equate, but difference is no more than the one-period of measured signal,
5) etc., in the Precision Measuring Frequency method, CNT1 and CNT2 are two controllable counters, and standard-frequency signal is from the input end of clock CLK input of CNT1; Measured signal after shaping is from the input end of clock CLK input of CNT2, when preset gate-control signal is high level, the rising edge signal of the measured signal after shaping starts CNT1 and CNT2 by the Q end of d type flip flop simultaneously, CNT1, CNT2 are counted standard-frequency signal and the measured signal after shaping simultaneously, are respectively N swith N x, when the preset gate signal when being low level, the rising edge signal of the rear measured signal come will make two counters close simultaneously, and measured frequency is (F s/ N s) * NX, equal precision measurement method measuring accuracy is relevant with the standard frequency of preset gate width, with the frequency-independent of measured signal, in the situation that the preset gate time is identical with conventional frequency measurement gate time and the measured signal frequency is different, the measuring accuracy of equal precision measurement method is constant;
6) error analysis:being located at once actual gate time t Counter is Nx to the count value of measured signal, to the count value of standard signal, is Ns.The frequency of standard signal is fs, and the frequency of measured signal is suc as formula (2-1):
fx=(Nx/Ns)·fs???????????????????????????????(2-1)
From formula 1-1, if ignore the frequently error of fs of mark, wait the issuable relative error of Precision Measuring Frequency suc as formula (2-2):
δ=(|fxe-fx|/fxe)×100%???????????????????????????(2-2)
The exact value that wherein fxe is the measured signal frequency;
In measurement, because the start-stop time of fx counting is all that rising edge by this signal triggers, in gate time t to the counting Nx of fx error free (t=NxTx); The counting Ns of fs is differed at most to the error of a number, | Δ Ns|≤1, its survey frequency is suc as formula (2-3):
fxe=[Nx/(Ns+ΔNs)]·fs??????????????????????????(2-3)
By formula (2-1) and (2-3) substitution formula (2-2), and arrange suc as formula (2-4):
δ=|ΔNs|/Ns≤1/Ns=1/(t·fs)????????????????????????(2-4)
By above formula, found out, the size of the relative error of survey frequency and measured signal frequency is irrelevant, only relevant with the standard signal frequency with gate time, has realized the equal precision measurement of whole test frequency range, gate time is longer, standard frequency is higher, and the relative error of frequency measurement is just less, and the high frequency crystal oscillation device that standard frequency can be high by the good precision of degree of stability produces, guaranteeing under the constant prerequisite of measuring accuracy, improve the standard signal frequency, can make shorten gate time, improve test speed;
7) overall system design is as follows:
When system works, the input signal of the 100MHz provided by system clock, through signal source module, first by 100 frequency divisions, produce the clock signal of 1MHZ, again the clock signal frequency division of 1MHZ is produced to multi-frequency output, wherein the output frequency of 1HZ is used as the clock input of control module, the output frequency of 7812HZ is used as the clock input of display module, the count enable signal testen and the reset signal clr that by control module, are produced are controlled counting module, and by the latch signal load of its generation, latch module is controlled, once count enable signal is high level, and rising edge clock arrives, counter just starts normal counting, reset signal arrives and counts zero clearing, and when latch signal is high level, data just are latched device and latch, then the data that latch being outputed to display module shows, data latch the assurance system can stablize the demonstration data, display is partly used 1602 liquid crystal displays, digital frequency meter is comprised of 5 parts, respectively: frequency divider, gating circuit, counter, latch and display,
Wherein: according to the system principle of digital frequency meter, gate_control control signal generator, the count enable signal gate_control of gate_control can produce a periodic signal that 1 s is wide, and the ENA Enable Pin of each counter couter of frequency meter is carried out to synchro control: stop counting while when the gate_control high level, allowing counting, low level;
Flip_latch is latch, when the rising edge of signal load, immediately the data of the input port of module is latched into the inside of flip_latch, and by the output terminal output of flip_latch, then, 1062 liquid crystal displays outputs.Used latch here, benefit is the stable data that show, can constantly not glimmer due to periodic reset signal; Counter is decade counter, has a clock to enable input end ENA, for the lock count value.Allow counting when high level, forbid counting during low level.Eight decade counter counter are cascaded up and realize 8 decimal system tally functions [2,7].LCD_Driver is seven sections coding display driving circuits, the result of frequency counting is translated into to the corresponding arabic numeral that can show on charactron, is convenient to read the result of measurement;
In order to realize systemic-function, there are the problem of a work schedule in frequency measurement control signal generator gate_control, counter counter, latch flip_latch, during design, need to consider;
The top-level block diagram main.bdf of 8 bit digital frequency meters, design realizes comprising signal source module F1MHZ, CNT, frequency meter module FREQ and the large module of display module LCD_Drive tri-, below introduces respectively structure and the implementation method of three modules;
signal source module
Signal source is gate-control signal in order to produce 1MHz and frequency-fixed signal to be measured, and to input system clock clk(50MHz) carry out the module of frequency division, design source code gate_control.v is to input system clock clk(50MHz) carry out frequency division and produce the 1MHz signal;
frequency divider
The 1MHZ signal that CLK is the PIN1MHZ input, freq1 is the 1HZ signal of exporting to the control signal generator;
frequency measurement control signal generator
The effect of control module is to produce the needed various control signals of frequency measurement, the standard input clock of control signal is 1HZ, every two clock period are carried out a frequency measurement, the individual control signal that this module produces is for when each measurement starts, counter is resetted, to remove the result of measuring last time, this reset signal high level is effective, continue the time of half clock period, fdiv allows signal for counting, at the rising edge moment of fdiv signal counting module, start the frequency of input signal is measured, Measuring Time is just a clock period, be just in time unit interval 1s, in at this moment, the umber of pulse of measured signal is counted, be the frequency of signal, then value is latched, and deliver to charactron and show, the benefit that latch is set is to make the data stabilization shown, can constantly not glimmer due to periodic reset signal, when measuring beginning each time, all must be again to counter clear 0,
Latch
The latch module also is absolutely necessary, after the measurement module measurement completes, in the rising edge of load signal constantly is latched into register by measured value, then output to display module, latch has been the effect that data keep, and it will be saved in data to trigger or reset next time, the latch module is that master-slave flip-flop forms, exchanged for storing data, data stabilization is got off and keep a period of time not change, until new data are replaced it;
Program is for realizing the function of latch module, and when the rising edge of latch signal load arrives, latch is latched into register by measured value, then output to display module, latching output is not to carry out immediately, but has experienced an of short duration time delay, and this is because hardware causes;
decade counter
Counter module is with the asynchronous resetting end by 8, the counting module cascade that the mould of carry signal output is 10 forms, carry out the realization of element exampleization by counter, the special character of this decade counter is, there is a clock to enable input end ENA, for the lock count device, when the high level counting allows, counter inhibit during low level, counter module is for being counted the pulse of input signal, this module must have the ports such as counting permission, asynchronous resetting, so that control module is controlled it;
program modulethe function realized is the 10 system countings with Enable Pin, program require to only have when the Enable Pin signal be that the high level hour counter could work, the rising edge arrival hour counter of each clock adds 1, because what will realize here is 10 system countings, so when counting down to 10 hour counter zero clearings, produce carry signal simultaneously, the carry signal here is only a pulse signal, once counting becomes 1 from 10, pulse signal becomes low level immediately, this counter also should be with reset signal simultaneously, once reset signal is high level, counter is zero clearing immediately;
display modulethe LCD1602 LCDs:
the LCDs driver modulemodel is LCD1602.
The invention has the beneficial effects as follows: the invention provides the inaccurate problem of measuring for overcoming low-frequency range, employing gate-control signal and measured signal are carried out dual control to the enable signal of counter, have greatly improved accuracy.When gate-control signal is 1, enable signal is not 1, and while only having the rising edge arrival of measured signal, Enable Pin just starts to send useful signal, and two counters start counting simultaneously.When gate-control signal becomes 0, enable signal is not to change immediately, but just becomes 0 when the next rising edge of measured signal arrives, and counter stops counting.Therefore the error of measuring mostly is a standard time clock cycle most.When the signal that adopts 100MHz, during as standard signal, error is 0.01 μ s to the maximum.
The accompanying drawing explanation
Fig. 1 waits Precision Measuring Frequency principle oscillogram figure;
Fig. 2 waits Precision Measuring Frequency to realize schematic diagram;
Fig. 3 is the theory diagram of digital frequency meter;
Fig. 4 is fdiv encapsulation figure;
Fig. 5 is the sequential analogous diagram of fdiv;
Fig. 6 is the encapsulation figure of flip_latch;
Fig. 7 is the sequential analogous diagram of flip_latch;
Fig. 8 is the encapsulation figure of counter;
fig. 9it is the sequential analogous diagram of CNT10;
Figure 10 is LCD1602 LCDs driver module structural drawing;
Figure 11 is the analogous diagram of LCD1602 LCDs driver module.
Embodiment
With reference to Figure of description, method of the present invention is described in detail below.
Deng the Precision Measuring Frequency method, be to grow up on the basis of direct frequency measurement method.Be not fixing value its gate time, but the integral multiple in measured signal cycle synchronize with measured signal, therefore, keeps away except to produce ± 1 word error of measured signal counting, and reached the equal precision measurement in whole test frequency range.Its measuring frequency principle is as shown in Fig. 2 .1.In measuring process, there are two counters respectively standard signal and measured signal to be counted simultaneously.Given first gate opening signal (preset gate rising edge), this hour counter does not start counting, but the rising edge of by the time measured signal is while arriving, counter just really starts counting.Then then, counter does not stop counting to preset closing gate signal (negative edge) immediately, but the rising edge of by the time measured signal just finishes counting while arriving, and completes the one-shot measurement process.Can find out, actual gate time t with preset gate time t1 strictly do not equate, but difference is no more than the one-period of measured signal.
Deng Precision Measuring Frequency principle oscillogram as shown in Figure 1:
Implementation method Deng Precision Measuring Frequency can be reduced to shown in Fig. 2.CNT1 and CNT2 are two controllable counters, and standard-frequency signal is from the input end of clock CLK input of CNT1; Measured signal after shaping is from the input end of clock CLK input of CNT2.When preset gate-control signal is high level, the rising edge of the measured signal after shaping starts CNT1 and CNT2 by the Q end of d type flip flop simultaneously.CNT1, CNT2 are counted standard-frequency signal and the measured signal after shaping simultaneously, are respectively N swith N x.When the preset gate signal when being low level, the rising edge of the rear measured signal come will make two counters close simultaneously, and measured frequency is (F s/ N s) * NX.Equal precision measurement method measuring accuracy is relevant with the standard frequency of preset gate width, with the frequency-independent of measured signal.In the situation that the preset gate time is identical with conventional frequency measurement gate time and the measured signal frequency is different, the measuring accuracy of equal precision measurement method is constant.Fig. 2 waits Precision Measuring Frequency to realize schematic diagram
Error analysis
Being located at once actual gate time t Counter is Nx to the count value of measured signal, to the count value of standard signal, is Ns.The frequency of standard signal is fs, and the frequency of measured signal is suc as formula (2-1):
fx=(Nx/Ns)·fs???????????????????????????????(2-1)
From formula 1-1, if ignore the frequently error of fs of mark, wait the issuable relative error of Precision Measuring Frequency suc as formula (2-2):
δ=(|fxe-fx|/fxe)×100%???????????????????????????(2-2)
The exact value that wherein fxe is the measured signal frequency.
In measurement, because the start-stop time of fx counting is all that rising edge by this signal triggers, in gate time t to the counting Nx of fx error free (t=NxTx); The counting Ns of fs is differed at most to the error of a number, | Δ Ns|≤1, its survey frequency is suc as formula (2-3):
fxe=[Nx/(Ns+ΔNs)]·fs??????????????????????????(2-3)
By formula (2-1) and (2-3) substitution formula (2-2), and arrange suc as formula (2-4):
δ=|ΔNs|/Ns≤1/Ns=1/(t·fs)????????????????????????(2-4)
As can be seen from the above equation, the size of the relative error of survey frequency and measured signal frequency is irrelevant, only relevant with the standard signal frequency with gate time, has realized the equal precision measurement of whole test frequency range.Gate time is longer, and standard frequency is higher, and the relative error of frequency measurement is just less.Standard frequency can produce by high frequency crystal oscillation device good by degree of stability, that precision is high, guaranteeing to improve the standard signal frequency under the constant prerequisite of measuring accuracy, can make shorten gate time, improves test speed.
the overall design of system
When system works, the input signal of the 100MHz provided by system clock, through signal source module, first by 100 frequency divisions, produce the clock signal of 1MHZ, again the clock signal frequency division of 1MHZ is produced to multi-frequency output, wherein the output frequency of 1HZ is used as the clock input of control module, the output frequency of 7812HZ is used as the clock input of display module, the count enable signal testen and the reset signal clr that by control module, are produced are controlled counting module, and by the latch signal load of its generation, latch module is controlled, once count enable signal is high level, and rising edge clock arrives, counter just starts normal counting, reset signal arrives and counts zero clearing, and when latch signal is high level, data just are latched device and latch, then the data that latch being outputed to display module shows, data latch the assurance system can stablize the demonstration data, display is partly used 1602 liquid crystal displays.
The theory diagram of digital frequency meter as shown in Figure 3.Mainly by 5 parts, formed, respectively: frequency divider, gating circuit, counter, latch and display.
According to the system principle of digital frequency meter, gate_control control signal generator.The count enable signal gate_control of gate_control can produce a periodic signal that 1 s is wide, and the ENA Enable Pin of each counter couter of frequency meter is carried out to synchro control: stop counting while when the gate_control high level, allowing counting, low level.
Flip_latch is latch.When the rising edge of signal load, immediately the data of the input port of module are latched into the inside of flip_latch, and by the output terminal output of flip_latch, then, 1062 liquid crystal displays outputs.Used latch here, benefit is to stablize the demonstration data, can the constantly flicker due to periodic reset signal.Counter is decade counter.There is a clock to enable input end ENA, for the lock count value.Allow counting when high level, forbid counting during low level.Eight decade counter counter are cascaded up and realize 8 decimal system tally functions [2,7].LCD_Driver is seven sections coding display driving circuits, the result of frequency counting can be translated into to the corresponding arabic numeral that can show on charactron, is convenient to read the result of measurement.
In order to realize systemic-function, there are the problem of a work schedule in frequency measurement control signal generator gate_control, counter counter, latch flip_latch, during design, need to consider.
The top-level block diagram of 8 bit digital frequency meters (main.bdf), design realizes comprising signal source module (F1MHZ, CNT), frequency meter module (FREQ) and the large module of display module (LCD_Drive) three.Below introduce respectively structure and the implementation method of three modules.
signal source module
Signal source is gate-control signal in order to produce 1MHz and frequency-fixed signal to be measured, and to input system clock clk(50MHz) carry out the module of frequency division, design source code gate_control.v is to input system clock clk(50MHz) carry out frequency division and produce the 1MHz signal.
frequency divider
The encapsulation figure of fdiv is as Fig. 4, and in figure, CLK is the 1MHZ signal that PIN1MHZ inputs, and freq1 is the 1HZ signal of exporting to the control signal generator.
The work schedule analogous diagram of fdiv as shown in Figure 5.
frequency measurement control signal generator
The effect of control module is to produce the needed various control signals of frequency measurement.The standard input clock of control signal is 1HZ, and every two clock period are carried out a frequency measurement.The individual control signal that this module produces, for when each measurement starts, is resetted to counter, and to remove the result of measuring last time, this reset signal high level is effective, continues the time of half clock period.Fdiv allows signal for counting, at the rising edge moment of fdiv signal counting module, start the frequency of input signal is measured, Measuring Time is just a clock period (just in time for unit interval 1s), at this moment between in the umber of pulse of measured signal counted, be the frequency of signal.Then value is latched, and deliver to charactron and show.The benefit that latch is set is to make the data stabilization shown, can the constantly flicker due to periodic reset signal.When measuring beginning each time, all must be again to counter clear 0.
latch
The latch module also is absolutely necessary, and after the measurement module measurement completes, in the rising edge of load signal constantly is latched into register by measured value, then outputs to display module.Latch has been the effect that data keep, and it will be saved in data to trigger or reset next time.Mainly that master-slave flip-flop forms.Exchanged for storing data, data stabilization is got off and keep a period of time not change, until new data are replaced it.
The encapsulation of latch flip_latch is as Fig. 6.Clk connects the latch_en end of gate_control.
The working timing figure of latch flip_latch as shown in Figure 7.
This program is for realizing the function of latch module, but its program is quite simple, and when the rising edge of latch signal load arrives, latch is latched into register by measured value, then outputs to display module.But from analogous diagram 3.9, can significantly find out, latching output is not to carry out immediately, but has experienced an of short duration time delay, and this is because hardware causes.
decade counter
Counter module be by 8 with the asynchronous resetting end, the counting module cascade that the mould of carry signal output is 10 forms.Carry out the realization of element exampleization by (counter).The special character of this decade counter is to have a clock to enable input end ENA, for the lock count device.When the high level counting allows, counter inhibit during low level.Counter module is for the pulse of input signal is counted, and this module must have the ports such as counting permission, asynchronous resetting, so that control module is controlled it.
As shown in Figure 8, wherein CLR is the couter_clr end that resets and meet gate_control in the encapsulation of counter, and EN meets the couter_en end of gate_control, Q[3..0] meet the A[3...0 of latch] end.
The work schedule analogous diagram of the decade counter counter that has clock to enable, as shown in Figure 9.
The function that this program module realizes is the 10 system countings with Enable Pin.Program require to only have when the Enable Pin signal be that the high level hour counter could work, the rising edge arrival hour counter of each clock adds 1, because what will realize here is 10 system countings, so when counting down to 10 hour counter zero clearings, produce carry signal simultaneously, the carry signal here is only a pulse signal, once counting becomes 1 from 10, pulse signal becomes low level immediately.This counter also should be with reset signal simultaneously, once reset signal is high level, counter is zero clearing immediately.
the brief introduction of display module LCD1602 LCDs:
1. brief introduction
The industry character mode lcd can show i.e. 32 characters of 16x02 simultaneously.(16 row 2 row)
Annotate: for the convenience meaned, hereinafter all with 1 expression high level, 0 means level.
2. pin function
1602 adopt 16 pin interfaces of standard, wherein:
The 1st pin: VSS is power supply ground;
The 2nd pin: VDD connects the 5V positive source;
The 3rd pin: V0 is liquid crystal display contrast adjustment end, and while connecing positive supply, contrast is the most weak, contrast the highest (can produce " ghost " when contrast is too high, during use, can adjust contrast by the potentiometer of a 10K) during earthing power supply;
The 4th pin: RS is that register is selected, selection instruction register while during high level 1, selecting data register, low level 0;
The 5th pin: RW is reading writing signal line, carries out read operation during high level (1), carries out write operation during low level (0);
The 6th pin: E (or EN) end is for enabling (enable) end;
7th~14 pin: D0~D7 is 8 bi-directional data ends;
15th~16 pin: empty pin or back of the body lamp power supply.The 15 instep light positive utmost points, 16 instep light negative poles.
3. operation is controlled
The operation control table
Operation
Read states
Write command
Read data
Write data
Input
RS=0,RW=1,E=1
RS=0,RW=0,
D0 ~ 7=order code, the E=H pulse
RS=1,RW=1,E=1
RS=1,RW=0,
D0 ~ 7=data, the E=H pulse.
4. character set
The character generation storer (CGROM) of 1602 Liquid Crystal Module inside has been stored 160 different dot character figures, these characters have: the capital and small letter of arabic numeral, English alphabet, symbol commonly used and Japanese ideogram etc., each character has a fixing code, such as the code of English alphabet " A " of capitalization is 01000001B(41H), during demonstration, module shows the dot character figure in the 41H of address, and we just can see letter " A ".
Because 1602 identifications is ASCII character, test can be used the ASCII character indirect assignment, in mcu programming, can also use character type constant or variable assignments, as ' A '.
Below 1602 16 system ASCII character table addresses:
When reading, first read those row of the left side, then read top that row, as: an exclamation mark! ASCII be 0x21, the ASCII of letter b is that the 0x42(front adds 0x and means sexadecimal).
[editing this section] instruction set
1602 by 8 bit data end transmission data and the instructions of D0 ~ D7.
Display mode arranges: (initialization)
0011 0000 [0x38] arranges 16 * 2 and shows, 5 * 7 dot matrix, 8 bit data interface;
Display switch and cursor setting: (initialization)
0000 1DCB D shows that (1 is effective), C cursor show (1 is effective), B cursor flicker (1 is effective)
(after reading or writing a character, address pointer adds 1 &amp to 0000 01NS N=1; Cursor adds 1),
(after reading or writing a character, address pointer subtracts 1 &amp to N=0; Cursor subtracts 1),
S=1 and N=1 (after writing a character, whole screen display show move to left)
S=0 is after writing a character, and whole screen display is shown and do not moved
Data pointer arranges:
The data first address is 80H, so data address is 80H+ address code (0-27H, 40-67H)
Other settings:
01H (showing cls, data pointer=0, all demonstrations=0); 02H (showing carriage return, data pointer=0).
LCD1602 LCDs driver module, structure is as shown in figure 11;
Latch_en meets the latch_en in gate_control, and clk_LCD meets clk.
Simulation parameter: be regularly that 10 measurement frequency input signals are that 25Khz/10=2.5KHZ LCD is shown as 10HZ for the 1/25KHZ count value.
Except the described technical characterictic of instructions, be the known technology of those skilled in the art.

Claims (1)

1. the frequency measurement method based on FPGA, it is characterized in that comprising: the reference clock that adopts a standard, in the inner umber of pulse to measured signal of unit interval (1s), counted, be the frequency of signal, because the starting and ending of gate is random for signal constantly, the quantization error of a recurrence interval will be had, further analysis to measure accuracy: establishing the measured signal recurrence interval is Tx, frequency is Fx, when Measuring Time is T=1s, accuracy of measurement accuracy of measurement &=Tx/T=1/Fx, the accuracy of measurement of known direct frequency measurement method is relevant with the frequency of signal: when the measured signal frequency is higher, accuracy of measurement is also higher, otherwise accuracy of measurement is also lower, the direct frequency measurement method is only suitable for the signal that survey frequency is higher, can not meet the remain unchanged requirement of frequency of measuring accuracy in whole measurement frequency range, the inaccurate problem of measuring for overcoming low-frequency range, employing gate-control signal and measured signal are carried out dual control to the enable signal of counter, improved accuracy, when gate-control signal is 1, enable signal is not 1, while only having the rising edge arrival of measured signal, Enable Pin just starts to send useful signal, two counters start counting simultaneously, when gate-control signal becomes 0, enable signal is not to change immediately, but when arriving, the next rising edge of measured signal just becomes 0, counter stops counting, therefore the error of measuring mostly is a standard time clock cycle most, when the signal that adopts 100MHz during as standard signal, error is 0.01 μ s to the maximum, concrete steps are as follows:
1) utilize serial bus data transmission method, calculate measured signal pulse number in p.s., require count enable signal TSTEN can produce the periodic signal of 1 second pulsewidth, and the ENA Enable Pin of each counter cnt10 of frequency meter is carried out to synchro control, when TSTEN is high level, allow counting; During low level, stop counting, and the number that keeps it to count, during stopping counting, at first need the upper jumping of a latch signal LOAD along the count value in front 1 second latchs in 32 latch REG32B by counter, and translate and stablize demonstration by outside code translator, after latch signal, must carry out zero clearing to counter by reset signal CLR_CNT, for the counting operation in next second is prepared;
2) when system works, the input signal of 1 Hz that pulse producer provides, carry out the conversion of signal through frequency measurement control signal generator, produce count signal, measured signal produces the square wave of same frequency by signal transformation circuit, send into counting module, counting module is counted the square wave of input, count results is sent in latch, guarantee that system stability shows data, show that decoder driver circuit converts the count results of binary representation to the decimal system result that can correspondingly show at liquid crystal display;
3) the frequency measurement with constant-precision method such as frequency meter employing, it is constant that measuring accuracy keeps, the variation with measured signal does not change, under the requirement of Quick Measurement, guarantee the frequency measurement of degree of precision, must adopt higher standard-frequency signal, single-chip microcomputer is subject to the restriction of clock frequency own and some ordering calculations, frequency measurement speed is slower, can't meet high speed, high-precision frequency measurement requirement; And adopt high integration, on-site programmable gate array FPGA at a high speed to provide assurance for realizing high speed, high-precision frequency measurement;
Be not fixing value the gate time of 4) equal precision measurement method, but the integral multiple in measured signal cycle, with measured signal, synchronize, therefore, keep away except measured signal is counted to produce ± 1 word error, and reached the equal precision measurement in whole test frequency range, in measuring process, there are two counters respectively standard signal and measured signal to be counted simultaneously, given first gate opening signal, it is preset gate rising edge signal, this hour counter does not start counting, but the rising edge signal of by the time measured signal is while arriving, counter just really starts counting, then preset closing gate signal, be the negative edge signal then, counter does not stop counting immediately, but the rising edge signal of by the time measured signal just finishes counting while arriving, complete the one-shot measurement process, can find out, actual gate time t with preset gate time t1 strictly do not equate, but difference is no more than the one-period of measured signal,
5) etc., in the Precision Measuring Frequency method, CNT1 and CNT2 are two controllable counters, and standard-frequency signal is from the input end of clock CLK input of CNT1; Measured signal after shaping is from the input end of clock CLK input of CNT2, when preset gate-control signal is high level, the rising edge signal of the measured signal after shaping starts CNT1 and CNT2 by the Q end of d type flip flop simultaneously, CNT1, CNT2 are counted standard-frequency signal and the measured signal after shaping simultaneously, are respectively N swith N x, when the preset gate signal when being low level, the rising edge signal of the rear measured signal come will make two counters close simultaneously, and measured frequency is (F s/ N s) * NX, equal precision measurement method measuring accuracy is relevant with the standard frequency of preset gate width, with the frequency-independent of measured signal, in the situation that the preset gate time is identical with conventional frequency measurement gate time and the measured signal frequency is different, the measuring accuracy of equal precision measurement method is constant;
6) error analysis:being located at once actual gate time t Counter is Nx to the count value of measured signal, to the count value of standard signal, is Ns, and the frequency of standard signal is fs, and the frequency of measured signal is suc as formula (2-1):
fx=(Nx/Ns)·fs???????????????????????????????(2-1)
From formula 1-1, if ignore the frequently error of fs of mark, wait the issuable relative error of Precision Measuring Frequency suc as formula (2-2):
δ=(|fxe-fx|/fxe)×100%???????????????????????????(2-2)
The exact value that wherein fxe is the measured signal frequency;
In measurement, because the start-stop time of fx counting is all that rising edge by this signal triggers, in gate time t to the counting Nx of fx error free (t=NxTx); The counting Ns of fs is differed at most to the error of a number, | Δ Ns|≤1, its survey frequency is suc as formula (2-3):
fxe=[Nx/(Ns+ΔNs)]·fs??????????????????????????(2-3)
By formula (2-1) and (2-3) substitution formula (2-2), and arrange suc as formula (2-4):
δ=|ΔNs|/Ns≤1/Ns=1/(t·fs)????????????????????????(2-4)
By above formula, found out, the size of the relative error of survey frequency and measured signal frequency is irrelevant, only relevant with the standard signal frequency with gate time, has realized the equal precision measurement of whole test frequency range, gate time is longer, standard frequency is higher, and the relative error of frequency measurement is just less, and the high frequency crystal oscillation device that standard frequency can be high by the good precision of degree of stability produces, guaranteeing under the constant prerequisite of measuring accuracy, improve the standard signal frequency, can make shorten gate time, improve test speed;
7) overall system design is as follows:
When system works, the input signal of the 100MHz provided by system clock, through signal source module, first by 100 frequency divisions, produce the clock signal of 1MHZ, again the clock signal frequency division of 1MHZ is produced to multi-frequency output, wherein the output frequency of 1HZ is used as the clock input of control module, the output frequency of 7812HZ is used as the clock input of display module, the count enable signal testen and the reset signal clr that by control module, are produced are controlled counting module, and by the latch signal load of its generation, latch module is controlled, once count enable signal is high level, and rising edge clock arrives, counter just starts normal counting, reset signal arrives and counts zero clearing, and when latch signal is high level, data just are latched device and latch, then the data that latch being outputed to display module shows, data latch the assurance system can stablize the demonstration data, display is partly used 1602 liquid crystal displays, digital frequency meter is comprised of 5 parts, respectively: frequency divider, gating circuit, counter, latch and display,
Wherein: according to the system principle of digital frequency meter, gate_control control signal generator, the count enable signal gate_control of gate_control can produce a periodic signal that 1 s is wide, and the ENA Enable Pin of each counter couter of frequency meter is carried out to synchro control: stop counting while when the gate_control high level, allowing counting, low level;
Flip_latch is latch, when the rising edge of signal load, immediately the data of the input port of module are latched into the inside of flip_latch, and exported by the output terminal of flip_latch, then, 1062 liquid crystal display outputs, used latch here, benefit is the stable data that show, can constantly not glimmer due to periodic reset signal;
Counter is decade counter, has a clock to enable input end ENA, for the lock count value, allows counting when high level, forbids counting during low level, and eight decade counter counter are cascaded up and realize 8 decimal system tally functions [2,7];
LCD_Driver is seven sections coding display driving circuits, the result of frequency counting is translated into to the corresponding arabic numeral that can show on charactron, is convenient to read the result of measurement;
In order to realize systemic-function, there are the problem of a work schedule in frequency measurement control signal generator gate_control, counter counter, latch flip_latch, during design, need to consider;
The top-level block diagram main.bdf of 8 bit digital frequency meters, design realizes comprising signal source module F1MHZ, CNT, frequency meter module FREQ and the large module of display module LCD_Drive tri-, below introduces respectively structure and the implementation method of three modules;
signal source module
Signal source is gate-control signal in order to produce 1MHz and frequency-fixed signal to be measured, and to input system clock clk(50MHz) carry out the module of frequency division, design source code gate_control.v is to input system clock clk(50MHz) carry out frequency division and produce the 1MHz signal;
frequency divider
The 1MHZ signal that CLK is the PIN1MHZ input, freq1 is the 1HZ signal of exporting to the control signal generator;
frequency measurement control signal generator
The effect of control module is to produce the needed various control signals of frequency measurement, the standard input clock of control signal is 1HZ, every two clock period are carried out a frequency measurement, the individual control signal that this module produces is for when each measurement starts, counter is resetted, to remove the result of measuring last time, this reset signal high level is effective, continue the time of half clock period, fdiv allows signal for counting, at the rising edge moment of fdiv signal counting module, start the frequency of input signal is measured, Measuring Time is just a clock period, be just in time unit interval 1s, in at this moment, the umber of pulse of measured signal is counted, be the frequency of signal, then value is latched, and deliver to charactron and show, the benefit that latch is set is to make the data stabilization shown, can constantly not glimmer due to periodic reset signal, when measuring beginning each time, all must be again to counter clear 0,
Latch
The latch module also is absolutely necessary, after the measurement module measurement completes, in the rising edge of load signal constantly is latched into register by measured value, then output to display module, latch has been the effect that data keep, and it will be saved in data to trigger or reset next time, the latch module is that master-slave flip-flop forms, exchanged for storing data, data stabilization is got off and keep a period of time not change, until new data are replaced it;
Program is for realizing the function of latch module, and when the rising edge of latch signal load arrives, latch is latched into register by measured value, then output to display module, latching output is not to carry out immediately, but has experienced an of short duration time delay, and this is because hardware causes;
decade counter
Counter module is with the asynchronous resetting end by 8, the counting module cascade that the mould of carry signal output is 10 forms, carry out the realization of element exampleization by counter, the special character of this decade counter is, there is a clock to enable input end ENA, for the lock count device, when the high level counting allows, counter inhibit during low level, counter module is for being counted the pulse of input signal, this module must have the ports such as counting permission, asynchronous resetting, so that control module is controlled it;
program modulethe function realized is the 10 system countings with Enable Pin, program require to only have when the Enable Pin signal be that the high level hour counter could work, the rising edge arrival hour counter of each clock adds 1, because what will realize here is 10 system countings, so when counting down to 10 hour counter zero clearings, produce carry signal simultaneously, the carry signal here is only a pulse signal, once counting becomes 1 from 10, pulse signal becomes low level immediately, this counter also should be with reset signal simultaneously, once reset signal is high level, counter is zero clearing immediately.
CN201310439616.4A 2013-09-25 2013-09-25 Frequency measurement method based on FPGA CN103499739A (en)

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Application publication date: 20140108