CN102109875B - Signal generator with pulse signal generation function, and method for generating pulse signal - Google Patents
Signal generator with pulse signal generation function, and method for generating pulse signal Download PDFInfo
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- CN102109875B CN102109875B CN200910243149.1A CN200910243149A CN102109875B CN 102109875 B CN102109875 B CN 102109875B CN 200910243149 A CN200910243149 A CN 200910243149A CN 102109875 B CN102109875 B CN 102109875B
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Abstract
The invention discloses a signal generator. The signal generator comprises a control system, a waveform processing unit 24 and a waveform output end 29 which are connected in series sequentially; the waveform processing unit comprises an internal clock unit 244 used for generating an internal clock signal, a coarse pulse width unit 242, a delay unit 243 and a pulse generation unit 245; the control system is used for calculating a first time length and a second time length according to a pulse width value and sending the first time length and the second time length to the waveform processing unit; the coarse pulse width unit generates a first signal edge and a second signal edge; an interval between the first signal edge and the second signal edge is the first time length; the delay unit is trigged by the second signal edge to delay the second time length and then output a third signal edge; and the pulse generation unit generates a pulse according to the first signal edge and the third signal edge. The width of the pulse generated by the signal generator is more accurate.
Description
Technical field
The present invention relates to a kind of signal generator, particularly a kind of can more accurately control to produce pulse signal pulsewidth direct digital synthesis technique (DDS, Direct Digital Frequency Synthesis) signal generator.
Background technology
Signal generator, as common driving source, has been widely used scientific research and Industrial Engineering field.A typical apply of signal generator is exactly simulate various signal in the lab, as the input stimulus of circuit under test and system, for the various performance index of test circuit under test and system provide simulated environment.Traditional signal generator is divided into four large classes by its signal waveform: (1) sinusoidal signal generator: be mainly used in the frequency characteristic of metering circuit and system, nonlinear distortion, gain and sensitivity etc.; (2) function (waveform) signal generator: produce some specific periodically function of time waveform (sine wave, square wave, triangular wave, sawtooth wave and pulsating wave) signal, except for except communication, instrument and automatic control system test, can also be widely used in other non-field of electric measurement; (3) pulse signal generator: the generator producing the adjustable rect.p. of width, amplitude and repetition frequency, can be used for the transient response of p-wire sexual system, or be used as the performance that simulating signal tests radar, multichannel communication multiple telecommunication and other pulse digit systems; (4) random signal generator: can be used for simulating the noise in actual operating conditions, introduces the random signal of generation and treats examining system, thus Analytical system performance; The additional known noise Signals & Systems internal noise of system under test (SUT) can to compare to measure noise figure; Sinusoidal or pulse signal can also be replaced, with Analytical system dynamic perfromance etc. by random signal.Wherein, pulse signal generator generally adopts traditional pulse duration modulation method adjustment pulse width.
Chinese invention patent application Publication Specification (publication number: CN101183824A, application number: 200710192911.9, denomination of invention: the method and apparatus for pulse-length modulation) discloses a kind of control circuit of duty ratio 100, please refer to Fig. 1, it comprises pulse width modulation circuit 110 and oscillator 140, and pulse width modulation circuit 110 receives timing signal U from oscillator 140
oSC140, to produce pulse width modulating signal 130, the voltage V namely in Fig. 1
pWM.Timing signal U
oSC140 can be voltage can be also electric current, and is periodic, and its cycle is T
oSC.Timing signal U
oSC140 in cycle T
oSCcoefficient k be low value, in cycle T
oSCresidual coefficient be high level.Pulse width modulating signal 130 is in cycle T
oSCcoefficient D be high level, D is dutycycle here, pulse width modulation circuit 110 also receive control electric current I
c120.Control electric current I
c120 regulate dutycycle D.
Please refer to Fig. 2, curve 200 represents dutycycle D how response limiting electric current I
cand change.Dutycycle D is less than I at control electric current
btime be maximal value D
b, and be greater than I at control electric current
atime be minimum value D
a.When control electric current is value I
x, it is at I
aand I
bbetween time, dutyfactor value is D
x, it is at D
aand D
bbetween.In control electric current I
aand I
bbetween, the gain of pulse-width modulator is slope-m.In fig. 2, pulse-width modulator gain m has the unit of amperage reciprocal.
Please with reference to Fig. 3 and Fig. 4, control circuit of duty ratio 300 is the specific embodiment of control circuit of duty ratio 100, and it can produce the response of similar curve 200.As shown in the figure, circuit 300 receives and controls electric current I
c120.Current source 305 is from control electric current I
ci is deducted in 120
b.At the input end of current mirror 352, transistor 310 receives and controls electric current I
c120 and come from and control the electric current I of electric current 305
bbetween difference.The transistor 310 and 315 of current mirror 352 has the intensity of the respective ratio of 1: M, is the product of input current and scale-up factor M to make image current 325.
Oscillator 150 provides gauge tap S
1the timing signal 340 of 378.When timing signal 340 is low value, switch S
1378 is closed with current charges capacitor C
d376, this electric current is the electric current I from current source 345
1with the electric current sum of the electric current by rectifier 354.When being timing from the difference between the electric current of current source 335 and image current 325, poor for this by the electric current of rectifier 354.When image current 325 is greater than the electric current from current source 335, be zero by the electric current of rectifier 354.Rectifier 354 comprises diode.
Capacitor C is compared by comparer 360
dvoltage V on 376
d356 and reference voltage V
rEF372.As voltage V
d356 are greater than reference voltage V
rEFwhen 372, the output 370 of comparer 360 is high level.As voltage V
d356 are less than reference voltage V
rEFwhen 372, the output 370 of comparer 360 is low value.
Delay circuit 366, for the rising edge of signal postponing to come self-oscillator 150, at Ben Chu, is the nonideal response for compensating comparer 360.Be received as the input with door 362 from the delay timing signal 358 of delay circuit 366 and the output 370 of comparer 360.With the output 374 gauge tap S of door 362
2384.Also be pulse width modulating signal 330 with the output 374 of door 362.When the output 374 with door 362 is high level, switch S
2384 is closed with current source 382 couples of capacitor C
d376 electric discharges.
Visible, control circuit of duty ratio 100 is by capacitor C
dvoltage V on 376
d356 produce pulse width modulating signal 330, due to capacitor C
dvoltage V on 376
d356 is analog quantity, and analog quantity is easily by ectocine, and as temperature impact, cause the dutycycle of pulse width modulating signal 330 inaccurate, namely pulse width is inaccurate.
Summary of the invention
Producing the inaccurate problem of pulse signal pulse width to solve prior art, the invention provides a kind of pulse width signal generator more accurately producing pulse signal.
Meanwhile, the present invention also provides a kind of pulse width pulse signal production method more accurately producing pulse signal.
A kind of signal generator, it comprises a control system of sequentially connecting, a waveform processing unit and a wave form output end, waveform processing unit comprises an internal clock unit for generation of internal clock signal, a thick pulse width unit, a delay cell and an impulse generating unit, described control system is used for calculating a very first time length and second time span according to a pulse width values, and send to described waveform processing unit, described thick pulse width unit produces a first signal edge and a secondary signal edge according to described very first time length, described first signal edge and secondary signal edge are spaced apart described very first time length, described delay cell is according to described second time span, under described secondary signal edging trigger, a the 3rd signal edge is exported after second time span described in time delay, described impulse generating unit produces a pulse according to described first signal edge and described 3rd signal edge.
For a pulse signal production method for above-mentioned signal generator, comprise the steps: to calculate a very first time length and second time span according to a pulse width values; Produce a first signal edge and a secondary signal edge according to described very first time length, described first signal edge and secondary signal edge are spaced apart described very first time length; According to described second time span, under described secondary signal edging trigger, after the second time span described in time delay, export a 3rd signal edge; A pulse is produced according to described first signal edge and described 3rd signal edge.
Signal generator of the present invention and pulse signal production method, owing to determining the pulsewidth of very first time length based on internal clock signal, the pulsewidth of the second time span is determined based on delay unit, because internal clock signal is digital signal, the change affected by external environment etc. is less, therefore can produce pulsewidth comparatively accurately.
Accompanying drawing explanation
Fig. 1 is the module map of a kind of control circuit of duty ratio 100 disclosed in Chinese invention patent application Publication Specification.
Fig. 2 is the response curve of pulse width modulation circuit 110 shown in Fig. 1.
Fig. 3 is the circuit diagram of a kind of control circuit of duty ratio 300 disclosed in an embodiment of control circuit of duty ratio 100 shown in Fig. 1.
Fig. 4 is the signal timing diagram in control circuit of duty ratio 300 shown in Fig. 3.
Fig. 5 is the modular structure schematic diagram of the signal generator 2 of first embodiment of the invention.
Fig. 6 is the modular structure schematic diagram of waveform processing unit 24 in the signal generator 2 of first embodiment of the invention.
Fig. 7 is the flow chart of steps that the signal generator 2 of first embodiment of the invention produces pulse signal method.
Fig. 8 is waveform processing unit 24 each signal timing diagram when working.
Fig. 9 is the modular structure schematic diagram of an embodiment of delay unit 243.
Figure 10 is each signal timing diagram when working of delay unit 243 shown in Fig. 9.
Figure 11 is the modular structure schematic diagram of the signal generator 3 of second embodiment of the invention.
Figure 12 is the process flow diagram of each step of the method for the generation pulse signal of signal generator 3 shown in Figure 11.
Figure 13 is waveform processing unit 34 each signal timing diagram when working.
Figure 14 is the modular structure schematic diagram of the signal generator 4 of third embodiment of the invention.
Figure 15 is the modular structure schematic diagram of the waveform processing unit 44 of signal generator 4 shown in Figure 14.
Figure 16 is the unit of waveform processing shown in Figure 15 44 each signal timing diagram when working.
Figure 17 is the modular structure schematic diagram of the signal generator 5 of four embodiment of the invention.
Figure 18 is the unit of waveform processing shown in Figure 17 54 each signal timing diagram when working.
Embodiment
Introduce the first embodiment of signal generator of the present invention below.
Please refer to Fig. 5, the signal generator 2 of first embodiment of the invention comprises a control system 21, waveform processing unit 24 and a wave form output end 29.In the present embodiment, control system 21 comprises a controller 211, input block 213 and an external clock unit 214.Input block 213 is connected to controller 211, and waveform processing unit 24 is connected with controller 211 with data bus 231 by address bus 232, and external clock unit 214 is connected with waveform processing unit 24 by external clock line 233.Waveform processing unit 24 is connected to wave form output end 29.
Input block 213 is for receiving pulse width values that is that user sets or input.The steering order that controller 211 can identify for this pulse width values being resolved to waveform processing unit 24 and process, sends to waveform processing unit 24 by address bus 232 and data bus 231.Waveform processing unit 24 is for producing the waveform of the pulse width values meeting user's setting or input according to this steering order.
Controller 211 is made up of DSP, and input block 213 is made up of keyboard and the I/O such as USB interface, LAN interface interface, and external clock unit 214 is made up of crystal oscillator, and waveform processing unit 24 is made up of FPGA.In the present embodiment, this external clock unit 214 produces the clock signal of 50MHZ.
In the present embodiment, please refer to Fig. 6, waveform processing unit 24 comprises the thick pulse width unit of a storage unit 241,242, delay cell 243, internal clock unit 244 and an impulse generating unit 245.Storage unit 241 is connected to data bus 231 and address bus 232, and storage unit 241 is also connected to thick pulse width unit 242 by line 253, and storage unit 241 is also connected to delay cell 243 by line 254.Internal clock unit 244 is connected to external clock line 233, and internal clock unit 244 is also connected respectively to thick pulse width unit 242 and delay cell 243.Thick pulse width unit 242 is connected to impulse generating unit 245 by line 256, and thick pulse width unit 242 is also connected to delay cell 243 by line 255.Delay cell 243 is connected to impulse generating unit 245 by line 257.Impulse generating unit 245 is connected to wave form output end 29.
In the present embodiment, storage unit 241 is the internal storage of FPGA.Certainly, storage unit 241 can also be made up of the external memory storage of FPGA, or is made up of together with external memory storage the internal storage of FPGA.Internal clock unit 244 is made up of phaselocked loop, and it receives the clock signal of the 50MHZ of transmission on external clock line 233 and carries out frequency multiplication, produces the internal clock signal of 200MHZ, is sent to thick pulse width unit 242 and delay cell 243.Thick pulse width unit 242 is made up of counter.
Please refer to Fig. 7, introduce each step of the method for the generation pulse signal of signal generator 2 below.
Step S1: calculate a very first time length and second time span according to a pulse width values;
Please with reference to Fig. 5, Fig. 6 and Fig. 7, user inputs a pulse width values by input block 213, and this pulse width values is the pulse width of the pulse signal that signal generator 2 exports, and such as, this pulse width values is 23ns.This pulse width values is decomposed into a very first time length and a second time span sum by controller 211, wherein, very first time length is the part that this pulse width values can be divided exactly by this internal clock cycles, and this second time span is then part that this pulse width can not be divided exactly by this internal clock cycles.In the citing of present embodiment, the internal clock signal produced due to internal clock unit 244 in waveform processing unit 24 is 200MHZ, namely an internal clock cycles is 5ns, therefore this pulse width values 23ns being decomposed the very first time length obtained is 20ns, it is 4 times of internal clock cycles, and the second time span is 3ns.Again such as, if pulse width values is 19ns, then very first time length is 15ns, and it is 3 times of internal clock cycles, and the second time span is 4ns.
Still with this pulse width values for 23ns illustrates, this very first time length 20ns and the second time span 3ns is sent to the storage unit 241 in waveform processing unit 24 by controller 211 by address bus 232 and data bus 231, and this very first time length is kept in storage space 251, the second time span is kept in storage space 252.Detailed process is: the address being chosen storage space 251 by address bus 232, and very first time length is sent to storage space 251 by data bus 231.Chosen the address of storage space 252 by address bus 232, the second time span is sent to storage space 252 by data bus 231.
Step S2: produce a first signal edge and a secondary signal edge, described first signal edge and secondary signal edge are spaced apart described very first time length;
Please with reference to Fig. 6, Fig. 7 and Fig. 8, thick pulse width unit 242 reads this very first time length by line 253 from storage space 251, is 20ns in the citing of present embodiment.Thick pulse width unit 242 sends a first signal edge P1 when an internal clock cycles starts by line 256, such as, be the rising edge of pulse signal, starts to count this internal clock signal C while this first signal edge P1.When adding up to count to 4 internal clock signal cycle T, when namely 20ns arrives, sending a secondary signal edge P2 by line 255 to delay cell 243, such as, is the rising edge of the pulse signal of a 10ns pulsewidth.
Step S3: under described secondary signal edging trigger, exports a 3rd signal edge after the second time span described in time delay;
Delay cell 243 reads this second time span by line 254 from storage space 252, be 3ns in the citing of present embodiment, delay cell 243 is from receiving this secondary signal edge P2, after time delay 3ns, exporting a 3rd signal edge P3 from line 257, such as, is the rising edge of pulse signal.
Step S4: produce a pulse according to described first signal edge and described 3rd signal edge;
Impulse generating unit 245 continues output high level immediately to wave form output end 29 after receiving the first signal edge P1 that line 256 transmits, impulse generating unit 245 continues output low level immediately to wave form output end 29 after receiving the 3rd signal edge P3 that line 257 transmits.Like this, wave form output end 29 just can export the pulse signal P4 of a 23ns pulsewidth.
Please refer to Fig. 9 and Figure 10, delay cell 243 comprises a control signal generation unit 247 and an input and output delay unit 248.Control signal generation unit 247 and input and output delay unit 248 are all connected to internal clock unit 244, are used for receiving internal clock signal C respectively.Control signal generation unit 247 is connected to line 254, and control signal generation unit 247 is also connected to input and output delay unit 248 by a line 258.Input and output delay unit 248 is connected to line 255, and input and output delay unit 248 is connected to line 257.
Input and output delay unit 248 is the one " absolute delay unit (IODELAY) able to programme " had in FPGA, and input and output delay unit 248 can carry out time delay to the signal that line 255 inputs, and the signal after time delay exports from line 257.It is 75ps that input and output delay unit 248 has minimum delay resolution, and the time of time delay is the Integer N times of 75ps, 0≤N≤63, and the value of N can by the control of line 258.Specifically, the pulsewidth of the delays time to control pulse signal that input and output delay unit 248 inputs according to line 258 is N number of internal clock cycles T, then the N number of 75ps of signal lag of input and output delay unit 248 pairs of lines 255 inputs, then exports from line 257.
Control signal generation unit 247 values according to this second time span, export the delays time to control pulse signal of corresponding pulsewidth.
Citing in the present embodiment, be 3ns for the second time span, control signal generation unit 247 produces and exports a pulsewidth from line 258 is that the delays time to control pulse signal of 40 internal clock cycles T is to input and output delay unit 248, then when 248 when keeping such delays time to control pulse signal, the signal inputted by line 255 that input and output delay unit 248 can continue carries out time delay, time delay size is 40 75ps, i.e. 3ns.
As can be seen here, present embodiment signal generator 2 is owing to producing the pulsewidth of very first time length based on internal clock signal C, the pulsewidth of the second time span is produced based on input and output delay unit 248, because internal clock signal C is digital signal, the change affected by external environment etc. is less, therefore can produce pulsewidth comparatively accurately.
In addition, because input and output delay unit 248 have employed the one " absolute delay unit (IODELAY) able to programme " had in FPGA, not only can provide point-device time delay, and also belong to digital circuit chip due to FPGA, therefore the change affected by external environment etc. is less, can produce pulsewidth comparatively accurately.And compare the time that mimic channel saves a lot of debugging and test, cost of development is lower.
In addition, because in present embodiment, the frequency of internal clock signal is preferably 200MHZ, namely the cycle of internal clock signal is 5ns, and therefore very first time length is the integral multiple of 5ns, as 5ns, 10ns, 15ns etc.Be 75ps because input and output delay unit 248 has minimum delay resolution again, and the time of time delay is the Integer N times of 75ps, 0≤N≤63, as seen its maximum delay time 75ps × 64=4.8ns, approximate 5ns, namely the second time span can approximate 5ns.As can be seen here, signal generator 2 can produce the pulse of Pulse of Arbitrary width value.
Introduce the second embodiment of signal generator of the present invention below.
Please refer to Figure 11, signal generator 3 is from the difference of signal generator 2: waveform processing unit 34 is different with the inner structure of waveform processing unit 24.In the present embodiment, waveform processing unit 24 comprises the thick pulse width unit of a storage unit 241,242, delay cell 243, internal clock unit 244 and an impulse generating unit 245.Storage unit 241 is connected to data bus 231 and address bus 232, and storage unit 241 is also connected to thick pulse width unit 242 by line 253, and storage unit 241 is also connected to delay cell 243 by line 254.Internal clock unit 244 is connected to external clock line 233, and internal clock unit 244 is also connected respectively to thick pulse width unit 242 and delay cell 243.Thick pulse width unit 242 is connected to impulse generating unit 245 by line 256, and delay cell 243 is also connected to line 256 by line 355.Delay cell 243 is connected to impulse generating unit 245 by line 257.Impulse generating unit 245 is connected to wave form output end 29.
Please refer to Figure 12, introduce each step of the method for the generation pulse signal of signal generator 3 below.
Step S11: calculate a very first time length and second time span according to a pulse width values;
In this step S11, the course of work of signal generator 3 is identical with the step S1 of signal generator 2.
Step S2: produce a first signal edge and a secondary signal edge, described first signal edge and secondary signal edge are spaced apart described very first time length;
Please with reference to Figure 11, Figure 12 and Figure 13, thick pulse width unit 242 reads this very first time length by line 253 from storage space 251, is 20ns in the citing of present embodiment.Thick pulse width unit 242 sends a first signal edge P1 when an internal clock cycles starts by line 256, such as, be the rising edge of pulse signal and permanent High level, start to count this internal clock signal C while this first signal edge P1.When adding up to count to 4 internal clock signal cycle T, namely when 20ns arrives, send a secondary signal edge P2 by line 256, such as, be the negative edge of pulse signal and continue low level, like this, line 256 outputs a pulsewidth in 4 internal clock signal cycle T is the pulse of 20ns.
Step S3: under described secondary signal edging trigger, exports a 3rd signal edge after the second time span described in time delay;
Delay cell 243 reads this second time span by line 254 from storage space 252, is 3ns in the citing of present embodiment.Because line 355 is identical with the signal on line 256, therefore signal time delay 3ns of will receiving from line 256 of delay cell 243, the pulsewidth therefore exporting a time delay 3ns on online 257 is the pulse of 20ns.Wherein secondary signal edge P2 exports from line 257 after by time delay 3ns, thus forms a 3rd signal edge P3.
Step S4: produce a pulse according to described first signal edge and described 3rd signal edge;
Impulse generating unit 245 continues output high level immediately to wave form output end 29 after receiving the first signal edge P1 that line 256 transmits, impulse generating unit 245 continues output low level immediately to wave form output end 29 after receiving the 3rd signal edge P3 that line 257 transmits.Like this, wave form output end 29 just can export the pulse signal P4 of a 23ns pulsewidth.
Alternatively embodiment, impulse generating unit 245 can be reduced to one or, by line 256 and line 257 export signal carry out logical OR operation, just can export the pulse signal P4 of a 23ns pulsewidth at wave form output end 29.
As the distortion of the first embodiment and the second embodiment, be sent to the very first time length of storage space 251 by address bus 232 and data bus 231 and the second time span can replace with the numerical value that other can express very first time length and the second time span, such as very first time length can replace with the multiple of very first time length divided by internal clock cycles T.Second time span can replace with the multiple of the second time span divided by minimum delay resolution.In the citing of the first embodiment and the second embodiment, the internal clock signal produced due to internal clock unit 244 in waveform processing unit 24 is 200MHZ, very first time length is 20ns, the second time span is 3ns, therefore can substitute 20ns with multiple 4, replace 3ns with multiple 40.
Introduce the 3rd embodiment of signal generator of the present invention below.
Please refer to Figure 14, the signal generator 4 of the present invention one better embodiment comprises a control system 41, waveform processing unit 44 and a wave form output end 49.In the present embodiment, control system 41 comprises a controller 411, input block 413 and an external clock unit 414.Input block 413 is connected to controller 411, and waveform processing unit 44 is connected with controller 411 with a secondary signal line 431 by first signal wire 432, and external clock unit 414 is connected with waveform processing unit 44 by external clock line 433.Waveform processing unit 44 is connected to wave form output end 49.
Input block 413 is for receiving pulse width values that is that user sets or input.The steering order that controller 411 can identify for this pulse width values being resolved to waveform processing unit 44 and process, sends to waveform processing unit 44 by address bus 432 and data bus 431.Waveform processing unit 44 is for producing the waveform of the pulse width values meeting user's setting or input according to this steering order.
Controller 411 is made up of DSP, and input block 413 is made up of keyboard and the I/O such as USB interface, LAN interface interface, and external clock unit 414 is made up of crystal oscillator, and waveform processing unit 44 is made up of FPGA.In the present embodiment, this external clock unit 414 produces the clock signal of 50MHZ.
In the present embodiment, please refer to Figure 15, waveform processing unit 44 comprises a thick pulse width unit 442, delay cell 443, internal clock unit 444 and an impulse generating unit 445.Thick pulse width unit 442 is connected to the first signal wire 431, and delay cell 443 is connected to secondary signal line 432.Internal clock unit 444 is connected to external clock line 433, and internal clock unit 444 is also connected respectively to thick pulse width unit 442 and delay cell 443.Thick pulse width unit 442 is connected to impulse generating unit 445 by line 456, and thick pulse width unit 442 is also connected to delay cell 443 by line 455.Delay cell 443 is connected to impulse generating unit 445 by line 457.Impulse generating unit 445 is connected to wave form output end 49.
In the present embodiment, internal clock unit 444 is made up of phaselocked loop, and it receives the clock signal of the 50MHZ of transmission on external clock line 433 and carries out frequency multiplication, produces the internal clock signal of 200MHZ, is sent to thick pulse width unit 442 and delay cell 443.Thick pulse width unit 442 is made up of counter.
Please refer to Fig. 7, introduce each step of the method for the generation pulse signal of signal generator 4 below.
Step one: calculate a very first time length and second time span according to a pulse width values;
Please with reference to Figure 14 and Figure 15, user inputs a pulse width values by input block 413, and this pulse width values is the pulse width of the pulse signal that signal generator 4 exports, and such as, this pulse width values is 23ns.This pulse width values is decomposed into a very first time length and a second time span sum by controller 411, wherein, very first time length is the part that this pulse width values can be divided exactly by this internal clock cycles, and this second time span is then part that this pulse width values can not be divided exactly by this internal clock cycles.In the citing of present embodiment, the internal clock signal produced due to internal clock unit 444 in waveform processing unit 44 is 200MHZ, namely an internal clock cycles is 5ns, therefore this pulse width values 23ns being decomposed the very first time length obtained is 20ns, it is 4 times of internal clock cycles, and the second time span is 3ns.Again such as, if pulse width values is 19ns, then very first time length is 15ns, and it is 3 times of internal clock cycles, and the second time span is 4ns.
Still with this pulse width values for 23ns illustrates, controller 411 produces first control signal according to this very first time length 20ns, is sent to waveform processing unit 44 by the first signal wire 431.Controller 411 produces second control signal according to the second time span 3ns, is sent to waveform processing unit 44 by secondary signal line 432.This first control signal and the second control signal can be pulse signal, triangular signal etc.
Step 2: produce a first signal edge and a secondary signal edge, described first signal edge and secondary signal edge are spaced apart described very first time length;
Please with reference to Figure 14, Figure 15 and Figure 16, thick pulse width unit 442 obtains this first control signal from the first signal wire 431.Thick pulse width unit 442 sends a first signal edge P1 when an internal clock cycles starts by line 256, such as, be the rising edge of pulse signal, starts to count this internal clock signal C while this first signal edge P1.When adding up to count to 4 internal clock signal cycle T, when namely 20ns arrives, sending a secondary signal edge P2 by line 455 to delay cell 443, such as, is the rising edge of the pulse signal of a 10ns pulsewidth.
Step 3: under described secondary signal edging trigger, exports a 3rd signal edge after the second time span described in time delay;
Delay cell 443 obtains this second control signal from secondary signal line 432.Delay cell 443 is from receiving this secondary signal edge P2, and after time delay 3ns, exporting a 3rd signal edge P3 from line 457, such as, is the rising edge of pulse signal.
Step 4: produce a pulse according to described first signal edge and described 3rd signal edge;
Impulse generating unit 445 continues output high level immediately to wave form output end 49 after receiving the first signal edge P1 that line 456 transmits, impulse generating unit 445 continues output low level immediately to wave form output end 49 after receiving the 3rd signal edge P3 that line 457 transmits.Like this, wave form output end 49 just can export the pulse signal P4 of a 23ns pulsewidth.
Introduce the 4th embodiment of signal generator of the present invention below.
Please refer to Figure 17, signal generator 5 is from the difference of signal generator 4: waveform processing unit 54 is different with the inner structure of waveform processing unit 44.In the present embodiment, waveform processing unit 54 comprises a thick pulse width unit 442, delay cell 443, internal clock unit 444 and an impulse generating unit 445.Thick pulse width unit 442 is connected to the first signal wire 431, and delay cell 443 is connected to secondary signal line 432.Internal clock unit 444 is connected to external clock line 433, and internal clock unit 444 is also connected respectively to thick pulse width unit 442 and delay cell 443.Thick pulse width unit 442 is connected to impulse generating unit 445 by line 456, and delay cell 443 is also connected to line 456 by line 555.Delay cell 443 is connected to impulse generating unit 445 by line 457.Impulse generating unit 445 is connected to wave form output end 49.
Introduce each step of the method for the generation pulse signal of signal generator 3 below.
Step one: calculate a very first time length and second time span according to a pulse width values;
In this step, the course of work of signal generator 5 is identical with the step one of signal generator 4.
Step 2: produce a first signal edge and a secondary signal edge, described first signal edge and secondary signal edge are spaced apart described very first time length;
Please with reference to Figure 17 and Figure 18, thick pulse width unit 442 obtains this first control signal from the first signal wire 431.Thick pulse width unit 442 sends a first signal edge P1 when an internal clock cycles starts by line 456, such as, be the rising edge of pulse signal and permanent High level, start to count this internal clock signal C while this first signal edge P1.When adding up to count to 4 internal clock signal cycle T, namely when 20ns arrives, send a secondary signal edge P2 by line 456, such as, be the negative edge of pulse signal and continue low level, like this, line 456 outputs a pulsewidth in 4 internal clock signal cycle T is the pulse of 20ns.
Step 3: under described secondary signal edging trigger, exports a 3rd signal edge after the second time span described in time delay;
Delay cell 443 obtains this second control signal from secondary signal line 432.Because line 555 is identical with the signal on line 456, therefore signal time delay 3ns of will receiving from line 456 of delay cell 443, the pulsewidth therefore exporting a time delay 3ns on online 457 is the pulse of 20ns.Wherein secondary signal edge P2 exports from line 457 after by time delay 3ns, thus forms a 3rd signal edge P3.
Step 4: produce a pulse according to described first signal edge and described 3rd signal edge;
Impulse generating unit 445 continues output high level immediately to wave form output end 49 after receiving the first signal edge P1 that line 456 transmits, impulse generating unit 445 continues output low level immediately to wave form output end 49 after receiving the 3rd signal edge P3 that line 457 transmits.Like this, wave form output end 49 just can export the pulse signal P4 of a 23ns pulsewidth.
Alternatively embodiment, impulse generating unit 445 can be reduced to one or, by line 456 and line 457 export signal carry out logical OR operation, just can export the pulse signal P4 of a 23ns pulsewidth at wave form output end 49.
As variant embodiment, the connection in each embodiment of the present invention between modules is series connection, does not get rid of in the middle of them and can also be in series with other functional modules as required.Such as, an interface module be made up of FPGA can also be serially connected with between controller and waveform processing unit.
As variant embodiment, in each embodiment of the present invention, the mode of pulse width values that is that user sets or input can have other alternative.Such as, by arranging the cycle and dutycycle that need the waveform exported, the effect of input pulse width value can also be reached.
As variant embodiment, in each embodiment of the present invention, waveform processing unit also can be made up of other programmable logic device (PLD) such as CPLD.
Claims (10)
1. a signal generator, it comprises a control system of sequentially connecting, a waveform processing unit and a wave form output end, it is characterized in that: waveform processing unit comprises an internal clock unit for generation of internal clock signal, thick pulse width unit, a delay cell and an impulse generating unit
Described control system is used for calculating a very first time length and second time span according to a pulse width values, and send to described waveform processing unit, described very first time length is that described pulse width values can be done the maximum part divided exactly by the cycle of described internal clock signal, described second time span is the part that described pulse width values can not be divided exactly by the cycle of described internal clock signal
Described thick pulse width unit produces a first signal edge and a secondary signal edge according to described very first time length, and described first signal edge and secondary signal edge are spaced apart described very first time length,
Described delay cell, according to described second time span, under described secondary signal edging trigger, exports a 3rd signal edge after the second time span described in time delay,
Described impulse generating unit produces a pulse according to described first signal edge and described 3rd signal edge.
2. signal generator according to claim 1, it is characterized in that: very first time length and the second time span are saved to the first storage space and second storage space of the storer of described waveform processing unit by described control system respectively by address bus and data bus, described thick pulse width unit produces described first signal edge and secondary signal edge according to the value in described first storage space, and described delay cell produces described 3rd signal edge according to the value of described second storage space.
3. signal generator according to claim 2, is characterized in that: delay cell comprises a control signal generation unit and an input and output delay unit,
Described input and output delay unit is used under described secondary signal edging trigger, exports described 3rd signal edge after the second time span described in time delay,
Described control signal generation unit is used for producing a delay control signal according to the value of described second storage space, for controlling the time of the time delay of described input and output delay unit.
4. signal generator according to claim 1, is characterized in that: described delay cell exports after described secondary signal edge time delay second time span as the 3rd signal edge.
5. signal generator according to claim 1, is characterized in that: the frequency of described internal clock signal is 200MHZ, and the maximum delay time of described delay unit is less than 5ns.
6. signal generator according to claim 1, is characterized in that: described waveform processing unit comprises programmable logic device (PLD).
7., for a pulse signal production method for signal generator as claimed in claim 1, it is characterized in that, comprise the steps:
A very first time length and second time span is calculated according to a pulse width values, described very first time length is the part that described pulse width values can be divided exactly by the cycle of described internal clock signal, and described second time span is the part that described pulse width values can not be divided exactly by the cycle of described internal clock signal;
Produce a first signal edge and a secondary signal edge according to described very first time length, described first signal edge and secondary signal edge are spaced apart described very first time length;
According to described second time span, under described secondary signal edging trigger, after the second time span described in time delay, export a 3rd signal edge;
A pulse is produced according to described first signal edge and described 3rd signal edge.
8. pulse signal production method according to claim 7, it is characterized in that: described step is under described secondary signal edging trigger, and exporting a 3rd signal edge after the second time span described in time delay is export after the second time span described in described secondary signal edge time delay as described 3rd signal edge.
9. pulse signal production method according to claim 7, it is characterized in that: described step produces a first signal edge and a secondary signal edge is generation intermediate pulse, and described first signal edge and described secondary signal edge are respectively rising edge and the negative edge of described intermediate pulse.
10. pulse signal production method according to claim 9, it is characterized in that: described step is under described secondary signal edging trigger, exporting a 3rd signal edge after second time span described in time delay is by described intermediate pulse time delay, using the negative edge after time delay as the 3rd signal edge.
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| US9766160B2 (en) | 2011-08-26 | 2017-09-19 | Siemens Aktiengesellschaft | Method for generating a pulse signal sequence |
| CN102541643A (en) * | 2011-12-30 | 2012-07-04 | 上海新时达电气股份有限公司 | Logic signal delayed processing method for embedded system |
| CN103178809B (en) * | 2013-02-04 | 2016-02-17 | 深圳市鼎阳科技有限公司 | A kind of DDS porch control method, module and pulse signal generator |
| CN103488244B (en) * | 2013-09-09 | 2016-04-27 | 中国电子科技集团公司第四十一研究所 | A kind of random waveform generation systems and method |
| CN106712490A (en) * | 2016-07-27 | 2017-05-24 | 南京航空航天大学 | DC/DC control circuit based on IODELAY firmware |
| US11188115B2 (en) | 2018-02-11 | 2021-11-30 | University Of Science And Technology Of China | Sequence signal generator and sequence signal generation method |
| CN114499470A (en) * | 2022-04-06 | 2022-05-13 | 之江实验室 | Nanosecond programmable pulse signal generator |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1447935A (en) * | 2000-08-24 | 2003-10-08 | 泰拉丁公司 | Noise-shaped digital frequency synthesis |
| CN1144116C (en) * | 1997-05-23 | 2004-03-31 | 三菱电机株式会社 | Device for generating clock signal |
| CN1790286A (en) * | 2004-12-17 | 2006-06-21 | 上海环达计算机科技有限公司 | PCI test card and test method thereof |
| US7375546B1 (en) * | 2006-06-08 | 2008-05-20 | Xilinx, Inc. | Methods of providing performance compensation for supply voltage variations in integrated circuits |
-
2009
- 2009-12-28 CN CN200910243149.1A patent/CN102109875B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1144116C (en) * | 1997-05-23 | 2004-03-31 | 三菱电机株式会社 | Device for generating clock signal |
| CN1447935A (en) * | 2000-08-24 | 2003-10-08 | 泰拉丁公司 | Noise-shaped digital frequency synthesis |
| CN1790286A (en) * | 2004-12-17 | 2006-06-21 | 上海环达计算机科技有限公司 | PCI test card and test method thereof |
| US7375546B1 (en) * | 2006-06-08 | 2008-05-20 | Xilinx, Inc. | Methods of providing performance compensation for supply voltage variations in integrated circuits |
Non-Patent Citations (1)
| Title |
|---|
| 165MHz脉冲/数据发生器数字波形产生部分的设计;赵栋;《中国优秀硕士学位论文全文数据库》;20061215(第12期);第7-49页 * |
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