CN106712490A

CN106712490A - DC/DC control circuit based on IODELAY firmware

Info

Publication number: CN106712490A
Application number: CN201610602609.5A
Authority: CN
Inventors: 胡文; 袁效鹏; 胡姗姗; 庄珊娜; 张巍巍; 陆晓明; 齐全; 陈悦; 朱熠良
Original assignee: Nanjing Power Technology Co Ltd; Nanjing University of Aeronautics and Astronautics
Current assignee: Nanjing Power Technology Co Ltd; Nanjing University of Aeronautics and Astronautics
Priority date: 2016-07-27
Filing date: 2016-07-27
Publication date: 2017-05-24

Abstract

The invention discloses a DC/DC control circuit based on IODELAY firmware. The DC/DC control circuit is composed of a clock generating circuit, a pulse width generating circuit, an IODELAY delay circuit, and an OR-gating circuit. The clock generating circuit performs frequency multiplication on an input clock signal, and then outputs basic clock signals to the pulse width generating circuit and the IODELAY delay circuit. The pulse width generating circuit outputs coarse tuning pulse-width signals to the IODELAY delay circuit and the OR-gating circuit. The IODELAY delay circuit carries out precise time-delay on the coarse tuning pulse-width signal, and outputs a delayed pulse width signal to the OR-gating circuit. The coarse tuning pulse-width signal and the delayed pulse width signal are input to the OR-gating circuit, and a final DC/DC control signal is output. The DC/DC control circuit realizes precise time delay by means of the IODELAY firmware, namely, performs frequency division on the basic clock signal, improves the duty ratio resolution of the DC/DC control signal under the condition that the basic clock signal is unchanged, and has high precision, universality and applicability.

Description

DC/DC control circuits based on IODELAY firmwares

Technical field

The invention belongs to electronic technology field, and in particular to a kind of DC/DC controls circuit.

Background technology

Pulsewidth modulation（Pulse Width Modulation, PWM）Type DC/DC converters are widely used in camera, take the photograph In the portable type electronic products such as camera, PDA, laptop computer.PWM type DC/DC converters have analog- and digital- two kinds of frameworks.Simulation The product area of framework is small, low in energy consumption, accounts for the main flow in market, but it is very sensitive to noise；And Digital Design framework scalability Good, stability is high, noise relative insensitivity to external world, can just make up the shortcoming of analog architectures.From DC/DC converters Growth requirement sees that digital Control Technology is necessary.In the design of current digital architecture DC/DC, generally existing pwm signal is accounted for The resolution ratio of empty ratio is difficult to the shortcoming for improving.

IODELAY firmwares are the programmable delay units included in each I/O module of Xilinx companies, can be used to combine Input channel, deposit input channel, combination output channel or deposit output channel etc., also internally can directly use in resource.

In article " the high accuracy number PWM DC/DC controller designs based on FPGA ", it is proposed that one kind is using scene Programmable gate array（FPGA）Realize the scheme of digital high precision PWM types DC/DC, the program mainly by A/D modular converters, Pid control module and DPWM（Digital pulse width modulation）Module is constituted, and final simulation result shows that digital PWM reaches 8 points Resolution, the output frequency of 1MHz.But the program has the following disadvantages：When Base clock resolution ratio is constant, modulation accuracy cannot Improve, simply modulation accuracy is relatively low.Other design is complex, and design technology requirement is higher, and cost is costly.

The content of the invention

It is an object of the invention to provide a kind of high-resolution DC/DC controls circuit, in the bar that fundamental clock signal is constant DC/DC control signals duty cycle resolution can be improved 64 times under part.

Realize that the technical scheme of the object of the invention is as follows：It is a kind of based on IODELAY firmwares DC/DC control circuit, by when There is circuit, IODELAY delay circuits and/or gating circuit composition in clock generative circuit, pulsewidth.When clock forming circuit is to input Fundamental clock signal is produced after clock signal frequency multiplication；There is the coarse adjustment of circuit realiration pulsewidth in pulsewidth, export coarse adjustment pulse width signal； IODELAY delay circuits generate time delay pulse width signal to coarse adjustment pulse width signal precise delay；Coarse adjustment pulse width signal and time delay pulsewidth Signal input or gating circuit export final DC/DC control signals.The present invention realizes precise delay by IODELAY firmwares, Divided equivalent to fundamental clock signal, DC/DC control signal dutycycles are improve under conditions of fundamental clock signal is constant Resolution ratio.The present invention realizes precise delay by IODELAY firmwares, is divided equivalent to fundamental clock signal, in Base clock DC/DC control signal duty cycle resolutions are improve under conditions of signal is constant.

Clock forming circuit generates fundamental clock signal by 1 frequency multiplier to input clock signal frequency multiplication.

There is circuit and produce coarse adjustment pulse width signal by pulse width generator in pulsewidth, realize the coarse adjustment of pulsewidth.

The function of IODELAY delay circuits is realized by the IODELAY firmwares of Xilinx companies.IODELAY firmwares are according to it Input array realizes the precise delay that phase resolution is 360 °/64=5.625 °, generation time delay pulsewidth letter to coarse adjustment pulse width signal Number, divided equivalent to fundamental clock signal 64, by DC/DC control signal dutycycles under conditions of fundamental clock signal is constant Resolution ratio improves 64 times.

Or gating circuit is by look-up table（Look-up-table, LUT）Realize logic or function, coarse adjustment pulse width signal and prolong When pulse width signal input LUT and export final DC/DC control signals.

What the resolution ratio that the present invention solves traditional PWM types DC/DC control circuit PWM signal dutyfactor was difficult to improve lacks Point, with stronger with stronger accuracy, versatility and applicability.

Brief description of the drawings

Fig. 1 is DC/DC control circuit overall structures.

Fig. 2 is clock forming circuit.

Fig. 3 is that pulsewidth occurs circuit.

Fig. 4 is IODELAY delay circuits.

Fig. 5 is or gating circuit.

Fig. 6 is that pulsewidth occurs circuit output waveform.

Fig. 7 is IODELAY delay circuit output waveforms.

Fig. 8 is or gating circuit output waveform.

Specific embodiment

The present invention is described in more detail with reference to the accompanying drawings.

The present invention provide a kind of high-resolution from DC/DC control circuit, general structure is as shown in figure 1, the control circuit There are four parts such as circuit, IODELAY delay circuits and/or gating circuit by clock forming circuit, pulsewidth to constitute.Each several part Physical circuit figure is as shown in Figures 2 to 5.

10 bit array dc will be input into first（9:0）It is divided into 4 bit array N=dc high（9:6）With low 6 bit array m=dc（5:0）.

In the clock forming circuit shown in Fig. 2, DCM × 5 are 5 times of frequency doublers, and CLK signal is believed for input clock Number, its frequency is 50MHz.CLK by after the frequency multiplication of DCM × 5, for the fundamental clock signal CK of 250MHz send out to pulsewidth by output frequency Raw circuit and IODELAY delay circuits are used as the cycle T=4ns for controlling clock, i.e. fundamental clock signal.

In pulsewidth as shown in Figure 3 occurs circuit, pulse width generator exports corresponding pulsewidth according to 4 bit array N high is input into Coarse adjustment pulse width signal to IODELAY delay circuits and/or gating circuit.Pulsewidth occur circuit output waveform as shown in fig. 6, The width of coarse adjustment pulse signal is N × T, and the integer clock cycle of array is as input into corresponding to pulse width generator.

In IODELAY delay circuits as shown in Figure 4, IODELAY firmwares are according to the low 6 bit array m of input to coarse adjustment arteries and veins Bandwidth signals enter the time delay that line phase is m × 360 °/64, and corresponding time delay is m × T/64, as solid corresponding to IODELAY Part is input into small several fundamental clock signal cycles of array.Divided equivalent to fundamental clock signal 64.Delay phase with it is low 6 The relation of array is as shown in Figure 7.

In as shown in Figure 5 or gating circuit, logic or function are realized by LUT.LUT input/output relations table such as following table It is shown.It is 0 to control A2, A3 input of LUT, as long as it is high level output as high level that A0 and A1 have signal all the way.Coarse adjustment Pulse width signal and time delay pulse width signal are input into from A0, A1 respectively, and LUT outputs are final DC/DC control signals.Equivalent to thick Pulse width signal and time delay pulse width signal is adjusted to determine the rising edge and trailing edge of DC/DC control signals respectively.Or gating circuit is defeated Go out waveform as shown in Figure 8.

LUT input/output relation tables

, mainly there is the coarse adjustment of circuit realiration signal by pulsewidth, slightly in DC/DC control circuit of the present invention based on IODELAY firmwares Adjust the pulsewidth modulation for completing the integer fundamental clock signal cycle, as N × T；The thin of signal is realized by IODELAY delay circuits Adjust, fine tuning completes the pulsewidth modulation in small several fundamental clock signal cycles, as m × T/64.The arteries and veins of final DC/DC control signals A width of coarse adjustment and fine tuning pulsewidth sum, i.e. (N+m/64) × T, under conditions of fundamental clock signal is constant, by DC/DC controls The duty cycle resolution of signal improves 64 times.

Claims

1. a kind of DC/DC based on IODELAY firmwares controls circuit, it is characterised in that：The control circuit includes that clock generates electricity There is circuit, IODELAY delay circuits and/or gating circuit in road, pulsewidth；Wherein, clock forming circuit is to input clock signal times Fundamental clock signal to pulsewidth is exported after frequency circuit and IODELAY delay circuits occur；There is circuit output coarse adjustment pulsewidth in pulsewidth Signal is to IODELAY delay circuits and/or gating circuit；IODELAY delay circuits are to coarse adjustment pulse width signal precise delay, output Time delay pulse width signal to or gating circuit；Coarse adjustment pulse width signal and the input of time delay pulse width signal or gating circuit, export final DC/DC control signals.

2. the DC/DC based on IODELAY firmwares according to claim 1 controls circuit, it is characterised in that：Time delay pulsewidth is believed Number and the time delay between coarse adjustment pulse width signal be corresponding to IODELAY firmwares input array small several fundamental clock signals week Phase.

3. the DC/DC based on IODELAY firmwares according to claim 1 controls circuit, it is characterised in that：There is electricity in pulsewidth Route pulse width generator is input into array and produces coarse adjustment pulse width signal according to it, realizes the coarse adjustment of pulsewidth；The arteries and veins of coarse adjustment pulse width signal A width of integer fundamental clock signal cycle that array is input into corresponding to pulse width generator.

4. the DC/DC based on IODELAY firmwares according to claim 1 controls circuit, it is characterised in that：Or gating circuit Logic or function are realized by look-up table LUT, coarse adjustment pulse width signal and time delay pulse width signal are input into LUT and export final DC/DC Control signal, the two determines the rising edge and trailing edge of DC/DC control signals respectively, and the pulsewidth of final DC/DC control signals is Integer fundamental clock signal cycle and small several fundamental clock signal cycle sums.

5. the DC/DC based on IODELAY firmwares according to claim 1 controls circuit, it is characterised in that：Clock generation electricity Route frequency multiplier generates fundamental clock signal to input clock signal frequency multiplication.