CN104502688A - DC (direct current) variable low-frequency envelope digital detector - Google Patents
DC (direct current) variable low-frequency envelope digital detector Download PDFInfo
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Abstract
The invention provides a DC variable low-frequency envelope digital detector. The DC variable low-frequency envelope digital detector at least comprises a disperse adjustable band-gap reference voltage generator, a comparator for comparing input signals with band-gap reference voltage, a digital calibration detector for detecting the output of the comparator and calibrating the band-gap reference voltage. According to the low-frequency characteristics of input voltage, the DC variable low-frequency envelope digital detector can greatly simplify the complexity of a circuit scheme, achieve degree of freedom and avoid influence of process and temperature change on signal processing performance to the maximum degree; a calibration tracing scheme can solves the problem of DC drift, which cannot be handled by traditional methods, and save on-chip large capacitors; due to the fact that most signal processing tasks are undertaken in a digital circuit part, so that the circuit power consumption can be greatly reduced.
Description
Technical field
The present invention relates to integrated circuit (IC) design field, particularly relate to a kind of inversion of direct current lower-frequency envelope digital detector.
Background technology
In electronic applications, visible everywhere to the needs of input, such as, automatic growth control in radio-frequency transmitter is exactly the gain needing the size of detection signal amplitude in good time to adjust each module of signal path, amplitude when making signal arrive digital to analog converter input end just reaches the full amplitude of oscillation of digital to analog converter input range, instead of exceedes the full amplitude of oscillation or much less than the full amplitude of oscillation.To also transmitting in this way, real time detection signal watt level, makes it be operated in optimum condition to adjust.Come the field of rather low-frequency, the AC signal with certain envelope is commonly used for a control signal, such as amplitude is at 0 ~ 100mV, 100 ~ 200mV, 200 ~ 300mV ... represent different mode of operations respectively, then just need testing circuit to detect the amplitude of this control signal in system, to change the control signal (such as digital signal) exporting and be applicable to system and use.
Traditional envelope detector is detect the peak value place absolute voltage value of input waveform instead of the peak-to-peak envelope value of AC compounent in fact, and its DC shift will affect final envelope detected result like this.When a-c cycle is higher, direct current signal and AC signal can be separated and process, then traditional envelope detection method would not be subject to the DC shift impact of input voltage; But for when the frequency of AC compounent lower, wanting to separate direct current signal just needs very large electric capacity with AC signal, will take most of area of integrated circuit like this, and this is unallowed under considerable low cost requirement.So under traditional envelope detection method is only applicable to than higher-frequency category.
When quite high for accuracy of detection, the temperature variant requirement of circuit performance will be quite strict.If testing result absolute value is directly relevant to the technological parameter during circuit, and this technological parameter has sizable temperature drift coefficient, and the method is not just suitable in temperature variation greatly and also will keep high-precision detection perform.
So under above-mentioned inversion of direct current comparatively low frequency incoming voltage, need also to keep stable detectability when temperature variation is larger, and do not need electric capacity on large-area integrated circuit chip, then need the more novel method being used in low-frequency ac signal detection.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of inversion of direct current lower-frequency envelope digital detector, affects large problem for the drift solving envelope detector in prior art to testing result.
For achieving the above object and other relevant objects, the invention provides a kind of inversion of direct current lower-frequency envelope digital detector, described direct current lower-frequency envelope digital detector at least comprises:
Discrete gap tunable reference voltage generator, comparer and digital calibration detecting device;
Described discrete gap tunable reference voltage generator produces the bandgap voltage reference of discrete variable according to the control bit that described digital calibration detecting device provides;
Described comparer is connected to described discrete gap tunable reference voltage generator, for comparing the size of input voltage and described bandgap voltage reference, and exports judged result;
Described digital calibration detecting device is connected to described comparer, and for detecting the comparative result that described comparer exports and the described control bit of comparative result calibration output exported according to described comparer, timing simultaneously upgrades output and deposits bit.
Preferably, described discrete gap tunable reference voltage generator comprises band gap current reference and adjustable resistance array, one end of described band gap current reference connects power supply, the other end connects described adjustable resistance array, the other end ground connection of described adjustable resistance array, described band gap current reference flows through described adjustable resistance array and produces described bandgap voltage reference.
More preferably, described adjustable resistance array is controlled by described control bit, actual resistance and described control bit linear.
More preferably, the resistance type used in described adjustable resistance array is identical with the resistance type used in described band gap current reference.
Preferably, described digital calibration detecting device comprises square wave detector, calibrating device, register and frequency divider;
Described square wave detector is connected to described comparer, for judging that whether comparative result that described comparer exports is the square-wave signal within the scope of setpoint frequency, judges Output rusults;
Described calibrating device is connected to described comparer and described square wave detector, and the situation of change of the judged result exported for the comparative result that exports according to described comparer and described square wave detector calibrates described control bit;
Described register is connected to described comparer, described square wave detector and described calibrating device, the situation of change of the judged result exported for the comparative result that exports according to described comparer and described square wave detector deposits described control bit, and deposits bit described in exporting;
Described frequency divider connects the first clock signal, is used for driving described calibrating device and described register by after described first clock signal frequency division.
More preferably, time period between adjacent two rising edges of the comparative result that described square wave detector exports at described comparer counts, if count results is in setting counting region, represent that comparative result that described comparer exports is the square-wave signal within the scope of setpoint frequency, the judged result set of described square wave detector output; Otherwise, then represent that the comparative result of the output of described comparer is not square-wave signal within the scope of setpoint frequency, the judged result reset that described square wave detector exports.
More preferably, it is minimum value that described calibrating device arranges described control bit, the comparative result that now described comparer exports is desired value " 1 ", the judged result that described square wave detector exports is desired value " 0 ", under the clock signal driving that described frequency divider exports, described calibrating device carries out+1 operation to described control bit, until described comparer and described square wave detector two of exporting pre-interim any one change; Described calibrating device arranges described control bit is afterwards maximal value, the comparative result that now described comparer exports is desired value " 0 ", the judged result that described square wave detector exports is desired value " 0 ", under the clock signal driving that described frequency divider exports, described calibrating device carries out-1 operation to described control bit, until described comparer and described square wave detector two of exporting pre-interim any one change; Then go round and begin again repetition aforesaid operations.
More preferably, depositing bit described in upgrading respectively in any one two kinds of situation changed in two desired values that described register exports in described comparer and described square wave detector is current control bit, and the bit of depositing in two kinds of situations goes round and begins again and alternately upgrades.
More preferably, the difference of depositing bit described in described register two kinds of situations of depositing respectively is exactly the envelope size numeral expression of described input voltage; Deposit described in two kinds of situations that described register is deposited respectively bit and half be exactly the DC voltage size mathematical expression of described input voltage.
More preferably, described frequency divider is integer frequency divider.
As mentioned above, inversion of direct current lower-frequency envelope digital detector of the present invention, has following beneficial effect:
Inversion of direct current lower-frequency envelope digital detector of the present invention can calibrate the input voltage followed the tracks of direct current and drift about in scope of design, thus can detect the accurate peak-to-peak value of low-frequency ac envelope wherein; When being all the information of useful control signal for direct current signal size and AC signal size, both mixing, only need single pin to input, and without the need to separately process, are all the cost that greatly can reduce chip package manufacture from sheet or in sheet; Owing to not needing operation input voltage being carried out to such as Simulation scale-up, analog filtering in sheet, and use the band-gap reference reference with process corner, the suitable robust of temperature variation, so the overall highly stable robust of detection perform; Most signal process uses digital circuit, maximizes the scale simplifying mimic channel, greatly can shorten the design cycle, reduces design risk.
Accompanying drawing explanation
Fig. 1 is shown as the structural representation of inversion of direct current lower-frequency envelope digital detector of the present invention.
Fig. 2 is shown as the structural representation of adjustable resistance array of the present invention.
Fig. 3 is shown as the principle of work schematic diagram of inversion of direct current lower-frequency envelope digital detector of the present invention when input signal has larger AC compounent.
Fig. 4 be shown as inversion of direct current lower-frequency envelope digital detector of the present invention input signal have less even there is no an AC compounent time principle of work schematic diagram.
Fig. 5 is shown as the control bit state change schematic diagram in the digital calibration detecting device in inversion of direct current lower-frequency envelope digital detector of the present invention.
Fig. 6 is shown as the align mode change schematic diagram in the digital calibration detecting device in inversion of direct current lower-frequency envelope digital detector of the present invention.
Element numbers explanation
1 inversion of direct current lower-frequency envelope digital detector
11 discrete gap tunable reference voltage generators
111 band gap current references
112 adjustable resistance arrays
12 comparers
13 digital calibration detecting devices
131 square wave detector
132 calibrating devices
133 registers
134 frequency dividers
The comparative result that A comparer exports
The judged result that B square wave detector exports
Phase align mode
P
hhigh align mode
P
llow align mode
Code<N-1:0> control bit
Code_R<N-1:0> deposits bit
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this instructions can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this instructions also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 1 ~ Fig. 6.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
As shown in Figure 1, the invention provides a kind of inversion of direct current lower-frequency envelope digital detector 1, described inversion of direct current lower-frequency envelope digital detector 1 at least comprises:
Discrete gap tunable reference voltage generator 11, comparer 12 and digital calibration detecting device 13.
Particularly, described discrete gap tunable reference voltage generator 11 produces the bandgap voltage reference Vbias of discrete variable according to control bit Code<N-1:0>.
As shown in Figure 1, described discrete gap tunable reference voltage generator 11 comprises: band gap current reference 111 and adjustable resistance array 112.One end of described band gap current reference 111 connects power vd D, the other end connects described adjustable resistance array 112, the other end ground connection GND of described adjustable resistance array 112, described band gap current reference 111 flows through described adjustable resistance array 112 and produces described bandgap voltage reference Vbias.
As shown in Figure 1, the order of magnitude of described band gap current reference 111, the order of magnitude of described adjustable resistance array 112 and adjustable accuracy are set, described adjustable resistance array 112 is controlled by described control bit Code<N-1:0>, actual resistance and described control bit Code<N-1:0> linear.The electric current that described band gap current reference 111 exports can obtain the bandgap voltage reference Vbias with certain degree of regulation corresponding with described control bit Code<N-1:0>, the magnitude of voltage of described bandgap voltage reference Vbias and described control bit Code<N-1:0> one_to_one corresponding after described adjustable resistance array 112.
As shown in Figure 2, in the present embodiment, described adjustable resistance array 112 comprises a minimum resistance and multiple unit resistance, and each resistant series connects, constituent parts resistance respectively with a switch in parallel, realized disconnecting and the gating of described unit resistance by the turn-on and turn-off of switch; The conducting resistance of each switch needs the resistance be designed to much smaller than the unit resistance with this switch in parallel, in the present embodiment, is set as 1/10.In the present embodiment, the resistance of described minimum resistance is R
x, the resistance of constituent parts resistance is 2 times of changes, namely in R, 2R, 4R ... growth, in order to obtain good tuning linearity, the size of the switch that constituent parts resistance is corresponding is also in 2 times of relationship change.
For the bandgap voltage reference Vbias making described discrete gap tunable reference voltage generator 11 produce has the output of robust under technique, temperature variations, the wide length of the type of the resistance that described adjustable resistance array 112 uses, single resistance is identical with the resistance used in described band gap current reference 111, to maintain close technique, temperature characterisitic.
Particularly, described comparer 12 is connected to described discrete gap tunable reference voltage generator 11, for comparing the size of instantaneous input voltage Vin and described bandgap voltage reference Vbias, and exports comparative result A.
As shown in Figure 1, described input voltage vin is connected to the positive input of described comparer 12, and described bandgap voltage reference Vbias is connected to the reverse input end of described comparer 12.If described input voltage vin is greater than described bandgap voltage reference Vbias, the comparative result A that described comparer 12 exports is high level; Otherwise described comparative result A is low level.
Particularly, described digital calibration detecting device 13 is connected to described comparer 12, for detecting the comparative result A that described comparer 12 exports, and the comparative result A exported according to described comparer 12 under the driving of the first clock signal C K1 calibrates the described control bit Code<N-1:0> of output, timing simultaneously upgrades output and deposits bit Code_R<N-1:0>.
As shown in Figure 1, described digital calibration detecting device 13 comprises square wave detector 131, calibrating device 132, register 133 and frequency divider 134.
As shown in Figure 1, described square wave detector 131 is connected to described comparer 12, for judging that whether comparative result that described comparer 12 exports is the square-wave signal within the scope of setpoint frequency, and exports judged result B.
Time period between adjacent two rising edges of the comparative result A that described square wave detector 131 exports at described comparer 12 counts, if count results is in setting counting region, represent that comparative result A that described comparer 12 exports is the square-wave signal within the scope of setpoint frequency, the judged result B set of described square wave detector 131 output; Otherwise, then represent that the comparative result A of the output of described comparer 12 is not the square-wave signal within the scope of setpoint frequency, the judged result B reset that described square wave detector 131 exports.The rising edge of the comparative result A that counting process can export at described comparer 12 restarts, and carries out in real time.When described count results exceedes setting numerical value, and new rising edge does not also arrive, then represent that the square wave frequency of the comparative result A that described comparer 12 exports exceeds setpoint frequency scope, then terminate computation process, no longer count, the judged result B reset that described square wave detector 131 exports, until have rising edge to arrive just restart counting process.
As shown in Figure 1, described frequency divider 134 connects described first clock signal C K1, is calibrating device 132 and described register 133 described in second clock signal CK2 rear drive to described first clock signal C K1 frequency division.
Described first clock signal C K1 wants the highest frequency that can detect described input signal Vin, and namely described first clock signal C K1 is higher than the highest frequency of described input signal Vin, is preferably 3 ~ 4 times, to improve redundance.Namely the cycle of described input signal Vin is 3 ~ 4 times of described first clock signal C K1 cycle.
Due to described square wave detector 131 at least need the cycle of a described input voltage vin after just can judge correct result, so the described second clock signal CK2 cycle is at least long than the one-period of described input voltage vin, be preferably 2 ~ 3 times, to improve redundance.Described frequency divider 134 is integer frequency dividers, considers the select permeability of circuit complexity, and inversion of direct current lower-frequency envelope digital detector 1 of the present invention does not need so accurate simultaneously, therefore, in the present embodiment, selects integral frequency divisioil instead of fractional frequency division.Namely the work clock CK1 of described square wave detector 131 is integral multiples of the work clock CK2 of described calibrating device 132 and described register 133.Integer near the frequency dividing ratio of described frequency divider 134 be set as described input voltage vin cycle and described first clock signal C K1 periodic ratio 2 ~ 3 times.
As shown in Figure 1, described calibrating device 132 is connected to described comparer 12 and described square wave detector 131, and the situation of change for the judged result B exported according to comparative result A and the described square wave detector 131 of described comparer 12 output calibrates described control bit Code<N-1:0>.
As shown in Figure 3, if control bit Code<N-1:0> is minimum value 0 described in described calibrating device 132 initial setting up, then corresponding described bandgap voltage reference Vbias is also minimum value, now align mode Phase=P
l, the comparative result A that described comparer 12 exports is desired value " 1 ", and the judged result B that described square wave detector 131 exports is desired value " 0 ", namely works as Phase=P
ltime, (A, B) expection equals (1,0).
As shown in Figure 4, if control bit Code<N-1:0> is maximal value 2 described in described calibrating device 132 initial setting up
n-1, then the corresponding described bandgap voltage reference Vbias of band is also maximal value, now described align mode Phase=P
h, the comparative result A that described comparer 12 exports is desired value " 0 ", and the judged result B that described square wave detector 131 exports is desired value " 0 ", namely works as Phase=P
htime, (A, B) expection equals (0,0).
Under the synchronous driving of described second clock signal CK2, detect (A, B), described control bit Code<N-1:0> and described align mode Phase.Work as Phase=P
ltime, (A, B) expection equals (1,0); Work as Phase=P
htime, (A, B) expection equals (0,0).Condition (1) represents that (A, B) equals expected results; Condition (2) represents that (A, B) is not equal to expected results; Condition (3) represents Phase=P
l; Condition (4) represents Phase=P
h; Condition (5) represents that described control bit Code<N-1:0> is minimum value; Condition (6) represents that described control bit Code<N-1:0> is maximal value.
As shown in Figure 5, if condition (1) and (3) meet, and condition (6) does not meet, then described control bit Code<N-1:0> carries out+1 operation renewal, namely (A, B) equals desired value, the Phase=P of its correspondence
land described control bit Code<N-1:0> currency is not maximal value, then described control bit Code<N-1:0> carries out+1 operation and upgrades, until described comparer 12 and described square wave detector 131 two of exporting pre-interim any one change; Meanwhile, as shown in Figure 6, described align mode Phase is constant, is still P
l.
As shown in Figure 5, if condition (1) and (4) meet, and condition (5) does not meet, then described control bit Code<N-1:0> carries out-1 operation renewal, namely (A, B) equals desired value, the Phase=P of its correspondence
hand described control bit Code<N-1:0> currency is not minimum value, then described control bit Code<N-1:0> carries out-1 operation and upgrades, until described comparer 12 and described square wave detector 131 two of exporting pre-interim any one change; Meanwhile, as shown in Figure 6, described align mode Phase is constant, is still P
h.
As shown in Figure 5, if condition (2) and (3) meet, or condition (3) and (6) meet, then described control bit Code<N-1:0> carries out maxima operation renewal, namely (A, B) is not equal to the desired value of its correspondence and Phase=P
l, or Phase=P
land described control bit Code<N-1:0> currency equals maximal value, then described control bit Code<N-1:0> carries out maxima operation renewal, simultaneously, as shown in Figure 6, described align mode Phase is changed and is set to P
h.
As shown in Figure 5, if condition (2) and (4) meet, or condition (4) and (5) meet, then described control bit Code<N-1:0> carries out minimum value operation renewal, namely (A, B) is not equal to the desired value of its correspondence and Phase=P
h, or Phase=P
hand described control bit Code<N-1:0> currency equals minimum value, then described control bit Code<N-1:0> carries out minimum value operation renewal, simultaneously, as shown in Figure 6, described align mode Phase is changed and is set to P
l.
Aforesaid operations goes round and begins again and repeats.
As shown in Figure 1, described register 133 is connected to described comparer 12, described square wave detector 131 and described calibrating device 132, situation of change for the judged result B exported according to comparative result A and the described square wave detector 131 of described comparer 12 output deposits described control bit Code<N-1:0>, and deposits bit Code_R<N-1:0> described in exporting.
Described register 133 carries out signal and deposits while described align mode Phase more new transition (in two desired values that namely described comparer and described square wave detector export, any one changes).When described align mode Phase is from P
lbe converted to P
hwhile control bit is at that time recorded as Code
l, namely Code
lbe updated to current control bit; When described align mode Phase is from P
hbe converted to P
lwhile control bit is at that time recorded as Code
h, namely Code
hbe updated to current control bit; Then Code
lrepresent the control bit corresponding to voltage of input voltage lower limb, and Code
hrepresent the control bit corresponding to voltage of input voltage coboundary, wherein, (Code
h-Code
l) represent quantization bit value corresponding to described input voltage vin amplitude, i.e. the envelope size numeral expression of described input voltage vin; (Code
h-Code
l)/2 represent the quantization bit value corresponding to described input voltage vin DC level, i.e. the DC voltage size mathematical expression of described input voltage vin.
Inversion of direct current lower-frequency envelope digital detector of the present invention mainly divides three parts, i.e. digital calibration detecting device, comparer, discrete gap tunable reference voltage generator.Wherein, comparer compares the magnitude relationship of input voltage and bandgap voltage reference, and digital calibration detecting device utilizes the comparative result of comparer, statistical calculation, timely replacement control bit accordingly, controls discrete gap tunable reference voltage generator to regulate the size of bandgap voltage reference.Digital calibration detecting device is by built-in square wave detector, and the time period between adjacent two rising edges of the comparative result exported at comparer counts, to judge that whether comparative result that comparer exports is the square-wave signal within the scope of setpoint frequency.The built-in frequency divider of digital calibration detecting device makes square wave detector and other calibrate under registration module is operated in two relevant synchronous clocks of speed, guarantees the accurate stable of signal transacting.The adjustable extent of classifying rationally bandgap voltage reference and degree of regulation, make the actual corresponding bandgap voltage reference of each control bit, utilize comparer to realize the equivalency transform of an analog to digital signal.
Detect relative to traditional pure analogue envelope, inversion of direct current lower-frequency envelope digital detector of the present invention is for the low frequency characteristic of input voltage, and the clock operating frequencies of existing integrated circuit middling speed is enough to simulate real time signal processing, simulating signal is converted into low accuracy digital signal process, greatly simplify the complexity of circuit arrangement, realize degree of freedom, allow the impact that signal transacting maximizing performance causes from technique, temperature variation.Calibration tracking scheme solves the DC shift problem that classic method cannot process especially, exempts bulky capacitor on sheet.Because most of signal processing tasks is all divided in digital circuits section, greatly reduce circuit power consumption.
In sum, the invention provides a kind of inversion of direct current lower-frequency envelope digital detector, at least comprise: discrete gap tunable reference voltage generator, comparer for comparator input signal and described bandgap voltage reference size, and export the digital calibration detecting device with the described bandgap voltage reference of calibration for detecting described comparer.The present invention both can be used for satellite digital video broadcast (DVB-S) system making high frequency head monolithic low noise block (Low Noise Block, LNB) in, to detect direct-current polarity and 22K Hybrid mode signal, the comparatively low-frequency ac signal amplitude detection that DC component is drifted about within the specific limits also can be used as.Use digital dynamic is calibrated, and adapts to DC shift on a large scale, thus does not need direct current and AC signal to separate to process, and saves chip input pin number, reduces costs, save super large capacitor in sheet, the scaled down version area of pictural surface.Utilize band-gap reference reference in sheet, make detection precisely and stablize.Digital circuit major part signal processing function, makes design more aobvious terse easily clear.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (10)
1. an inversion of direct current lower-frequency envelope digital detector, is characterized in that, described direct current lower-frequency envelope digital detector at least comprises:
Discrete gap tunable reference voltage generator, comparer and digital calibration detecting device;
Described discrete gap tunable reference voltage generator produces the bandgap voltage reference of discrete variable according to the control bit that described digital calibration detecting device provides;
Described comparer is connected to described discrete gap tunable reference voltage generator, for comparing the size of input voltage and described bandgap voltage reference, and exports comparative result;
Described digital calibration detecting device is connected to described comparer, and for detecting the comparative result that described comparer exports and the described control bit of comparative result calibration output exported according to described comparer, timing simultaneously upgrades output and deposits bit.
2. inversion of direct current lower-frequency envelope digital detector according to claim 1, it is characterized in that: described discrete gap tunable reference voltage generator comprises band gap current reference and adjustable resistance array, one end of described band gap current reference connects power supply, the other end connects described adjustable resistance array, the other end ground connection of described adjustable resistance array, described band gap current reference flows through described adjustable resistance array and produces described bandgap voltage reference.
3. inversion of direct current lower-frequency envelope digital detector according to claim 2, is characterized in that: described adjustable resistance array is controlled by described control bit, actual resistance and described control bit linear.
4. the inversion of direct current lower-frequency envelope digital detector according to Claims 2 or 3, is characterized in that: the resistance type used in described adjustable resistance array is identical with the resistance type used in described band gap current reference.
5. inversion of direct current lower-frequency envelope digital detector according to claim 1, is characterized in that:
Described digital calibration detecting device comprises square wave detector, calibrating device, register and frequency divider;
Described square wave detector is connected to described comparer, for judging that whether comparative result that described comparer exports is the square-wave signal within the scope of setpoint frequency, and exports judged result;
Described calibrating device is connected to described comparer and described square wave detector, and the situation of change of the judged result exported for the comparative result that exports according to described comparer and described square wave detector calibrates described control bit;
Described register is connected to described comparer, described square wave detector and described calibrating device, the situation of change of the judged result exported for the comparative result that exports according to described comparer and described square wave detector deposits described control bit, and deposits bit described in exporting;
Described frequency divider connects the first clock signal, is used for driving described calibrating device and described register by after described first clock signal frequency division.
6. inversion of direct current lower-frequency envelope digital detector according to claim 5, it is characterized in that: the time period between adjacent two rising edges of the comparative result that described square wave detector exports at described comparer counts, if count results is in setting counting region, represent that comparative result that described comparer exports is the square-wave signal within the scope of setpoint frequency, the judged result set of described square wave detector output; Otherwise, then represent that the comparative result of the output of described comparer is not the square-wave signal within the scope of setpoint frequency, the judged result reset that described square wave detector exports.
7. inversion of direct current lower-frequency envelope digital detector according to claim 5, it is characterized in that: it is minimum value that described calibrating device arranges described control bit, the comparative result that now described comparer exports is desired value " 1 ", the judged result that described square wave detector exports is desired value " 0 ", under the clock signal driving that described frequency divider exports, described calibrating device carries out+1 operation to described control bit, until described comparer and described square wave detector two of exporting pre-interim any one change; Described calibrating device arranges described control bit is afterwards maximal value, the comparative result that now described comparer exports is desired value " 0 ", the judged result that described square wave detector exports is desired value " 0 ", under the clock signal driving that described frequency divider exports, described calibrating device carries out-1 operation to described control bit, until described comparer and described square wave detector two of exporting pre-interim any one change; Then go round and begin again repetition aforesaid operations.
8. inversion of direct current lower-frequency envelope digital detector according to claim 7, it is characterized in that: depositing bit described in upgrading respectively in any one two kinds of situation changed in two desired values that described register exports in described comparer and described square wave detector is current control bit, the bit of depositing in two kinds of situations goes round and begins again and alternately upgrades.
9. inversion of direct current lower-frequency envelope digital detector according to claim 8, is characterized in that: the difference of depositing bit described in two kinds of situations that described register is deposited respectively is exactly the envelope size numeral expression of described input voltage; Deposit described in two kinds of situations that described register is deposited respectively bit and half be exactly the DC voltage size mathematical expression of described input voltage.
10. inversion of direct current lower-frequency envelope digital detector according to claim 5, is characterized in that: described frequency divider is integer frequency divider.
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| CN111404596A (en) * | 2020-03-27 | 2020-07-10 | 南京宽超通信技术有限公司 | Multifunctional controller for satellite downlink tuner |
| CN115185324A (en) * | 2021-04-07 | 2022-10-14 | 华大半导体有限公司 | Voltage regulating circuit of band-gap reference voltage source |
| CN115993482A (en) * | 2023-03-22 | 2023-04-21 | 季华实验室 | Accurate zeroing circuit and power detector |
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| US7783205B1 (en) * | 2006-01-26 | 2010-08-24 | Universal Electronics Inc. | Learning infrared amplifier for remote control devices |
| CN101873124A (en) * | 2010-05-24 | 2010-10-27 | 哈尔滨工程大学 | Self-adaptive threshold pulse amplified shaping circuit |
| CN103795664A (en) * | 2012-10-31 | 2014-05-14 | Ls产电株式会社 | Demodulation apparatus and method for operating the same |
-
2015
- 2015-01-04 CN CN201510003276.XA patent/CN104502688B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1041663A (en) * | 1988-08-01 | 1990-04-25 | 国际商业机器公司 | Suppress the Method and circuits that the data channel additivity is disturbed |
| US7783205B1 (en) * | 2006-01-26 | 2010-08-24 | Universal Electronics Inc. | Learning infrared amplifier for remote control devices |
| CN101098422A (en) * | 2006-06-29 | 2008-01-02 | 三洋电机株式会社 | Picture signal detecting apparatus |
| CN101873124A (en) * | 2010-05-24 | 2010-10-27 | 哈尔滨工程大学 | Self-adaptive threshold pulse amplified shaping circuit |
| CN103795664A (en) * | 2012-10-31 | 2014-05-14 | Ls产电株式会社 | Demodulation apparatus and method for operating the same |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111404596A (en) * | 2020-03-27 | 2020-07-10 | 南京宽超通信技术有限公司 | Multifunctional controller for satellite downlink tuner |
| CN111404596B (en) * | 2020-03-27 | 2022-01-28 | 南京宽超通信技术有限公司 | Satellite downlink high-frequency head controller |
| CN115185324A (en) * | 2021-04-07 | 2022-10-14 | 华大半导体有限公司 | Voltage regulating circuit of band-gap reference voltage source |
| CN115185324B (en) * | 2021-04-07 | 2023-12-29 | 华大半导体有限公司 | Voltage regulating circuit of band-gap reference voltage source |
| CN115993482A (en) * | 2023-03-22 | 2023-04-21 | 季华实验室 | Accurate zeroing circuit and power detector |
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|---|---|
| CN104502688B (en) | 2017-04-19 |
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