CN103488244B - A kind of random waveform generation systems and method - Google Patents
A kind of random waveform generation systems and method Download PDFInfo
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Abstract
The invention discloses a kind of random waveform generation systems of Wave data variable bit rate playback of triggering based on complex combination and method, system wherein comprise Wave data access unit with based on triggering mode waveform compilation with trigger playback unit; Based on triggering mode waveform compilation with trigger playback unit and comprise reading address generating subunit and the complex wave synthon unit of waveform, waveform reading address generating subunit comprises pulse gating module, trigger module, triggering reseting module, waveform trigger module, waveform triggers reseting module, waveform triggers buffer module, sequence trigger module, sequence trigger replicated blocks and sequence triggering arranges module.The present invention is based on Real-time digital signal processing, complex combination triggers and variable bit rate Wave data playback technology, give full play to the features such as all-digital waveform is synthesized, resolution is high, signal stabilization good, signal pattern is many, kind of modulation is many, and there is the advantage such as quick switching, the length of change signal period of signal frequency.
Description
Technical field
The invention belongs to random waveform and produce field, in particular to a kind of random waveform generation systems of the Wave data variable bit rate playback based on complex combination triggering, and a kind of random waveform method for generation of the Wave data variable bit rate playback based on complex combination triggering.
Background technology
AWG (Arbitrary Waveform Generator) is a kind of multiduty signal driving source, comprises the multiple digital modulation function such as FSK, MSK, QAM, PSK, becomes multiple signals, complex modulated signal when can produce complicated.Along with the development of electronic technology, digital baseband modulation signal generation technique is applied in the every field such as communication, control, measurement widely.It is multi-level that it shows as land, sea, air, sky in the effect of military aspect, the high density of disposing, multiple spectra, large time wide, the victory of large bandwidth, many kinds of parameters becomes, the integrated application of multiple working system and multiple Anti-Jamming Technique is feature very complicated signal Antagonistic Environment.For the testing performance index of the equipments such as various Complex Radar, electronic reconnaissance, communication countermeasure, enemy and we's identification, expansion frequency hopping communications, multiple digital modulation signals can be provided, solve maintenance and the training problem of countermeasures set, improve the scientific research of electronic counter-measures equipment, production, maintenance ability.
Current random waveform produces and mainly contains two kinds: the first is the mode utilizing the digital real-time mode of FPGA+DSP to produce, and the second is that the mode utilizing large capacity digital to store wave shape playback (any ripple) realizes.These two kinds of modes respectively have relative merits, and the bandwidth that real-time mode realizes is little relative to wave shape playback mode, but signal pattern can variously convert; Wave shape playback mode can only produce the waveform that storer exists, if the digital signal of storer will convert pattern, can hard disc data be called by local bus or be called the data of external counting machine by external interface, so waveform speed of download and external interface speed be subject to the impact of the bandwidth sum speed of instrument local bus.
In existing instrument and equipment, in 33250 of Agilent company, adopt single triggering, circulation triggering, do not adopt sequence to trigger, combine triggering, Phase Continuation multistage waveform can not be exported; The AFQ100A/B of R & S company only have employed single triggering, circulation triggers, combination Trigger Function, and the signal pattern of output is diversified not; Have employed single triggering, circulation triggering, burst triggering in the AWG7122C of Tek company, do not adopt sequence triggering, combination triggering etc., the multistage waveform in band different time gap can not be exported.
Signal pattern is there is few in existing function generator and AWG (Arbitrary Waveform Generator), as semiperiod, complete period, 1/4th periodic signals, arbitrarily/periodic signal etc., have that to trigger kind few, and in certain triggers the problems such as sampling rate is immutable.
Summary of the invention
The present invention is directed to above-mentioned shortcoming, a kind of random waveform generation systems of the Wave data variable bit rate playback based on complex combination triggering is provided, and a kind of random waveform method for generation of the Wave data variable bit rate playback based on complex combination triggering.
Its technical solution is:
Based on a random waveform generation systems for the Wave data variable bit rate playback that complex combination triggers, comprising:
Wave data access unit, for the control of the buffering and memory interface that complete Wave data; FPGA will be sent into from PCI chip local bus 32 bit data, after the address bus that pci interface module converts becomes 256 bit data bus and 25, write data FIFO and address FIFO in FPGA inside respectively; The Wave data of the Clockreading write inputted with internal memory control module at the opposite side of FIFO and address, send into Memory control module after handshake; Memory control module by the Wave data of input and address according to the sequential write memory bar of memory bar; In read mode, read address feeding Memory control module by reading address generating module generation, the Wave data read from memory bar is sent on output data bus by Memory control module after time delay, exports data_valid signal simultaneously; The data write FIFO that Read_FIFO will read from memory bar; At the opposite side of read_FIFO, FPGA reads FIFO with 1/16 of DA clock, and 256 bit data read are sent into parallel serial conversion module, and the data feeding DA converting 16 to carries out digital-to-analog conversion; Continuous print read and write is converted to step read-write by a large amount of FIFO in FPGA inside;
Based on waveform compilation and the triggering playback unit of triggering mode, by inner editing machine, or by interface GPIB or USB, by outer computer, waveform expression formula being transformed to Wave data is stored in wave memorizer, control the address that address generator changes wave memorizer, export corresponding Wave data, until the end of waveform segment; Waveform is represented in the mode of text, by amendment text in order to reach the object exporting different wave signal by outer computer.
The above-mentioned waveform compilation based on triggering mode comprises reading address generating subunit and the complex wave synthon unit of waveform with triggering playback unit, the reading address generating subunit of waveform wherein comprises:
Pulse gating module, using trigger pip as gate-control signal, when trigger pip is effective, plays waveform; Trigger useful signal directly as the enable signal of waveform address totalizer, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, then resets totalizer, makes totalizer restart to add up; The input of totalizer is simultaneously added with waveform start address, produces the reading address of waveform;
Trigger module, using trigger pip as a start signal, trigger pip sends rising or negative edge useful signal, waveform address totalizer starts to add up, and carry out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up; The input of totalizer is simultaneously added with waveform start address, produces the reading address of waveform; The trigger pip of outside input acts on waveform totalizer after edge sense circuit.
Trigger reseting module, using first trigger pip as start signal, follow-up trigger pip is as reset signal, and trigger pip sends first and rises or negative edge useful signal, and waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, the output of totalizer compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up; Meanwhile, trigger pip is conduct totalizer reset signal simultaneously also, carrys out a trigger pip, resets one-accumulate device; The output of totalizer is added with waveform start address, produces the reading address of waveform; Trigger pip below all will reset totalizer, make waveform restart to play; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Waveform trigger module, using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then trigger pip is invalid; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Waveform triggers reseting module, using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then reset totalizer, waveform is made to restart to play; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Waveform triggers buffer module, using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then trigger pip is until waveform broadcasting terminates effectively rear; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Sequence trigger module, receives after triggering, plays waveform once, again triggers and plays next waveform; Using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, sequence address totalizer adds 1, reads start address and the waveform length of next waveform inside sequence memory, until the next effectively enable totalizer of trigger pip; The output of totalizer is added with waveform start address, produces the reading address of waveform; Effectively occur in waveform when playing if triggered, then trigger pip is invalid and ignore waveform broadcasting time; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Sequence triggers replicated blocks, receives after triggering, and plays waveform until next waveform is play in triggering again; Using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, the output of totalizer compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up; After again triggering, sequence totalizer adds 1, reads start address and the waveform length of next waveform inside sequence memory; The output of totalizer is added with waveform start address, produces the reading address of waveform; Effectively occur in waveform when playing if triggered, then trigger pip until current form play terminate rear effectively and ignore waveform broadcasting time; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Sequence triggers and arranges module, receives after triggering, stops after playing waveform predetermined number of times, with waveform under wait again triggers and plays; Using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up, waveform number of times totalizer adds 1 simultaneously; The value of waveform number of times totalizer compares with waveform number of times, if number of times totalizer equals waveform number of times, then forbids that waveform address totalizer adds up; After again triggering, sequence totalizer adds 1, reads the start address of next waveform inside sequence memory, waveform length and broadcasting time; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then trigger pip is until current form broadcasting terminates effectively rear; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Complicated wave form synthon unit wherein, sends the reading address that above-mentioned a certain module produces waveform into address counter, length counter and repeat counter; When waveform multiplicity is greater than 1, after a wave form output, the parameter of address counter and length counter reloads, at the end of a wave form output, waveform end signal causes sequence address generator to point to the address of next waveform, makes functional nucleotide sequence produce next waveform, after memory address is complete, repeat above process again, make output waveform continuous, by functional nucleotide sequence, comparatively simple Waveform composition is produced the waveform of relative complex.
Based on a random waveform method for generation for the Wave data variable bit rate playback that complex combination triggers, comprise the following steps:
Wave data access step, for the control of the buffering and memory interface that complete Wave data; FPGA will be sent into from PCI chip local bus data 32, after the address bus that pci interface module converts becomes 256 bit data bus and 25, write data FIFO and address FIFO in FPGA inside respectively; The Wave data of the Clockreading write inputted with internal memory control module at the opposite side of FIFO and address, send into Memory control module after handshake; Memory control module by the Wave data of input and address according to the sequential write memory bar of memory bar; In read mode, read address feeding Memory control module by reading address generating module generation, the Wave data read from memory bar is sent on output data bus by Memory control module after time delay, exports data_valid signal simultaneously; The data write FIFO that Read_FIFO will read from memory bar; At the opposite side of read_FIFO, FPGA reads FIFO with 1/16 of DA clock, and 256 bit data read are sent into parallel serial conversion module, and the data feeding DA converting 16 to carries out digital-to-analog conversion; Continuous print read and write is converted to step read-write by a large amount of FIFO in FPGA inside;
Based on waveform compilation and the triggering replay procedure of triggering mode, by inner editing machine, or by interface GPIB or USB, by outer computer, waveform expression formula being transformed to Wave data is stored in wave memorizer, control the address that address generator changes wave memorizer, export corresponding Wave data, until the end of waveform segment; Waveform is represented in the mode of text, by amendment text in order to reach the object exporting different wave signal by outer computer.
The above-mentioned waveform compilation based on triggering mode comprises reading address generation step and the complex wave synthesis step of waveform with triggering replay procedure, the reading address generation step of waveform wherein comprises a certain step in the listed step of below selective gist:
Pulse gate step, using trigger pip as gate-control signal, when trigger pip is effective, plays waveform; Trigger useful signal directly as the enable signal of waveform address totalizer, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, then resets totalizer, makes totalizer restart to add up; The input of totalizer is simultaneously added with waveform start address, produces the reading address of waveform;
Triggered step, using trigger pip as a start signal, trigger pip sends rising or negative edge useful signal, waveform address totalizer starts to add up, and carry out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up; The input of totalizer is simultaneously added with waveform start address, produces the reading address of waveform; The trigger pip of outside input acts on waveform totalizer after edge sense circuit.
Trigger reset process, using first trigger pip as start signal, follow-up trigger pip is as reset signal, and trigger pip sends first and rises or negative edge useful signal, and waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, the output of totalizer compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up; Meanwhile, trigger pip is conduct totalizer reset signal simultaneously also, carrys out a trigger pip, resets one-accumulate device; The output of totalizer is added with waveform start address, produces the reading address of waveform; Trigger pip below all will reset totalizer, make waveform restart to play; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Waveform triggered step, using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then trigger pip is invalid; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Waveform triggers reset process, using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then reset totalizer, waveform is made to restart to play; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Waveform triggers buffer step, using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then trigger pip is until waveform broadcasting terminates effectively rear; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Sequence triggered step, receives after triggering, plays waveform once, again triggers and plays next waveform; Using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, sequence address totalizer adds 1, reads start address and the waveform length of next waveform inside sequence memory, until the next effectively enable totalizer of trigger pip; The output of totalizer is added with waveform start address, produces the reading address of waveform; Effectively occur in waveform when playing if triggered, then trigger pip is invalid and ignore waveform broadcasting time; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Sequence triggers repetition step, receives after triggering, and plays waveform until again trigger next waveform of broadcasting; Using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, the output of totalizer compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up; After again triggering, sequence totalizer adds 1, reads start address and the waveform length of next waveform inside sequence memory; The output of totalizer is added with waveform start address, produces the reading address of waveform; Effectively occur in waveform when playing if triggered, then trigger pip until current form play terminate rear effectively and ignore waveform broadcasting time; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Sequence triggers setting steps, receives after triggering, stops after playing waveform predetermined number of times, with waveform under wait again triggers and plays; Using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up, waveform number of times totalizer adds 1 simultaneously; The value of waveform number of times totalizer compares with waveform number of times, if number of times totalizer equals waveform number of times, then forbids that waveform address totalizer adds up; After again triggering, sequence totalizer adds 1, reads the start address of next waveform inside sequence memory, waveform length and broadcasting time; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then trigger pip is until current form broadcasting terminates effectively rear; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Complex wave synthesis step wherein, sends the reading address that above-mentioned selected a certain step produces waveform into address counter, length counter and repeat counter; When waveform multiplicity is greater than 1, after a wave form output, the parameter of address counter and length counter reloads, at the end of a wave form output, waveform end signal causes sequence address generator to point to the address of next waveform, makes functional nucleotide sequence produce next waveform, after memory address is complete, repeat above process again, make output waveform continuous, by functional nucleotide sequence, comparatively simple Waveform composition is produced the waveform of relative complex.
The present invention has following Advantageous Effects:
The present invention is based on Real-time digital signal processing technology, complex combination triggering technique and variable bit rate Wave data playback technology, realized by digital Large Copacity Waveform composition and complicated triggering mode, by Wave data directly stored in high-capacity and high-speed DDR2, the playback of Wave data is realized by single triggering or complex combination triggering mode, effectively can solve the semiperiod, complete period, 1/4th cycles, the generation of the sophisticated signals such as arbitrarily/mono-cycle (waveform length that specified by start address to termination address, storage space is corresponding is defined as the cycle), give full play to all-digital waveform synthesis, resolution is high, signal stabilization is good, signal pattern is many, the advantages such as kind of modulation is many, and adopt variable sample rates to realize the quick switching of signal frequency, change the advantages such as the length of signal period.
Be in particular in:
(1) used can change signal in complicated triggering cycle index, signal any/cycle, the frequency of signal, signal the time function such as edge, achieve the variation of output signal pattern;
(2) Phase Continuation fast frequency shift signal produces, the generation of the sophisticated signal such as generation, burr signal of the time varying signal of SPA sudden phase anomalies to utilize variable bandwidth speed playback technology to realize;
(3) employing all-digital waveform synthesis mode, structure is simple, favorable expandability, outputs signal spuious low, the interior good frequency response of band.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further described:
Fig. 1 is the schematic block diagram of hardware composition involved in the present invention.
The schematic block diagram of the hardware composition of Fig. 2 involved by the Wave data access unit in the present invention.
Fig. 3 is the schematic block diagram that the waveform compilation based on triggering mode in the present invention forms with the hardware triggering playback unit.
Fig. 4 is the first the broadcasting waveform schematic diagram in the present invention.
Fig. 5 is that the second in the present invention plays waveform schematic diagram.
Fig. 6 is the third broadcasting waveform schematic diagram in the present invention.
Fig. 7 is that the 4th kind in the present invention plays waveform schematic diagram.
Fig. 8 is that the 5th kind in the present invention plays waveform schematic diagram.
Fig. 9 is that the 6th kind in the present invention plays waveform schematic diagram.
Figure 10 is that the 7th kind in the present invention plays waveform schematic diagram.
Figure 11 is that the 8th kind in the present invention plays waveform schematic diagram.
Figure 12 is that the 9th kind in the present invention plays waveform schematic diagram.
Embodiment
Composition graphs 1, Fig. 2 and Fig. 3, hardware composition involved in the present invention can comprise: FPGA(model is XC6VSX315t), PC (host computer or outer computer), D/A converter (AD9736), low-pass filter, clock generation circuit and interface voltage converter.Above-mentioned FPGA is provided with parallel-serial conversion interface, DCM clock distributor, SPI interface, sequence memory, triggering administration module, Clock management module, data management module and sequence administration module.PC connects FPGA, FPGA by pci interface and interface voltage converter and connects D/A converter by parallel-serial conversion interface, SPI interface and DCM clock distributor, and clock generation circuit connects FPGA and D/A converter respectively, and D/A converter connects low-pass filter.
Principle of work of the present invention is roughly: Wave data is first write phase look-up table by interface by host computer (outer computer), during DDS work, the accumulation result of phase accumulator removes addressing phase look-up table as address, read the data processing module that Wave data corresponding to phase place sends rear class to, then discrete Wave data is delivered to DAC.
The present invention adopts memory bar DDR2 as waveform, interface level 1.8V, and capacity is 512M*8bit, reference voltage 0.9V, in FPGA internal data processing module, 256 bit data parallel serial conversions is become DA(AD9736) desired data 14 bit data.Using the data module of FPGA inside as Wave data access unit.
Based on the random waveform generation systems of Wave data variable bit rate playback that complex combination triggers, comprise Wave data access unit with based on triggering mode waveform compilation with trigger playback unit.
Above-mentioned Wave data access unit:
Composition graphs 2, Wave data access circuit mainly completes the buffering of data and the control of memory interface, mainly contains PCI control module, various FIFO, Memory control module, parallel serial conversion module and corresponding logic control composition.
Send into FPGA from PCI chip local bus data 32, after the address bus that pci interface module converts becomes 256 bit data bus and 25, write data FIFO and address FIFO in FPGA inside respectively.The data of the Clockreading write inputted with internal memory control module at the opposite side of FIFO and address, send into Memory control module (adopting ready-made controller) after handshake.Memory control module by the data of input and address according to the sequential write memory bar of memory bar.In read mode, read address feeding Memory control module by reading address generating module generation, the data read from memory bar are sent on output data bus by Memory control module after time delay, export data_valid signal simultaneously.The data write FIFO that Read_FIFO will read from memory bar.At the opposite side of read_FIFO, FPGA reads FIFO with 1/16 of DA clock, and 256 bit data read are sent into parallel serial conversion module, and the data feeding DA converting 16 to carries out digital-to-analog conversion.Because memory bar exists the refresh cycle, it is step for causing at read/write memory bar.So convert continuous print read and write to step read-write in FPGA inside by a large amount of FIFO.
The above-mentioned waveform compilation based on triggering mode and triggering playback unit comprise reading address generating subunit and the complex wave synthon unit of waveform, and the reading address generating subunit of waveform wherein comprises pulse gating module, trigger module, triggering reseting module, waveform trigger module, waveform triggering reseting module, waveform triggering buffer module, sequence trigger module, sequence triggering replicated blocks and sequence triggering and arranges module.
A distinguishing feature of the present invention is custom feature output signal to programmability and simplification user operation flexibly, thus meets the user's request of different levels.Or by outer computer, waveform expression formula can be transformed to Wave data by interface (GPIB or USB) and be stored in wave memorizer by inner editing machine, control the address that address generator changes wave memorizer, export corresponding Wave data, until the end of waveform segment.Represent waveform by computing machine in the mode of text like this, and can reach by amendment text the object exporting different wave signal.
Composition graphs 3, under waveform play mode, address production electric circuit, for generation of the address of reading data, is also the key point of FPGA indoor design.
Storage address controls and sequencer is the essential elements producing complicated wave form, and the clock signal in Fig. 3 is for illustrating.Address generator circuit mainly comprises sequence memory (being realized by FPGA internal RAM), totalizer, comparer and various steering logic composition.Sequence memory and wave memorizer are used for shape information and store, the parameter of sequence memory comprises start address (26), waveform length (26), the multiplicity (20) of each waveform, and sequence counter counting region can be determined from 1 to 2K(by sequence memory size).The Parameter Switch of list entries storer is start address, waveform length and multiplicity by sequencer.When starting output waveform, different according to the function selected, the mode producing address is also different.
Above-mentioned pulse gating module:
Composition graphs 4, trigger pip (being a level useful signal), as gate-control signal (not having functional nucleotide sequence), when trigger pip is effective, plays waveform.Trigger useful signal directly as the enable signal of waveform address totalizer, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, then resets totalizer, makes totalizer restart to add up.The input of totalizer is simultaneously added with waveform start address, produces the reading address of waveform.This mode is fairly simple mode, is usually used in producing signal in arteries and veins.
Above-mentioned trigger module:
Composition graphs 5, trigger pip (being using pulse useful signal) is as a start signal, trigger pip sends rising or negative edge (user's setting) useful signal, waveform address totalizer starts to add up, and carry out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up.The input of totalizer is simultaneously added with waveform start address, produces the reading address of waveform.In this manner, only effectively once, trigger pip below all will less than effect for trigger pip.This mode is fairly simple mode, conventional and generation continuous wave.In this manner, the trigger pip of outside input acts on waveform totalizer after edge sense circuit.This kind of triggering is commonly used to produce continuous wave signal.
Above-mentioned triggering reseting module:
Composition graphs 6, first trigger pip is as start signal, follow-up trigger pip is as reset signal, and trigger pip sends first and rises or negative edge (user's setting) useful signal, and waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, the output of totalizer compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up.Meanwhile, trigger pip is conduct totalizer reset signal simultaneously also, carrys out a trigger pip, resets one-accumulate device.The output of totalizer is added with waveform start address, produces the reading address of waveform.In this manner, trigger pip is below all by reset totalizer (making waveform restart to play).In this manner, the trigger pip of outside input acts on waveform totalizer after edge sense circuit.This kind of triggering can be used for producing the radar signal of two phase coding.Come to be that sinusoidal wave SPA sudden phase anomalies 180 degree, in the middle of reality realizes, as long as suitably control the cycle of trigger pulse, just can simulate the radar signal of two phase coding when trigger pulse edge.
Above-mentioned waveform trigger module:
Composition graphs 7, trigger pip is as start signal, trigger pip sends rising or negative edge (user's setting) useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously.The output of totalizer is added with waveform start address, produces the reading address of waveform.In this manner, if when triggering effectively occurs in waveform broadcasting, then trigger pip is invalid.In this manner, the trigger pip of outside input acts on waveform totalizer after edge sense circuit.This kind of triggering can be used for producing short-pulse radar signal.Only need to change carrier cycle, just can change pulse broadband.When sinusoidal wave frequency raises, the broadband of burst pulse is narrower.
Above-mentioned waveform triggers reseting module:
Composition graphs 8, trigger pip is as start signal, trigger pip sends rising or negative edge (user's setting) useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously.The output of totalizer is added with waveform start address, produces the reading address of waveform.In this manner, if when triggering effectively occurs in waveform broadcasting, then reset totalizer, waveform is made to restart to play.In this manner, the trigger pip of outside input acts on waveform totalizer after edge sense circuit.This kind of triggering can be used for producing semiperiod sinusoidal signal.Only need to change the recurrence interval, just can change sine wave period.
Above-mentioned waveform triggers buffer module:
Composition graphs 9, trigger pip is as start signal, trigger pip sends rising or negative edge (user's setting) useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously.The output of totalizer is added with waveform start address, produces the reading address of waveform.In this manner, if when triggering effectively occurs in waveform broadcasting, then trigger pip is until waveform broadcasting terminates effectively rear.In this manner, the trigger pip of outside input acts on waveform totalizer after edge sense circuit.The periodicity crossing number decision sinewave output of trigger pulse.
Above-mentioned sequence trigger module:
In conjunction with Figure 10, receive after triggering, play waveform once, again trigger and play next waveform.In such a mode, trigger pip is as start signal, and trigger pip sends rising or negative edge (user's setting) useful signal, and waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, the output of totalizer compared with waveform length, if equal waveform length, then reset totalizer, forbid that totalizer adds up, sequence address totalizer adds 1, reads start address and the waveform length of next waveform inside sequence memory.Until the next effectively enable totalizer of trigger pip.The output of totalizer is added with waveform start address, produces the reading address of waveform.In this manner, effectively occur in waveform when playing if triggered, then trigger pip is invalid and ignore waveform broadcasting time.In this manner, the trigger pip of outside input acts on waveform totalizer after edge sense circuit.Can produce complicated wave form, each waveform is the monocycle.
Above-mentioned sequence triggers replicated blocks:
In conjunction with Figure 11, receive after triggering, play waveform until again trigger next waveform of broadcasting.In such a mode, trigger pip is as start signal, trigger pip sends rising or negative edge (user's setting) useful signal, waveform address totalizer starts to add up, and carry out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up.After again triggering, sequence totalizer adds 1, reads start address and the waveform length of next waveform inside sequence memory.The output of totalizer is added with waveform start address, produces the reading address of waveform.In this manner, effectively occur in waveform when playing if triggered, then trigger pip until current form play terminate rear effectively and ignore waveform broadcasting time.In this manner, the trigger pip of outside input acts on waveform totalizer after edge sense circuit.Can produce complicated multistage waveform, every section of waveform is the multicycle, can slitless connection during replacing waveform pattern.And in phase zero points.
Above-mentioned sequence triggers and arranges module:
In conjunction with Figure 12, receive after triggering, stop after playing waveform predetermined number of times, wait for triggering again under playing with waveform.In such a mode, trigger pip is as start signal, trigger pip sends rising or negative edge (user's setting) useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, make totalizer restart to add up, waveform number of times totalizer adds 1 simultaneously.The value of waveform number of times totalizer compares with waveform number of times, if number of times totalizer equals waveform number of times, then forbids that waveform address totalizer adds up.After again triggering, sequence totalizer adds 1, reads the start address of next waveform inside sequence memory, waveform length and broadcasting time.The output of totalizer is added with waveform start address, produces the reading address of waveform.In this manner, if when triggering effectively occurs in waveform broadcasting, then trigger pip is until current form broadcasting terminates effectively rear.In this manner, the trigger pip of outside input acts on waveform totalizer after edge sense circuit.Can produce complicated multistage waveform, every section of waveform is the multicycle.
Above-mentioned complicated wave form synthon unit, sends the reading address that above-mentioned a certain module produces waveform into address counter, length counter and repeat counter; Output waveform address is also different.When waveform multiplicity is greater than 1, after a wave form output, the parameter of address counter and length counter must reload.At the end of a wave form output, waveform end signal causes sequence address generator to point to the address of next waveform, functional nucleotide sequence is made to produce next waveform, after memory address is complete, repeat above process again, make output waveform continuous, comparatively simple Waveform composition can be produced the waveform of relative complex by functional nucleotide sequence.Complicated multistage waveform can be produced, without the need to docking between waveform.
Based on a random waveform method for generation for the Wave data variable bit rate playback that complex combination triggers, comprise the following steps:
Wave data access step, for the control of the buffering and memory interface that complete Wave data; FPGA will be sent into from PCI chip local bus data 32, after the address bus that pci interface module converts becomes 256 bit data bus and 25, write data FIFO and address FIFO in FPGA inside respectively; The Wave data of the Clockreading write inputted with internal memory control module at the opposite side of FIFO and address, send into Memory control module after handshake; Memory control module by the Wave data of input and address according to the sequential write memory bar of memory bar; In read mode, read address feeding Memory control module by reading address generating module generation, the Wave data read from memory bar is sent on output data bus by Memory control module after time delay, exports data_valid signal simultaneously; The data write FIFO that Read_FIFO will read from memory bar; At the opposite side of read_FIFO, FPGA reads FIFO with 1/16 of DA clock, and 256 bit data read are sent into parallel serial conversion module, and the data feeding DA converting 16 to carries out digital-to-analog conversion; Continuous print read and write is converted to step read-write by a large amount of FIFO in FPGA inside;
Based on waveform compilation and the triggering replay procedure of triggering mode, by inner editing machine, or by interface GPIB or USB, by outer computer, waveform expression formula being transformed to Wave data is stored in wave memorizer, control the address that address generator changes wave memorizer, export corresponding Wave data, until the end of waveform segment; Waveform is represented in the mode of text, by amendment text in order to reach the object exporting different wave signal by outer computer.
The above-mentioned waveform compilation based on triggering mode comprises reading address generation step and the complex wave synthesis step of waveform with triggering replay procedure, the reading address generation step of waveform wherein comprises a certain step in the listed step of below selective gist:
Pulse gate step, using trigger pip as gate-control signal, when trigger pip is effective, plays waveform; Trigger useful signal directly as the enable signal of waveform address totalizer, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, then resets totalizer, makes totalizer restart to add up; The input of totalizer is simultaneously added with waveform start address, produces the reading address of waveform;
Triggered step, using trigger pip as a start signal, trigger pip sends rising or negative edge useful signal, waveform address totalizer starts to add up, and carry out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up; The input of totalizer is simultaneously added with waveform start address, produces the reading address of waveform; The trigger pip of outside input acts on waveform totalizer after edge sense circuit.
Trigger reset process, using first trigger pip as start signal, follow-up trigger pip is as reset signal, and trigger pip sends first and rises or negative edge useful signal, and waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, the output of totalizer compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up; Meanwhile, trigger pip is conduct totalizer reset signal simultaneously also, carrys out a trigger pip, resets one-accumulate device; The output of totalizer is added with waveform start address, produces the reading address of waveform; Trigger pip below all will reset totalizer, make waveform restart to play; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Waveform triggered step, using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then trigger pip is invalid; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Waveform triggers reset process, using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then reset totalizer, waveform is made to restart to play; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Waveform triggers buffer step, using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then trigger pip is until waveform broadcasting terminates effectively rear; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Sequence triggered step, receives after triggering, plays waveform once, again triggers and plays next waveform; Using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, sequence address totalizer adds 1, reads start address and the waveform length of next waveform inside sequence memory, until the next effectively enable totalizer of trigger pip; The output of totalizer is added with waveform start address, produces the reading address of waveform; Effectively occur in waveform when playing if triggered, then trigger pip is invalid and ignore waveform broadcasting time; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Sequence triggers repetition step, receives after triggering, and plays waveform until again trigger next waveform of broadcasting; Using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, the output of totalizer compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up; After again triggering, sequence totalizer adds 1, reads start address and the waveform length of next waveform inside sequence memory; The output of totalizer is added with waveform start address, produces the reading address of waveform; Effectively occur in waveform when playing if triggered, then trigger pip until current form play terminate rear effectively and ignore waveform broadcasting time; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Sequence triggers setting steps, receives after triggering, stops after playing waveform predetermined number of times, with waveform under wait again triggers and plays; Using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up, waveform number of times totalizer adds 1 simultaneously; The value of waveform number of times totalizer compares with waveform number of times, if number of times totalizer equals waveform number of times, then forbids that waveform address totalizer adds up; After again triggering, sequence totalizer adds 1, reads the start address of next waveform inside sequence memory, waveform length and broadcasting time; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then trigger pip is until current form broadcasting terminates effectively rear; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Complex wave synthesis step wherein, sends the reading address that above-mentioned selected a certain step produces waveform into address counter, length counter and repeat counter; When waveform multiplicity is greater than 1, after a wave form output, the parameter of address counter and length counter reloads, at the end of a wave form output, waveform end signal causes sequence address generator to point to the address of next waveform, makes functional nucleotide sequence produce next waveform, after memory address is complete, repeat above process again, make output waveform continuous, by functional nucleotide sequence, comparatively simple Waveform composition is produced the waveform of relative complex.
This system adopts FPGA kernel MIG(Memory control module in Fig. 1, Fig. 2) carry out the exchange of internal storage data, utilize exchanges data between pci bus and MIG, data can be read to memory bar from hard disk, also the exchanges data between MIG and FIFO can be adopted, export data from memory bar and carry out parallel serial conversion to 14 bit data, finally export digital to analog converter to, obtain simulating signal.Also utilize different triggering method and the variable sampling rate shown in composition graphs 3 generation of complicated the multi-system signal can be realized.
The relevant technologies content do not addressed in aforesaid way is taked or uses for reference prior art to realize.
It should be noted that, under the instruction of this instructions, those skilled in the art can also make such or such easy variation pattern, such as equivalent way, or obvious mode of texturing.Above-mentioned variation pattern all should within protection scope of the present invention.
Claims (4)
1., based on a random waveform generation systems for the Wave data variable bit rate playback of complex combination triggering, it is characterized in that comprising:
Wave data access unit, for the control of the buffering and memory interface that complete Wave data; FPGA will be sent into from PCI chip local bus data 32, after the address bus that pci interface module converts becomes 256 bit data bus and 25, write data FIFO and address FIFO in FPGA inside respectively; The Wave data of the Clockreading write inputted with internal memory control module at the opposite side of FIFO and address, send into Memory control module after handshake; Memory control module by the Wave data of input and address according to the sequential write memory bar of memory bar; In read mode, read address feeding Memory control module by reading address generating module generation, the Wave data read from memory bar is sent on output data bus by Memory control module after time delay, exports data_valid signal simultaneously; The data write FIFO that Read_FIFO will read from memory bar; At the opposite side of Read_FIFO, FPGA reads FIFO with 1/16 of DA clock, and 256 bit data read are sent into parallel serial conversion module, and the data feeding DA converting 16 to carries out digital-to-analog conversion; Continuous print read and write is converted to step read-write by a large amount of FIFO in FPGA inside;
Based on waveform compilation and the triggering playback unit of triggering mode, by inner editing machine, or by interface GPIB or USB, by outer computer, waveform expression formula being transformed to Wave data is stored in wave memorizer, control the address that address generator changes wave memorizer, export corresponding Wave data, until the end of waveform segment; Waveform is represented in the mode of text, by amendment text in order to reach the object exporting different wave signal by outer computer.
2. the random waveform generation systems of a kind of Wave data variable bit rate playback based on complex combination triggering according to claim 1, it is characterized in that: the above-mentioned waveform compilation based on triggering mode comprises reading address generating subunit and the complex wave synthon unit of waveform with triggering playback unit, the reading address generating subunit of waveform wherein comprises:
Pulse gating module, using trigger pip as gate-control signal, when trigger pip is effective, plays waveform; Trigger useful signal directly as the enable signal of waveform address totalizer, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, then resets totalizer, makes totalizer restart to add up; Meanwhile, the input of totalizer is added with waveform start address, produces the reading address of waveform;
Trigger module, using trigger pip as a start signal, trigger pip sends rising or negative edge useful signal, waveform address totalizer starts to add up, and carry out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up; Meanwhile, the input of totalizer is added with waveform start address, produces the reading address of waveform; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Trigger reseting module, using first trigger pip as start signal, follow-up trigger pip is as reset signal, and trigger pip sends first and rises or negative edge useful signal, and waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, the output of totalizer compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up; Meanwhile, trigger pip, also as totalizer reset signal, carrys out a trigger pip, resets one-accumulate device; The output of totalizer is added with waveform start address, produces the reading address of waveform; Trigger pip below all will reset totalizer, make waveform restart to play; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Waveform trigger module, using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then trigger pip is invalid; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Waveform triggers reseting module, using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then reset totalizer, waveform is made to restart to play; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Waveform triggers buffer module, using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then trigger pip is until waveform broadcasting terminates effectively rear; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Sequence trigger module, receives after triggering, plays waveform once, again triggers and plays next waveform; Using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, sequence address totalizer adds 1, reads start address and the waveform length of next waveform inside sequence memory, until the next effectively enable totalizer of trigger pip; The output of totalizer is added with waveform start address, produces the reading address of waveform; Effectively occur in waveform when playing if triggered, then trigger pip is invalid and ignore waveform broadcasting time; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Sequence triggers replicated blocks, receives after triggering, and plays waveform until next waveform is play in triggering again; Using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, the output of totalizer compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up; After again triggering, sequence totalizer adds 1, reads start address and the waveform length of next waveform inside sequence memory; The output of totalizer is added with waveform start address, produces the reading address of waveform; Effectively occur in waveform when playing if triggered, then trigger pip until current form play terminate rear effectively and ignore waveform broadcasting time; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Sequence triggers and arranges module, receives after triggering, stops after playing waveform predetermined number of times, waits for again triggering and plays next waveform; Using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up, waveform number of times totalizer adds 1 simultaneously; The value of waveform number of times totalizer compares with waveform number of times, if number of times totalizer equals waveform number of times, then forbids that waveform address totalizer adds up; After again triggering, sequence totalizer adds 1, reads the start address of next waveform inside sequence memory, waveform length and broadcasting time; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then trigger pip is until current form broadcasting terminates effectively rear; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Complex wave synthon unit wherein, sends the reading address that above-mentioned a certain module produces waveform into address counter, length counter and repeat counter; When waveform multiplicity is greater than 1, after a wave form output, the parameter of address counter and length counter reloads, at the end of a wave form output, waveform end signal causes sequence address generator to point to the address of next waveform, makes functional nucleotide sequence produce next waveform, after memory address is complete, repeat this process again, make output waveform continuous, by functional nucleotide sequence, comparatively simple Waveform composition is produced the waveform of relative complex.
3., based on a random waveform method for generation for the Wave data variable bit rate playback of complex combination triggering, it is characterized in that comprising the following steps:
Wave data access step, for the control of the buffering and memory interface that complete Wave data; FPGA will be sent into from PCI chip local bus data 32, after the address bus that pci interface module converts becomes 256 bit data bus and 25, write data FIFO and address FIFO in FPGA inside respectively; The Wave data of the Clockreading write inputted with internal memory control module at the opposite side of FIFO and address, send into Memory control module after handshake; Memory control module by the Wave data of input and address according to the sequential write memory bar of memory bar; In read mode, read address feeding Memory control module by reading address generating module generation, the Wave data read from memory bar is sent on output data bus by Memory control module after time delay, exports data_valid signal simultaneously; The data write FIFO that Read_FIFO will read from memory bar; At the opposite side of Read_FIFO, FPGA reads FIFO with 1/16 of DA clock, and 256 bit data read are sent into parallel serial conversion module, and the data feeding DA converting 16 to carries out digital-to-analog conversion; Continuous print read and write is converted to step read-write by a large amount of FIFO in FPGA inside;
Based on waveform compilation and the triggering replay procedure of triggering mode, by inner editing machine, or by interface GPIB or USB, by outer computer, waveform expression formula being transformed to Wave data is stored in wave memorizer, control the address that address generator changes wave memorizer, export corresponding Wave data, until the end of waveform segment; Waveform is represented in the mode of text, by amendment text in order to reach the object exporting different wave signal by outer computer.
4. the random waveform method for generation of a kind of Wave data variable bit rate playback based on complex combination triggering according to claim 3, it is characterized in that: the above-mentioned waveform compilation based on triggering mode comprises reading address generation step and the complex wave synthesis step of waveform with triggering replay procedure, the reading address generation step of waveform wherein comprises a certain step in the listed step of below selective gist:
Pulse gate step, using trigger pip as gate-control signal, when trigger pip is effective, plays waveform; Trigger useful signal directly as the enable signal of waveform address totalizer, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, then resets totalizer, makes totalizer restart to add up; Meanwhile, the input of totalizer is added with waveform start address, produces the reading address of waveform;
Triggered step, using trigger pip as a start signal, trigger pip sends rising or negative edge useful signal, waveform address totalizer starts to add up, and carry out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up; Meanwhile, the input of totalizer is added with waveform start address, produces the reading address of waveform; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Trigger reset process, using first trigger pip as start signal, follow-up trigger pip is as reset signal, and trigger pip sends first and rises or negative edge useful signal, and waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, the output of totalizer compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up; Meanwhile, trigger pip, also as totalizer reset signal, carrys out a trigger pip, resets one-accumulate device; The output of totalizer is added with waveform start address, produces the reading address of waveform; Trigger pip below all will reset totalizer, make waveform restart to play; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Waveform triggered step, using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then trigger pip is invalid; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Waveform triggers reset process, using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then reset totalizer, waveform is made to restart to play; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Waveform triggers buffer step, using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, until the next effectively enable totalizer of trigger pip simultaneously; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then trigger pip is until waveform broadcasting terminates effectively rear; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Sequence triggered step, receives after triggering, plays waveform once, again triggers and plays next waveform; Using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, and waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer, compared with waveform length, if equal waveform length, then resets totalizer, forbid that totalizer adds up, sequence address totalizer adds 1, reads start address and the waveform length of next waveform inside sequence memory, until the next effectively enable totalizer of trigger pip; The output of totalizer is added with waveform start address, produces the reading address of waveform; Effectively occur in waveform when playing if triggered, then trigger pip is invalid and ignore waveform broadcasting time; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Sequence triggers repetition step, receives after triggering, and plays waveform until again trigger next waveform of broadcasting; Using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, the output of totalizer compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up; After again triggering, sequence totalizer adds 1, reads start address and the waveform length of next waveform inside sequence memory; The output of totalizer is added with waveform start address, produces the reading address of waveform; Effectively occur in waveform when playing if triggered, then trigger pip until current form play terminate rear effectively and ignore waveform broadcasting time; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Sequence triggers setting steps, receives after triggering, stops after playing waveform predetermined number of times, waits for again triggering and plays next waveform; Using trigger pip as start signal, trigger pip sends rising or negative edge useful signal, waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, then reset totalizer, make totalizer restart to add up, waveform number of times totalizer adds 1 simultaneously; The value of waveform number of times totalizer compares with waveform number of times, if number of times totalizer equals waveform number of times, then forbids that waveform address totalizer adds up; After again triggering, sequence totalizer adds 1, reads the start address of next waveform inside sequence memory, waveform length and broadcasting time; The output of totalizer is added with waveform start address, produces the reading address of waveform; If when triggering effectively occurs in waveform broadcasting, then trigger pip is until current form broadcasting terminates effectively rear; The trigger pip of outside input acts on waveform totalizer after edge sense circuit;
Complex wave synthesis step wherein, sends the reading address that above-mentioned selected a certain step produces waveform into address counter, length counter and repeat counter; When waveform multiplicity is greater than 1, after a wave form output, the parameter of address counter and length counter reloads, at the end of a wave form output, waveform end signal causes sequence address generator to point to the address of next waveform, makes functional nucleotide sequence produce next waveform, after memory address is complete, repeat this process again, make output waveform continuous, by functional nucleotide sequence, comparatively simple Waveform composition is produced the waveform of relative complex.
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| CN101907881A (en) * | 2010-06-04 | 2010-12-08 | 西安电子科技大学 | Programmable digital pulse generator |
| CN102109875A (en) * | 2009-12-28 | 2011-06-29 | 北京普源精电科技有限公司 | Signal generator with pulse signal generation function, and method for generating pulse signal |
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| JP3417507B2 (en) * | 1995-05-31 | 2003-06-16 | 株式会社アドバンテスト | Arbitrary waveform generator for DUT test |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101017383A (en) * | 2006-11-01 | 2007-08-15 | 王文华 | High speed arbitrary waveform generator based on FPGA |
| CN102109875A (en) * | 2009-12-28 | 2011-06-29 | 北京普源精电科技有限公司 | Signal generator with pulse signal generation function, and method for generating pulse signal |
| CN101907881A (en) * | 2010-06-04 | 2010-12-08 | 西安电子科技大学 | Programmable digital pulse generator |
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