CN103178871A - Frequency hopping signal generator and method for determining frequency control words - Google Patents
Frequency hopping signal generator and method for determining frequency control words Download PDFInfo
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Abstract
The invention discloses a frequency hopping signal generator and a method for determining frequency control words. The frequency hopping signal generator comprises a memory for storing a frequency control word list, a frequency hopping sequence generator and a memory controller. The frequency hopping sequence generator is used for generating sequences and determining a frequency hopping sequence mode, and one sequence is selected from the generated sequences as a read address of the memory according to the frequency hopping sequence mode and sent to the memory controller. The memory controller is used for taking the frequency control works out of the memory according to the read address sent by the frequency hopping sequence generator. The method for determining frequency control words includes: generating the sequences, and determining the frequency hopping sequence mode; selecting one sequence from the generated sequences as the read address of the memory according to the frequency hopping sequence mode; and taking the frequency control words out of the memory according to the read address. The frequency hopping signal generator and the method for determining frequency control words have the advantages of being good in randomness, long in frequency hopping period, simple in circuit and the like.
Description
Technical field
The present invention relates to the Frequency-hopping Communication Technology field, relate in particular to a kind of Frequency Hopping Signal generator and determine the method for frequency control word.
Background technology
The outstanding advantages of frequency hopping communications is strong interference immunity, and its jamproof mechanism is constantly to change carrier frequency to carry out the communication that receiving-transmitting sides is made an appointment in frequency domain.The rule that in frequency hopping communications, carrier frequency changes is called frequency hopping pattern; Frequency hopping pattern is the function of time and frequency.Fig. 1 is the schematic diagram of a frequency hopping pattern, and the transverse axis in Fig. 1 is that time, the longitudinal axis are frequency, and as shown in Figure 1, it shows when adopt what frequency to communicate.
The performance of frequency hopping pattern has conclusive impact to the performance of frequency-hopping communication system, directly have influence on the networking capability of the anti-intercepting and capturing of system, anti-interference, net synchronization capability and system, if frequency hopping pattern designs badly, even the hardware circuit design of frequency-hopping communication system gets very outstanding, also be difficult to reach jamproof purpose.
In frequency-hopping system, be called frequency hopper for generation of the device of the carrier wave of frequency change, frequency hopper is made of two parts: FH Sequence Generator and frequency synthesizer.FH Sequence Generator produces the good frequency hop sequences of pseudo-randomness, namely frequency hopping pattern; Frequency synthesizer is good according to frequency hopping pattern generation spectral purity, carrier wave that frequency is switched fast.
In the prior art, modelled signal generator and carry out frequency hopping and process in the following way:
Adopt programmable logic array FPGA (Field Programmable Gate Array, field programmable gate array) and DDS (Direct Digital Synthesizer, Direct Digital Synthesizer) technology, realized a kind of Frequency Hopping Signal generator, it adopts the hardware structure of processor+FPGA, and operation principle is as follows:
Digital signal processor DSP (Digital Signal Processing, Digital Signal Processing) configures the frequency parameter that the user arranges to FPGA; DDR2DRAM (DDR2:Double Data Rate 2, Double Data Rate 2 are left in frequency hopping frequency control word list used in advance in; DRAM:Dynamic Random Access Memory, dynamic random access memory) in; FPGA realizes inside the DDS function, by storage control module access DDR2DRAM, takes out frequency control word by getting the point control module, and by the waveform of DDS according to frequency control word output corresponding frequencies; DAC (Digital Analog Converter, digital to analog converter) completes digital-to-analogue conversion; The carrier wave of output frequency saltus step after processing through filtering, amplitude amplification, decay, skew etc. subsequently.
The frequency hopping pattern mechanism of production of this scheme is: DSP generates the frequency control word list that frequency hopping pattern comprises in advance, and leaves in DDR2 DRAM by FPGA; After frequency hopping begins, the taking-up frequency control word of FPGA order from DDR2 DRAM, and give inner DDS module, thus produce the waveform of frequency change.Fig. 2 is that the schematic diagram of point control module is got in FPGA inside, and as shown in Figure 2, FPGA gets inside the point control module and comprises three counters, and counter A is used for controlling the address from DRAM reading frequency control word; Counter B is used for controlling the speed of reading frequency control word; Counter C is used for the operating speed of control frequency control word, i.e. frequency hopping rate.Also comprise a FIFO (First In First Out, first in first out), be used for the buffer memory frequency control word.
Usually, in the prior art, think a good frequency hopping pattern generally can consider following some:
1, the randomness of frequency hopping pattern itself will be got well.Randomness is good, and antijamming capability is strong.
2, the size of key of frequency hopping pattern wants large, requires the number of frequency hopping pattern abundant.The ability of anti-like this decoding is strong.
3, the requirement of the complexity of frequency hopping pattern is high as far as possible, hop period is long, makes like this interference side be difficult to recover integral body fully from a very little part of sequence.
4, for more frequency hopping pattern being arranged for the user, require the sequence pattern in the frequency hop sequences set many as far as possible.
Contrast above-mentioned factor, the inventor notices: the scheme of prior art be with DSP in advance with frequency control word according to certain Format Series Lines layout one-tenth table, and store in DRAM; Then give DDS by taking out of FPGA order from DRAM.Therefore, there is following deficiency in the producing method of this frequency hopping pattern:
1, hop period is short.Hop period is frequency hopping length in other words, refers to the time of frequency control word list output one time.Because a little mode is sequentially got in the FPGA employing, cause hop period short.In fact, suppose that DRAM has stored 10,000,000 frequency control words for example, the speed frequency hopping of then jumping with per second common in short wave frequency-hopping radio 100, hop period is about 1.15 days, and so short hop period is breakneck in military communication.
2, in order to increase hop period, for this scheme, can only use larger capacity, more granose DRAM, to deposit more frequency control word.Can significantly increase system cost, design complexities like this, effect is also very limited.
Although 3 DSP can carry out layout according to m sequence, M sequence or other sequence pattern to frequency control word, form the frequency control word list with pseudo-randomness, but because hop period is short, the original pseudo-randomness that has of these frequency hop sequences has also lost meaning.
If 4 customer requirements change frequency hop sequences patterns, DSP need to all frequency control words layout again, cause the software burden large; And the communication bandwidth between DSP and FPGA is usually not high, needs to expend the long time in DRAM for the FREQUENCY CONTROL word table after layout is written to by FPGA.Therefore, system response time is slow.
Summary of the invention
Provide a kind of method of Frequency Hopping Signal generator and definite frequency control word in the embodiment of the present invention, the randomness that produces in order to improve frequency hopping pattern.
The embodiment of the present invention provides a kind of Frequency Hopping Signal generator, comprising:
Memory is used for the list of storing frequencies control word;
The frequency hop sequences generator, for generation of sequence and determine the frequency hop sequences pattern, choose from the sequence that produces according to the frequency hop sequences pattern a kind of sequence as memory read the address after, be sent to Memory Controller;
Memory Controller is used for taking out frequency control word according to the address of reading that the frequency hop sequences generator is delivered to from memory.
Preferably, can further include:
The frequency hopping rate control module is used for producing frequency by counter and switches enable signal in order to control the speed of frequency hop sequences generator generation sequence.
Preferably, the frequency hopping rate control module can also be further used for when producing frequency switching enable signal, switches enable signal according to the frequency hopping rate control word generation frequency of configuration.
Preferably, the frequency hop sequences generator can also be further used for when definite frequency hop sequences pattern, and described frequency hop sequences pattern configures by processor, and when producing sequence, the exponent number of the sequence of generation is higher than the address bit wide of memory.
Preferably, the frequency hop sequences generator can also be further used for when definite frequency hop sequences pattern, and described frequency hop sequences pattern configures by processor, and described frequency hop sequences pattern comprises pseudo random sequence pattern and/or generic sequence pattern.
The embodiment of the present invention also provides a kind of definite frequency control word method, comprises the steps:
Produce sequence and determine the frequency hop sequences pattern;
Choose a kind of sequence as the address of reading of memory according to the frequency hop sequences pattern from the sequence that produces;
Take out frequency control word according to reading the address from memory.
Preferably, can further include:
Produce frequency by counter and switch enable signal in order to control the speed that produces sequence.
Preferably, when producing frequency switching enable signal, can also produce frequency according to the frequency hopping rate control word of configuration and switch enable signal.
Preferably, the exponent number of the sequence of generation can be higher than the address bit wide of memory.
Preferably, described frequency hop sequences pattern can comprise pseudo random sequence pattern and/or generic sequence pattern.
The method of a kind of Frequency Hopping Signal generator that provides in the embodiment of the present invention and definite frequency control word has the characteristics such as randomness is good, hop period is long, circuit is simple.
Description of drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or description of the Prior Art, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.In the accompanying drawings:
Fig. 1 is the schematic diagram of a frequency hopping pattern in background technology;
Fig. 2 is the schematic diagram that in background technology, FPGA gets inside the point control module;
Fig. 3 is the structural representation of Frequency Hopping Signal generator in the embodiment of the present invention;
Fig. 4 is hardware configuration and the FPGA internal module schematic diagram of Frequency Hopping Signal generator in the embodiment of the present invention;
Fig. 5 determines frequency control word method implementing procedure schematic diagram in the embodiment of the present invention;
Fig. 6 is the implementing procedure schematic diagram that in the embodiment of the present invention, FPGA and processor produce Frequency Hopping Signal;
Fig. 7 is frequency hop sequences generator interior sash schematic diagram in the embodiment of the present invention;
Fig. 8 is 60 rank m sequence generation principle schematic in the embodiment of the present invention.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the present invention is clearer, below in conjunction with accompanying drawing, the embodiment of the present invention is described in further details.At this, illustrative examples of the present invention and explanation thereof are used for explanation the present invention, but not as a limitation of the invention.
In the embodiment of the present invention, still adopt the structure of FPGA+ processor, but the producing method of frequency hopping pattern is fully different from the frequency hopping pattern producing method of Fig. 2, this species diversity is embodied in two aspects, the one, FPGA inner function module is different, and the 2nd, corresponding processor processing mode is also different.The design that the embodiment of the present invention produces Frequency Hopping Signal is: processor is stored in DRAM with the frequency control word list that the user arranges by FPGA, then take out frequency control word by FPGA according to certain frequency hop sequences pattern from DRAM, and exported the Frequency Hopping Signal of corresponding frequencies by the DDS module.The below specifically describes in detail.
Fig. 3 is the structural representation of Frequency Hopping Signal generator in the embodiment of the present invention, as shown in Figure 3, can comprise in the Frequency Hopping Signal generator:
Frequency hop sequences generator 315, for generation of sequence and determine the frequency hop sequences pattern, choose from the sequence that produces according to the frequency hop sequences pattern a kind of sequence as memory read the address after, be sent to Memory Controller;
Memory Controller 313 is used for taking out frequency control word according to the address of reading that the frequency hop sequences generator is delivered to from memory.
In enforcement, can further include in the Frequency Hopping Signal generator:
Frequency hopping rate control module 314 is used for producing frequency by counter and switches enable signal in order to control the speed of frequency hop sequences generator generation sequence.
In enforcement, the frequency hopping rate control module can be further used for when producing frequency switching enable signal, switches enable signal according to the frequency hopping rate control word generation frequency of configuration.
In enforcement, the frequency hop sequences generator can be further used for when definite frequency hop sequences pattern, and described frequency hop sequences pattern configures by processor, and when producing sequence, the exponent number of the sequence of generation is higher than the address bit wide of memory.
In enforcement, the frequency hop sequences generator can be further used for when definite frequency hop sequences pattern, and described frequency hop sequences pattern configures by processor, and described frequency hop sequences pattern comprises: pseudo random sequence pattern and/or generic sequence pattern.
The below is elaborated with example.
Fig. 4 is hardware configuration and the FPGA internal module schematic diagram of Frequency Hopping Signal generator, and at the Frequency Hopping Signal generator, FPGA is the core apparatus that produces Frequency Hopping Signal, and as shown in Figure 4, functions can be as follows:
Processor and ancillary equipment 301, can comprise the processor (concrete enforcement can be adopted DSP or other general processor) of controlling for system, the memory that is used for auxiliary processor work, be used for connecting LAN (the Local Area Network of host computer or network, LAN), GPIB (General-Purpose Interface Bus, general-purpose interface bus), USB (Universal Serial BUS, USB) bus interface module such as is used for the display screen of man-machine interaction and keyboard etc.; These system control equipments have versatility, are to those skilled in the art easily to understand, so do not draw one by one in Fig. 4;
Clock source 303 is used to whole device that high-precision stabilizing clock is provided, and in enforcement, the clock source frequency in thermometrically equipment can be selected 10MHz by common setting;
Fpga chip 304, the core apparatus of Frequency Hopping Signal output is used for the frequency control word list of processor configuration is deposited into DRAM memory; Produce the Frequency Hopping Signal of frequency change according to frequency hopping pattern;
DAC chip 305, analog-digital chip, the Wave data that is used for number format that FPGA is sent is converted to analog quantity, then output after processing through analog channel;
Analog channel 306 is used for the analog quantity of DAC output is for further processing, and comprises filtering, decay, amplification etc.
The below is elaborated to the enforcement of FPGA internal work.
As can be seen from Figure 4, FPGA inside can be divided into 6 functional modules, and each functions of modules can be as follows:
Communication interface modules 311 is used for realizing communicating by letter between fpga chip and processor, and the instruction that processor is sent is transmitted to inner other module of FPGA.
Clock module 312, the reference clock that is used for clock source is provided carries out frequency synthesis, for inner other module provides work clock.
Frequency hopping rate control module 314 adopts counter to realize, is used for switching enable signal 333 to frequency hop sequences generator 315 according to the frequency hopping rate control word 322 generation frequencies of processor configuration; It is the effective pulses of high level that frequency is switched enable signal 333, and its cycle has represented frequency hopping speed;
Frequency hop sequences generator 315 is used for switching enable signal 333 with frequency and produces various sequences, according to the frequency hop sequences mode 3 23 of processor configuration, selects a kind of sequence to give Memory Controller from the sequence that produces, as the address of reading of DRAM memory 302.In enforcement, frequency hop sequences adopts pseudo random sequence to realize, has pseudorandom characteristic; The frequency control word that takes out from the frequency control word list is also that pseudorandom changes, and therefore, the frequency hopping pattern that produces based on the embodiment of the present invention is pseudorandom.
DDS module 316 is used for producing the waveform of corresponding frequencies and exporting to DAC chip 305 according to frequency control word.In concrete enforcement, DDS module 316 is made of phase accumulator and wave memorizer.In the embodiment of the present invention, FPGA adopts accumulator and embedded memory to realize respectively these two, thereby realizes the DDS function.Phase accumulator is cumulative according to frequency control word, determines the frequency of output waveform; Wave memorizer can be by the waveform sampling point 324 of the pre-configured one-period of processor, then reads the address output waveform according to what phase accumulator produced.
Based on same inventive concept, a kind of method of definite frequency control word also is provided in the embodiment of the present invention, the below is elaborated.
Fig. 5 as shown in the figure, can comprise the steps: for determining frequency control word method implementing procedure schematic diagram
Step 502, choose a kind of sequence as the address of reading of memory according to the frequency hop sequences pattern from the sequence that produces;
In enforcement, can further include:
Produce frequency by counter and switch enable signal in order to control the speed that produces sequence.
In enforcement, when producing frequency switching enable signal, can produce frequency according to the frequency hopping rate control word of configuration and switch enable signal.
In enforcement, the exponent number of the sequence of generation can be higher than the address bit wide of memory.
In enforcement, the frequency hop sequences pattern can comprise: pseudo random sequence pattern and/or generic sequence pattern.
the below describes with the example that is produced as of the Frequency Hopping Signal generator in Fig. 4 to Frequency Hopping Signal, need to prove, the present embodiment is only to understand how to implement the present invention for the ease of those skilled in the art, but the generation that does not mean that Frequency Hopping Signal can only be produced by the Frequency Hopping Signal generator in Fig. 4, in fact, can be known by the present invention's design, as long as can choose a kind of sequence as the address of reading of memory from the sequence that produces according to the frequency hop sequences pattern, and then all can implement the generation of Frequency Hopping Signal according to this device components of reading to take out frequency control word in the address from memory, in like manner, switch the generation of enable signal, the processing of DDS etc. for frequency, can select the device components that can realize corresponding function too, and to be not limited only to be only that frequency hopping speed control, DDS etc. in the Frequency Hopping Signal generator of Fig. 4 can be realized, this is easily to understand to those skilled in the art.
Fig. 6 is the implementing procedure schematic diagram that FPGA and processor produce Frequency Hopping Signal, as shown in the figure, can comprise the steps:
After step 604, above parameter, waveform, list configuration are completed, can begin to export Frequency Hopping Signal;
The frequency hopping speed control of step 605, FPGA inside is controlled and is produced frequency and switch enable signal; Switch enable signal with this frequency and produce various frequency hop sequences, and therefrom take out one as the address of reading of DRAM;
The below is elaborated to concrete execution mode again.
In the invention process, the performance of frequency hopping pattern is mainly the character that depends on pseudo-code.So select pseudo-code sequence to become the key that obtains frequency hopping pattern well.For more frequency hopping pattern being arranged for the user, just need the sequence pattern in the frequency hop sequences set many as far as possible.Can support the pseudo random sequence patterns such as m sequence, M sequence, RS sequence in the embodiment of the present invention; For debug conveniently or some teaching on application, can also support the generic sequence pattern, namely according to the frequency control word that takes out in turn of frequency control word list.
Fig. 7 is frequency hop sequences generator interior sash schematic diagram, as shown in Figure 7, in the frequency hop sequences generator internal structure of the embodiment of the present invention, can be under frequency be switched the control of enable signal, the shift register and the feedback logic that utilize multistage trigger to consist of just can realize respectively m sequence, M sequence, RS sequence.
Fig. 8 is 60 rank m sequence generation principle schematic, the generation principle of explanation m sequence as an example of 60 rank m sequences example.The primitive polynomial of the m sequence on 60 rank is: x
60+ x
59+ 1.Therefore the result of the 60th, 59 trigger of 60 rank shift registers is done to feed back to the 1st grade after mould 2 adds, can realize 60 rank m sequences.
In order to produce enough cycles of macrocyclic pseudo random sequence, the exponent number of sequence can higher than the address bit wide of DRAM, therefore can carry out cut position with the high position of sequence according to the address bit wide of DRAM.Use a counter to produce under ordered mode and read the address, the bit wide of counter equals the address bit wide of DRAM, does not therefore need cut position.
Can also expand in the invention process and use other pseudo random sequence pattern, such as Bent sequence, GMW sequence etc.Adopting FPGA to produce these sequences is to be relatively easy to, in this not explanation one by one.
According to the frequency hop sequences pattern of processor configuration, select one the sequence after cut position, get final product as the address of reading of DRAM.
As seen from the above-described embodiment, by the technical scheme that the embodiment of the present invention provides, the frequency control word list configuration that processor only needs the user is arranged is to DRAM, even after this user revises the frequency hop sequences pattern, processor also need not to regenerate the frequency control word list.Can greatly alleviate the burden of software like this, improve system response time.
Simultaneously, frequency hop sequences is to make hop period very long by the inner benefit that produces of FPGA.Take 60 rank m sequences as example, even frequency hopping speed is per second 10,000 jumpings, hop period still can be up to 100,000 years.Hop period considerably beyond 10 years length of general frequency-hopping communication system.Because frequency hop sequences is produced by FPGA, by the technical scheme that the embodiment of the present invention provides, do not need to extend hop period by the number of increase frequency control word and the capacity of DRAM.
In the technical scheme that the embodiment of the present invention provides, the frequency hop sequences pattern can be very abundant, can support m sequence, M sequence, RS sequence, also can expand to easily other pseudo random sequence pattern, can also keep in addition the mode of generic sequence.And for same frequency control word list, adopt different frequency hop sequences patterns, just can produce different frequency hopping patterns.
The randomness of frequency hopping pattern itself is larger, and antijamming capability is also stronger.In the technical scheme that the embodiment of the present invention provides, due to the use to various pseudo random sequences, make based on frequency hopping pattern of the present invention to have good pseudo-randomness.
In the technical scheme that the embodiment of the present invention provides, adopt DDS as frequency synthesizer, make the Frequency Hopping Signal generator have the advantages that frequency hopping speed is fast, the frequency hopping band is wide, frequency resolution is high.
In the technical scheme that the embodiment of the present invention provides, due to the framework that has adopted processor and FPGA, have the characteristics such as integrated degree is high, volume is little, debugging is simple.
In a word, the technical scheme that the embodiment of the present invention provides not only can be applicable to the Frequency Hopping Signal generator in thermometrically field, is also a useful reference for frequency-hopping communication system.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above is only specific embodiments of the invention; the protection range that is not intended to limit the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. a Frequency Hopping Signal generator, is characterized in that, comprising:
Memory is used for the list of storing frequencies control word;
The frequency hop sequences generator, for generation of sequence and determine the frequency hop sequences pattern, choose from the sequence that produces according to the frequency hop sequences pattern a kind of sequence as memory read the address after, be sent to Memory Controller;
Memory Controller is used for taking out frequency control word according to the address of reading that the frequency hop sequences generator is delivered to from memory.
2. Frequency Hopping Signal generator as claimed in claim 1, is characterized in that, further comprises:
The frequency hopping rate control module is used for producing frequency by counter and switches enable signal in order to control the speed of frequency hop sequences generator generation sequence.
3. Frequency Hopping Signal generator as claimed in claim 2, is characterized in that, the frequency hopping rate control module is further used for when producing frequency switching enable signal, switches enable signal according to the frequency hopping rate control word generation frequency of configuration.
4. Frequency Hopping Signal generator as described in the claims 1 to 3 any one, it is characterized in that, the frequency hop sequences generator is further used for when definite frequency hop sequences pattern, described frequency hop sequences pattern configures by processor, when producing sequence, the exponent number of the sequence of generation is higher than the address bit wide of memory.
5. Frequency Hopping Signal generator as described in the claims 1 to 3 any one, it is characterized in that, the frequency hop sequences generator is further used for when definite frequency hop sequences pattern, described frequency hop sequences pattern configures by processor, and described frequency hop sequences pattern comprises pseudo random sequence pattern and/or generic sequence pattern.
6. the method for a definite frequency control word, is characterized in that, comprises the steps:
Produce sequence and determine the frequency hop sequences pattern;
Choose a kind of sequence as the address of reading of memory according to the frequency hop sequences pattern from the sequence that produces;
Take out frequency control word according to reading the address from memory.
7. method as claimed in claim 6, is characterized in that, further comprises:
Produce frequency by counter and switch enable signal in order to control the speed that produces sequence.
8. method as claimed in claim 7, is characterized in that, when producing frequency switching enable signal, switches enable signal according to the frequency hopping rate control word generation frequency of configuration.
9. method as described in claim 6 to 8 any one, is characterized in that, the exponent number of the sequence of generation is higher than the address bit wide of memory.
10. method as described in claim 6 to 8 any one, is characterized in that, described frequency hop sequences pattern comprises pseudo random sequence pattern and/or generic sequence pattern.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106200758A (en) * | 2016-06-23 | 2016-12-07 | 中国人民解放军63888部队 | A kind of Frequency Hopping Communication Signal radio spectrum characteristic simulation produces system and method |
| CN109471077A (en) * | 2018-11-02 | 2019-03-15 | 北京振兴计量测试研究所 | A kind of SAR echo signal generation method of frequency hopping |
| CN109547060A (en) * | 2018-11-22 | 2019-03-29 | 北京睿信丰科技有限公司 | It jumps spread-spectrum signal emitter, jump spread-spectrum signal reception device, frequency hopping spread spectrum (FHSS) communication system and frequency hopping spread spectrum (FHSS) communication method |
| CN112261663A (en) * | 2020-09-30 | 2021-01-22 | 北京智芯微电子科技有限公司 | Same frequency interference suppression method, system and storage medium during multi-station networking |
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| CN1444346A (en) * | 2002-03-11 | 2003-09-24 | 日本电气株式会社 | Frequency hooping communication device with simple structure |
| CN102185634A (en) * | 2011-04-26 | 2011-09-14 | 中国人民解放军理工大学 | Shortwave frequency hopping communication system and communication method thereof |
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| CN1444346A (en) * | 2002-03-11 | 2003-09-24 | 日本电气株式会社 | Frequency hooping communication device with simple structure |
| CN102185634A (en) * | 2011-04-26 | 2011-09-14 | 中国人民解放军理工大学 | Shortwave frequency hopping communication system and communication method thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106200758A (en) * | 2016-06-23 | 2016-12-07 | 中国人民解放军63888部队 | A kind of Frequency Hopping Communication Signal radio spectrum characteristic simulation produces system and method |
| CN109471077A (en) * | 2018-11-02 | 2019-03-15 | 北京振兴计量测试研究所 | A kind of SAR echo signal generation method of frequency hopping |
| CN109471077B (en) * | 2018-11-02 | 2020-12-18 | 北京振兴计量测试研究所 | Frequency hopping SAR echo signal generation method |
| CN109547060A (en) * | 2018-11-22 | 2019-03-29 | 北京睿信丰科技有限公司 | It jumps spread-spectrum signal emitter, jump spread-spectrum signal reception device, frequency hopping spread spectrum (FHSS) communication system and frequency hopping spread spectrum (FHSS) communication method |
| CN109547060B (en) * | 2018-11-22 | 2021-03-19 | 北京睿信丰科技有限公司 | Frequency hopping spread spectrum signal transmitting device, frequency hopping spread spectrum signal receiving device, frequency hopping spread spectrum communication system and frequency hopping spread spectrum communication method |
| CN112261663A (en) * | 2020-09-30 | 2021-01-22 | 北京智芯微电子科技有限公司 | Same frequency interference suppression method, system and storage medium during multi-station networking |
| CN112261663B (en) * | 2020-09-30 | 2023-06-20 | 北京智芯微电子科技有限公司 | Method, system and storage medium for suppressing same-frequency interference during networking of multiple groups |
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| CN103178871B (en) | 2016-06-01 |
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