CN101576619B - UWB radar signal simulator based on FPGA and UWB radar signal generation method - Google Patents

Abstract

The invention relates to a UWB radar signal simulator based on FPGA, comprising a PC104 interface module, an RAM module, an FPGA module and a high-speed DAC module; the PC104 interface module completes data transmission with a host with PC104 mode by a PCI protocol; the RAM module adopts six ZBT-SRAMs with the bit width of 32 as data cache; the FPGA module adopts Virtex-4 series of product XC4VLX40 offered by Xilinx company and comprises a PCI interface control module, a RAM control module, a high-speed DAC control module and a radar waveform control module; the high-speed DAC control module selects AD9736 of ADI company; the interconnection of all the modules is realized by control modules in the FPGA module, the PC104 interface control module completes butting joint of the FPGA module and the PC104 interface module; data generated by controlling a host computer is transmitted to the inner part of the FPGA module from the PC 104 interface module; the RAM control module completes butting joint of the FPGA module and the RAM module so as to realize the transmission of data between the FPGA and the ZBT-SRAM; and the high-speed DAC control module completes butting joint of the FPGA module and the high-speed DAC module and controls the high-speed DAC module to generate various radar waveforms.

Description

UWB radar signal simulator and UWB radar signal production method based on FPGA

(1) technical field

The present invention relates to a kind of UWB (ultra broadband) radar signal simulator based on FPGA (field programmable gate array); Produce various UWB simulating signals through FPGA control high-speed DAC (digital to analog converter); Can be used for information transmission and detections such as communication, radar, belong to areas of information technology.

(2) background technology

According to the nyquist sampling law, UWB signal portability more information, thereby be widely used in fields such as communication, radars.The UWB signal mainly is divided into narrow pulse signal and broad pulse modulating uwb signal.The narrow comparatively difficulty that transmits and receives of the former pulse width.The latter is similar with the conventional modulated signal form, has higher average power, and operating distance is far away, thereby is widely used.For example, the WIMIDEA communication system of the U.S. adopts the broad pulse modulating uwb signal of 500MHz bandwidth; The state-of-the-art GBR of the U.S. (ground radar) adopts broad pulse modulation signal UWB signal equally, and its bandwidth is 1GHz.

Analog-and digital-method all can produce simulating signal.The conventional analogue signal generating method utilizes VCO analog devices such as (voltage controlled oscillators) to accomplish signal and produces.The numeral production method utilizes DAC to convert Serial No. into simulating signal, thereby accomplishes the generation of simulating signal.With analog signal generating method comparatively speaking, digital production method has signal amplitude, phase place is easy to advantages such as control, thereby is used widely.The mode that numeral produces waveform mainly contains: two kinds of Direct Digital synthesis method of the frequency (DDFS) and Direct Digital Waveform synthetic methods (DDWS).

DDFS converts simulating signal to through DAC then through numerical value phase-accumulated, each sampling instant waveform of amplitude computation of table lookup.The work essence of DDFS is with reference clock frequency phase place to be carried out controlled interval calculation, accomplishes the simulation reconstruct of sampled value.

DDWS calculates the each point sampled value in advance according to signal form, deposits in order in the HSM, and the address that produces through sampling clock when producing signal, the sampled value of reading each point successively converts simulating signal to through DAC.DDWS produces the waveform memory address with reference clock frequency, directly reads the simulation reconstruct that Wave data is accomplished sampled value.

From the required device of concrete realization, the both needs high speed device to produce the UWB signal.The general use of DDFS is specifically designed to the DDS device that produces the LFM signal, and the form that produces signal is single, and the frequency that produces signal also can't vary, and is also stronger to the dependence of device.Comparatively speaking, the DDWS method can produce any frequency, any type of waveform, realizes the control of signal parameter is reached the hack to Wave data, conveniently carries out pre-distortion compensated.

The PD of train of impulses form (pulse Doppler) radar can get range-to-go, speed and angle information simultaneously, and therefore most of radar adopts the PD mode of operation.And the PD radar signal is varied, comprising: coherent pulse string, non-coherent pulse string; Pulse internal modulation simple signal, pulse internal modulation LFM (linear frequency modulation) signal, pulse internal modulation phase-coded signal; Pulse repetition time slip, pulse repetition time shake, pulse width slip, pulse width shake etc.

The radar signal that high-precision radar system need produce has high-precision frequency, phase place, range stability, the fast and flexible property when needing signal transformation simultaneously.

(3) summary of the invention

The object of the present invention is to provide a kind of UWB radar signal simulator and UWB radar signal production method, need to solve signal parameter stability, reach problems such as the quick switching of waveform with the generation of solution UWB radar signal based on FPGA.

The UWB radar signal production method based on FPGA that the present invention proposes adopts the Direct Digital Waveform synthetic method; Promptly at first calculate the each point sampled value in advance according to radar signal form to be produced; Deposit in the HSM in order; The address that produces through sampling clock afterwards, the sampled value of reading each point successively converts simulating signal to through DAC.

The UWB radar signal production method that the present invention proposes is on the hardware system based on the FPGA structure, to realize; A kind of UWB radar signal simulator based on FPGA of this system mainly comprises: PC104 (PCI) interface module, RAM module, FPGA module and high-speed DAC module etc. are partly formed.

PC104 (PCI) interface module: the present invention provides the HPI of a PC104 (PCI), accomplishes with the main frame of PC104 form and accomplishes data transmission through the PCI agreement.The PC104 interface module adopts the PCI9054 chip, and PCI9054 is one 32 33M bus master I/O accelerators, supports the PCI2.2 standard fully, reaches as high as the burst speed of 132MB/s.PCI9054 has adopted the advanced data pipeline framework (Data pipe architecture) of PLX company, supports three kinds of operator schemes, the M pattern; The C pattern; The J pattern, wherein the J pattern is the data line and the address wire multiplexer mode of local bus, also is the pattern that is adopted during this paper designs.

The RAM module: the present invention adopts the ZBT-SRAM of 6 32 bit wides as metadata cache, realizes total line use ratio of 100%, and maximum operation frequency is 200MHz.One group of per 3 storer, by two independently controller controls, two groups of work of both can having rattled also can be worked simultaneously.The maximum data bandwidth of each controller is 12*1600Mbps, can satisfy the data rate request of current most of sampling rate DAC.

FPGA module: the Virtex-4 series of products XC4VLX40 that FPGA of the present invention adopts Xilinx company to release.This FPGA inside has rich in natural resources, comprises the distributed RAM of 8 digital dock managers (DCM), 288Kbits, the Block RAM of 64 * 16kByte, 64 XtremeDSP unit, 640 configurable I/O pins.FPGA is a digital center of the present invention, accomplishes nearly all steering logic, comprising: pci interface control module, RAM control module, high-speed DAC control module, radar waveform control module etc.

High-speed DAC module: DAC is the most key analog device of the present invention, and its performance is directly determining the quality of simulating signal.And the selection of D/A chip needs the strict influence of considering factors such as switching rate, quantizing bit number, power consumption.At present the switching rate D/A chip that reaches 1.2Gpbs has the AD9736 that TS86101G2B that atmel corp provides and ADI company provide, and has taken all factors into consideration the AD9736 that above-mentioned factor the present invention has adopted ADI company.The switching rate of AD9736 is 1.2Gsps, bit wide 14bits, and data input level adopts low-voltage differential signal level---LVDS, and sufficiently high data transformation rate both was provided, and has reduced the power consumption of system again.

Control module through the FPGA inside modules between above-mentioned each module realizes connection to each other; Wherein the pci interface control module is accomplished docking of FPGA module and pci interface module, and the data of control host computer generation are transferred to the FPGA inside modules by the pci interface module; RAM control module completion FPGA module is docked with the RAM module, has realized the transmission of data between FPGA and ZBT-SRAM; High-speed DAC control module completion FPGA module is docked with the high-speed DAC module, and control high-speed DAC module produces various radar waveforms.

A kind of UWB radar signal production method based on FPGA of the present invention is specially:

(1), the generation of Wave data

The UWB radar signal simulator that the present invention proposes is based on the Direct Digital Waveform synthetic method, and wherein the generation of Wave data is accomplished by host computer PC 104; The host computer PC 104 main settings of accomplishing various output waveforms, and pass through the sampled data that in house software produces output waveform.

(2), the transmission of Wave data

The UWB radar signal simulator that the present invention proposes provides a PC104 (PCI) interface to be used for realizing the transmission of Wave data between host computer PC 104 and FPGA, and wherein transmission time sequence and the transmission mode of Wave data between the two realized by the control of PC104 (PCI) interface module.

(3), the storage of Wave data

FPGA receives from first will sampled data being stored after the sampled data of host computer PC 104, and the present invention adopts the ZBT-SRAM stored waveform data of 6 32 bit wides, realizes total line use ratio of 100%; One group of per 3 storer, by two independently controller controls, two groups of work of both can having rattled also can be worked simultaneously; The storing process of whole data is controlled realization jointly by FPGA module and RAM module.

(4), the conversion of Wave data

The Wave data ultimate demand of storing among the ZBT-SRAM is exported with the form of simulating signal through digital-to-analog conversion, thereby obtains the radar signal of actual demand; FPGA module controls RAM module is visited ZBT-SRAM in order to read the wherein Wave data of storage, then the Wave data that reads is passed to the high-speed DAC module successively, is accomplished the generation of various radar waveforms at last by FPGA module controls high-speed DAC module.

The UWB radar signal production method that the present invention proposes based on FPGA, its advantage and effect mainly are:

(1) the present invention has adopted system architecture and the digital production method of FPGA, accomplishes various waveform compilations and data generation task by PC104 (PCI) host computer, utilizes FPGA control high-speed DAC to accomplish the UWB analogue signal generating.It is compatible to bring into play PC104 main frame and PC operating system, and algorithm software is write easy advantage; Bring into play the advantage that FPGA produces quick logic and the generation of DAC high-speed data simultaneously.Both ensured the dirigibility of system, satisfied in the practical application requirement again real-time.

(2) the UWB radar signal production method of the present invention's proposition; Utilize coherent/non-coherent pulse strings such as the various pulse internal modulation simple signals of the real-time generation of FPGA control, pulse internal modulation LFM signal, pulse internal modulation phase-coded signal, pulse repetition time victory become, the pulse repetition time slides, the pulse repetition time shakes, pulse width victory change, pulse width slip, pulse width shake, can be used for fields such as various PD radar signal generations, Active Jamming.

(3) the UWB radar signal production method of the present invention's proposition not only can be used for various radar signals and produces.Because native system has programmable characteristics, can produce various forms of UWB modulation signals, can be used for fields such as communication.

(4) the present invention has that the systemic software development cost is low, the cycle is short, be convenient to safeguard and characteristics such as function upgrading.In addition, FPGA makes things convenient for the developer to carry out performance adjustment.

Description of drawings

Fig. 1 is a digital signal production method synoptic diagram.

Fig. 2 is a digital signal production method structured flowchart.

Fig. 3 is a PD radar type signal production method synoptic diagram.

Fig. 4 is that pulse parameter changes PD radar signal production method synoptic diagram.

Fig. 5 is an irregular signal generating method synoptic diagram of recurrence interval.

Fig. 6 is based on the UWB radar signal simulator structural drawing of FPGA.

Fig. 7 is a FPGA built-in function structural drawing.

Fig. 8 is ZBT-SRAM controller architecture figure.

Fig. 9 is input Data Format Transform figure.

Embodiment

Below in conjunction with accompanying drawing, the concrete technical scheme of invention is done further explanation.

The method that the present invention produces simulating signal adopts storer direct-reading method (DDWS), and signal generating method is as shown in Figure 1.At first the signal waveform of user's design demand generation is sampled to signal waveform according to the sampling law.Digital signal after then will sampling is kept in the storer.When producing simulating signal at last, the address of the storer that produces according to sampling clock is read the numerical value of each sampled point successively, converts simulating signal to through DAC.

The signal simulator production method structure of the present invention's design is as shown in Figure 2, can produce two-way quadrature (I, Q) simulating signal simultaneously, thereby can produce the more simulating signal of high bandwidth.Calculate the numerical value of I, each sampled point of Q two-way orthogonal signal in advance, and deposit in the HSM in order.When needing to produce simulating signal,, read the numerical value of each sampled point successively, convert I, Q two-way orthogonal signal to through DAC by the address of FPGA according to the storer of sampling clock generation.

And the PD radar signal be with impulse form repeat to occur as shown in Figure 3, the signal form of standard P D radar is by following parameter determining: signal form in pulse repetition time PRT, pulse width τ, the pulse.Signal frequency usually can conversion in the PRT in the practical application, arteries and veins, and irregular, the prompt change of pulse repetition time of Here it is pulse repetition time, arteries and veins contain the PD signal that frequent rate linear change, arteries and veins contain forms such as frequency agility frequently.

The producing method of standard P D radar is as shown in Figure 3, when three parameter PRT, τ and f are constant, just can confirm signal form; Utilize counter gating pulse repetition period and width respectively when producing standard P D signal, when the time arrives in the pulse signal, open DAC the output of the signal in the storer is produced signal in the pulse.

For the antijamming capability that improves radar signal with satisfy processing requirements such as ambiguity solution, the PD radar all can adopt the signal form of multiple complicacy in practical application, its producing method is as shown in Figure 4, except PRT, τ and f, has increased by two parameter δ and Δ.By the pulse repetition time and the width of counter controls PD signal, just each pulse repetition time and width all can change equally, and its Changing Pattern is controlled respectively by δ and Δ.When δ=0, when Δ is constant, generation is the PD radar signal of sliding the pulse repetition time; When δ=0, when Δ is random number, generation is the PD radar signal of pulse repetition time shake; When Δ=0, when δ is constant, generation is the PD radar signal that pulse width is slided; When Δ=0, when δ is random number, generation is the PD radar signal of pulse width shake; In addition, carrier frequency changes simultaneously in the pulse repetition time of PD radar signal and the arteries and veins, thereby forms more complicated signal mode.

Utilize method shown in Figure 5 to adopt the control of many group PRT parameters, can accomplish irregular waveform of pulse repetition time.

The system architecture of the above-mentioned UWB radar signal of the completion production method that the present invention proposes is as shown in Figure 6.System comprises parts such as PC104 (PCI) interface module, SRAM module, FPGA module and high-speed DAC module.The user accomplishes radar waveform editor, the generation of signal sampling point value through the software on the PC104 host computer, through driver, signal numerical value is sent in the RAM module of FPGA control through PC104 (PCI) interface; Produce various radar waveforms by FPGA module controls high-speed DAC module at last.Wherein the FPGA module is a core controller of the present invention, accomplishes functions such as the control of PC104 of the present invention (PCI) interface, SRAM module controls, DAC control, radar waveform control.The high-speed DAC module is a core analog device of the present invention, and its performance has directly determined the quality of simulating signal.The SRAM module is used for depositing Wave data in the present invention.PC104 (PCI) interface module is the interface that the present invention communicates by letter with host computer.

The present invention provides the HPI of a PC104 (PCI), accomplishes data transmission with the PC104 main frame through the PCI agreement.Pci interface chip adopts PCI9054, and PCI9054 is one 32 33M bus master I/O accelerators, supports the PCI2.2 standard fully, reaches as high as the burst speed of 132MB/s.PCI9054 has adopted the advanced data pipeline framework (Data pipe architecture) of PLX company, supports three kinds of operator schemes, the M pattern; The C pattern; The J pattern, wherein the J pattern is the data line and the address wire multiplexer mode of local bus, the pattern that also is among the present invention to be adopted.

The present invention adopts the ZBT-SRAM of 6 32 bit wides as metadata cache, and per 3 one group constitutes unique storage group structure, respectively by two independently controller controls.The access speed of SRAM can reach 200MHz, so the maximum data bandwidth of each controller is 16*1200Mbps, can satisfy the data storage needs of 1.2GHz data rate 16bits width D AC.

DAC of the present invention adopts the AD9736 of ADI.As a UWB radar signal simulator, the performance of D/A conversion chip has directly determined the quality of simulating signal, and the selection of D/A chip needs the strict influence of considering factors such as switching rate, quantizing bit number, power consumption.At present the switching rate D/A chip that reaches 1.2Gpbs has the AD9736 that TS86101G2B that atmel corp provides and ADI company provide, and has taken all factors into consideration the AD9736 that above-mentioned factor the present invention has adopted ADI company.The switching rate of AD9736 is 1.2Gsps, bit wide 14bits, and data input level adopts low-voltage differential signal level---LVDS, and sufficiently high data transformation rate both was provided, and has reduced the power consumption of system again.

The Virtex-4 series of products XC4VLX40 that FPGA of the present invention adopts Xilinx company to release.This FPGA inside has rich in natural resources, comprises the distributed RAM of 8 digital dock managers (DCM), 288Kbits, the Block RAM of 64 * 16kByte, 64 XtremeDSP unit, 640 configurable I/O pins.FPGA is a control core of the present invention, accomplishes nearly all steering logic, comprising: pci interface module controls, SRAM module controls, high-speed DAC module controls, radar waveform control etc.

FPGA built-in function structure is as shown in Figure 7.Inner each functional module connects each functional module concurrent working through bus.Pci interface provide and the PC104 host computer between data channel, host computer is through this interface, inner each functional module of addressable FPGA is through the working method of each module of register controlled.

The technical indicator of signal simulator comprises: bandwidth, stability, signal kinds etc., signal bandwidth is the important technology index of simulator.The present invention utilizes two-way high-performance DAC chip, and producing the two-way bandwidth is the simulating signal of 600MHz.The simulating signal that one tunnel bandwidth is 1.2GHz can be synthesized through the IQ orthogonal modulation in the outside.

Numerical approach also has an important techniques index: the time span of simulating signal.Time span T is by memory depth M and sample rate f _sDecision, T=M/f _sM=6M among the present invention, f _s=1.2GSPST=6M/1.2G=500 μ S promptly can produce the long data of 500 μ S.The present invention can produce the PD radar signal of pulse width less than 500 μ S bandwidth 1GHz.

The control of 1.2GSPS high-performance DAC, data storage, transmission method are directly determining performance index of the present invention among the present invention, and its data path and control method are as shown in Figure 8.Comprise PCI, SRAM, three data interfaces of DAC, three's data width, message transmission rate are not quite similar.The present invention utilizes two different FIFO of I/O width to accomplish the data transmission between the three.FIFO between PCI and the SRAM (being called write data FIFO) input 32bits output 96bits corresponds respectively to PCI32bits, 3 common 96bits of SRAM, and the clock of PCI input data is 33MHz, and the clock that outputs to the SRAM data is 200MHz.FIFO between SRAM and the DAC (being called read data FIFO) input 96bits output 14bits corresponds respectively to 3 SRAM 96bits, DAC14bits altogether, and the clock of SRAM input data is 200MHz, and the clock that outputs to the DAC data is 1.2GHz.

Write data FIFO input data transfer rate is 33MHz*32bits=132MBPS, and the data transfer rate of output is 200MHz*96bits=2.4GBPS, and the input data transfer rate is less than output data rate, and the ratio of inputoutput data rate is 5.5%.The present invention produces the PD radar signal, and what need transmission is signal in the arteries and veins, can be through PC104 (PCI) real-time Transmission less than 5.5% PD radar for dutycycle.In fact, signal generally is changeless in the arteries and veins of PD radar signal, therefore can when system initialization, be bound through pci bus by PC104.Also to transmit other parameters of PD signal during bookbinding, like PRT, τ etc.Therefore this shows that write data FIFO uses when system initialization, import data and be slower than output data and can increase the system initialization time, the performance index the when system that can't influence uses.

FIFO is different with write data, and read data FIFO is the data channel that connects between SRAM and the DAC, and the inputoutput data rate of this FIFO must strictly be mated, to satisfy the requirement of DAC data output.Read data FIFO input data transfer rate is 200MHz*96bits=2.4GBPS, and the data transfer rate of output is 1.2GHz*14bits=2.1GBPS, and the input data transfer rate satisfies the requirement that DAC exports at a high speed greater than output data rate.

Have only 28bits useful in the data of the 32bits that transmits on the pci bus, every 14bits is as the data input of DAC.The format conversion of data is as shown in Figure 9 in the system work process.The data of transmitting on the pci bus are designated as D0, D1, D2 in order ..., wherein every 3*32bits data constitute one group; FPGA stores every group of data into ZBT-SRAM0 respectively, and ZBT-SRAM1 among the ZBT-SRAM2, promptly stores D0 among the ZBT-SRAM0; D3 ..., store D1 among the ZBT-SRAM1, D4 ..., store D2 among the ZBT-SRAM2; D5 ..., per afterwards three data are transferred to read data FIFO for one group, data in read data FIFO according to D0_H; D0_L, D1_H, D1_L ... Storage; The high 16bits (14bits is valid data) of the corresponding D0 of D0_H wherein, the low 16bits (14bits is valid data) of the corresponding D0 of D0_L, last reading is converted into simulating signal through AD9736 in order according to the data in the FIFO.

During system initialization, Wave data is transferred among the input FIFO of SRAM control module through the pci bus interface of 32bits in the arteries and veins that the user generates; The data that the control module of SRAM will be imported among the FIFO are delivered to respectively among the SRAM of 3 32bits; When analogue signal generating in arteries and veins during signal, the SRAM control module reads 3 SRAM data of 3*32bits altogether with the speed of 200MHz, and data are transferred to DAC through the output of the DAC in control module FIFO; FPGA is input to DAC with the speed of the 1.2GHz data that 14bits is wide; Convert simulating signal into through reconfigurable filter etc. after the DAC chip output.

Performance index of the present invention are as shown in table 1.

Sequence number	Project	Performance index	Remarks
				1	Bandwidth	1.2GHz
2	Signal SFDR (SFDR)	51dBc
				3	Supply voltage	12V、5V
4	Power consumption	10W

Because the present invention adopts ultra-large FPGA as the major control chip, PC104 is as host computer, so system has stronger programmability and extendability.Utilize the powerful signal handling capacity of FPGA, can in FPGA, write live signal and produce logic, thereby overcome the restriction of memory span and PCI transmission speed.Can accomplish the generation of random waveform through user program.

Claims (1)

1. UWB radar signal simulator based on FPGA, this signal simulator mainly comprises: PC104 interface module, RAM module, FPGA module and high-speed DAC module;

PC104 interface module: the HPI of a PC104 is provided, accomplishes with the main frame of PC104 form and accomplish data transmission through the PCI agreement; The PC104 interface module adopts the PCI9054 chip, and PCI9054 has adopted the advanced data pipeline framework of PLX company, supports three kinds of operator schemes; The M pattern, C pattern, J pattern; Wherein the J pattern is the data line and the address wire multiplexer mode of local bus, also is the pattern that is adopted during this paper designs;

The RAM module: the ZBT-SRAM that adopts 6 32 bit wides realizes total line use ratio of 100% as metadata cache, and maximum operation frequency is 200MHz; The maximum data bandwidth of each controller is 12*1600Mbps, satisfies the data rate request of current most of sampling rate DAC;

The Virtex-4 series of products XC4VLX40 that FPGA module: FPGA adopts Xilinx company to release; This FPGA inside has rich in natural resources, comprises the distributed RAM of 8 digital dock managers, 288Kbits, the Block RAM of 64 * 16kByte, 64 XtremeDSP unit, 640 configurable I/O pins; FPGA accomplishes steering logic, comprising: pci interface control module, RAM control module, high-speed DAC control module, radar waveform control module;

The high-speed DAC module: the DAC chip is selected the AD9736 of ADI company; The switching rate of AD9736 is 1.2Gsps, bit wide 14bits, and data input level adopts low-voltage differential signal level---LVDS, and sufficiently high data transformation rate both was provided, and has reduced the power consumption of system again;

Control module through the FPGA inside modules between above-mentioned each module realizes connection to each other; Wherein the PC104 interface control module is accomplished docking of FPGA module and PC104 interface module, and the data of control host computer generation are transferred to the FPGA inside modules by the PC104 interface module; RAM control module completion FPGA module is docked with the RAM module, has realized the transmission of data between FPGA and ZBT-SRAM; High-speed DAC control module completion FPGA module is docked with the high-speed DAC module, and control high-speed DAC module produces various radar waveforms;

Wherein, the ZBT-SRAM of 6 32 bit wides in the described RAM module is as metadata cache, one group of per 3 storer, and by two independently controller controls, two groups of work of both can having rattled also can be worked simultaneously;

Wherein, according to the production method based on the UWB radar signal simulator signal of FPGA, it is characterized in that: this method is specially:

(1), the generation of Wave data

The UWB radar signal simulator is based on the Direct Digital Waveform synthetic method, and wherein the generation of Wave data is accomplished by host computer PC 104; The host computer PC 104 main settings of accomplishing various output waveforms, and pass through the sampled data that in house software produces output waveform;

(2), the transmission of Wave data

The UWB radar signal simulator provides a PC104 interface to be used for realizing the transmission of Wave data between host computer PC 104 and FPGA, and wherein transmission time sequence and the transmission mode of Wave data between the two realized by the control of PC104 interface module;

(3), the storage of Wave data

FPGA receives from first will sampled data being stored after the sampled data of host computer PC 104, adopts the ZBT-SRAM stored waveform data of 6 32 bit wides, realizes total line use ratio of 100%; One group of per 3 storer, by two independently controller controls, two groups of work of both can having rattled also can be worked simultaneously; The storing process of whole data is controlled realization jointly by FPGA module and RAM module;

(4), the conversion of Wave data

The Wave data ultimate demand of storing among the ZBT-SRAM is exported with the form of simulating signal through digital-to-analog conversion, thereby obtains the radar signal of actual demand; FPGA module controls RAM module is visited ZBT-SRAM in order to read the wherein Wave data of storage, then the Wave data that reads is passed to the high-speed DAC module successively, is accomplished the generation of various radar waveforms at last by FPGA module controls high-speed DAC module;

Wherein, the control of DAC, data storage, transmission method are directly determining performance index, and its data path and control method comprise PCI, SRAM and three data interfaces of DAC, and three's data width and message transmission rate are not quite similar; Utilize two different FIFO of I/O width to accomplish the data transmission between the three; FIFO between PC104 and the SRAM---be called write data FIFO, input 32bits output 96bits corresponds respectively to PCI32bits, 3 common 96bits of SRAM, and the clock of PCI input data is 33MHz, and the clock that outputs to the SRAM data is 200MHz; FIFO--between SRAM and the DAC is called read data FIFO, and input 96bits output 14bits corresponds respectively to 3 SRAM 96bits, DAC14bits altogether, and the clock of SRAM input data is 200MHz, and the clock that outputs to the DAC data is 1.2GHz;

Write data FIFO input data transfer rate is 33MHz*32bits=132MBPS, and the data transfer rate of output is 200MHz*96bits=2.4GBPS, and the input data transfer rate is less than output data rate, and the ratio of inputoutput data rate is 5.5%; Produce the PD radar signal, what need transmission be the interior signal of arteries and veins, for dutycycle less than 5.5% PD radar through the PC104 real-time Transmission;

FIFO is different with write data, and read data FIFO is the data channel that connects between SRAM and the DAC, and the inputoutput data rate of this FIFO must strictly be mated, to satisfy the requirement of DAC data output; Read data FIFO input data transfer rate is 200MHz*96bits=2.4GBPS, and the data transfer rate of output is 1.2GHz*14bits=2.1GBPS, and the input data transfer rate satisfies the requirement that DAC exports at a high speed greater than output data rate;

During system initialization, Wave data is transferred among the input FIFO of SRAM control module through the pci bus interface of 32bits in the arteries and veins that the user generates; The data that the control module of SRAM will be imported among the FIFO are delivered to respectively among the SRAM of 3 32bits; When analogue signal generating in arteries and veins during signal, the SRAM control module reads 3 SRAM data of 3*32bits altogether with the speed of 200MHz, and data are transferred to DAC through the output of the DAC in control module FIFO; FPGA is input to DAC with the speed of the 1.2GHz data that 14bits is wide; Convert simulating signal into through reconfigurable filter etc. after the DAC chip output.

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