CN103488244A

CN103488244A - Arbitrary waveform generation system and method

Info

Publication number: CN103488244A
Application number: CN201310404488.XA
Authority: CN
Inventors: 陈应兵; 包思云; 刘魁魁
Original assignee: CETC 41 Institute
Current assignee: CETC 41 Institute
Priority date: 2013-09-09
Filing date: 2013-09-09
Publication date: 2014-01-01
Anticipated expiration: 2033-09-09
Also published as: CN103488244B

Abstract

The invention discloses an arbitrary waveform generation system and method for variable-speed waveform data playback based on complex combined triggering. The system comprises a waveform data storage unit and a trigger mode based waveform editing and trigger playback unit; the trigger mode based waveform editing and trigger playback unit comprises a waveform reading address generation subunit and a complex wave synthesis subunit; the waveform reading address generation subunit comprises a pulse gating module, a trigger module, a trigger reset module, a waveform trigger module, a waveform trigger reset module, a waveform trigger buffer module, a sequence trigger module, a sequence trigger repeating module and a sequence trigger setting module. On the basis of real-time digital signal processing, complex combined trigger and variable-speed waveform data playback technologies, the system and method gives full play to the characteristics of all-digital waveform synthesis, high resolution, good signal stability, many signal styles, various modulation and the like, and has the advantages of quick switching, capability of changing length of signal cycles and the like.

Description

A kind of random waveform generation systems and method

Technical field

The invention belongs to random waveform and produce field, be particularly related to a kind of random waveform generation systems of the Wave data variable bit rate playback triggered based on complex combination, and a kind of random waveform method for generation of the Wave data variable bit rate playback triggered based on complex combination.

Background technology

AWG (Arbitrary Waveform Generator) is a kind of multiduty signal driving source, comprises the multiple Digital Modulation functions such as FSK, MSK, QAM, PSK, can produce when complicated and become multiple signals, complex modulated signal.Along with the development of electronic technology, digital baseband modulation signal generation technique has been applied in the every field such as communication, control, measurement widely.It shows as land, sea, air in the effect of military aspect, it is multi-level, the high density of disposing, the very complicated signal Antagonistic Environment that multiple spectra, wide, large bandwidth when large, many kinds of parameters be prompt to be become, the integrated application of multiple working system and multiple Anti-Jamming Technique is feature.Testing performance index for equipments such as various Complex Radars, electronic reconnaissance, communication countermeasure, enemy and we's identification, expansion frequency hopping communicationss, multiple digital modulation signals can be provided, solve maintenance and the training problem of countermeasures set, improve scientific research, production, the maintenance ability of electronic counter-measures equipment.

Current random waveform produces and mainly contains two kinds: the first is to utilize the mode of the digital real-time mode generation of FPGA+DSP, and the second is to utilize the mode of large capacity digital storage wave shape playback (random wave) to realize.These two kinds of modes respectively have relative merits, and the relative wave shape playback mode of bandwidth that real-time mode realizes is little, but the signal pattern can variously convert; The wave shape playback mode can only produce the waveform that storer exists, if the digital signal of storer will convert pattern, can call hard disc data or call the data of external counting machine by external interface by local bus, so waveform speed of download and external interface speed are subject to the impact of bandwidth and the speed of instrument local bus.

In existing instrument and equipment, as Agilent company 33250 in adopt that single triggers, circulation triggers, do not adopt that sequence triggers, combination triggers, can not output phase continuous multi-stage waveform; R& The AFQ100A/B of S company has only adopted single triggering, circulation to trigger, combine Trigger Function, and the signal pattern of output is variation not; In the AWG7122C of Tek company, adopt single triggering, circulation to trigger, happen suddenly and trigger, do not adopted sequence triggering, combination to trigger etc., can not export the multistage waveform with the different time gap.

In existing function generator and AWG (Arbitrary Waveform Generator), exist the signal pattern few, as semiperiod, complete period, 1/4th periodic signals, arbitrarily/periodic signal etc., exist to trigger kind few, and the problem such as sampling rate is immutable in certain triggers.

Summary of the invention

The present invention is directed to above-mentioned shortcoming, a kind of random waveform generation systems of the Wave data variable bit rate playback triggered based on complex combination is provided, and a kind of random waveform method for generation of the Wave data variable bit rate playback triggered based on complex combination.

Its technical solution is:

A kind of random waveform generation systems of the Wave data variable bit rate playback triggered based on complex combination comprises:

The Wave data access unit, for the buffering that completes Wave data and the control of memory interface; To send into FPGA from PCI chip local bus 32 bit data, become after 256 bit data bus and 25 s' address bus data writing FIFO and address FIFO respectively in FPGA inside through the pci interface module converts; The Memory control module is sent in Wave data and address that the Clockreading of inputting with the Memory control module at the opposite side of FIFO writes after handshake; The Memory control module by the Wave data of input and address according to the sequential write memory bar of memory bar; Under reading mode, produce and to read address and send into the Memory control module by reading address generating module, the Wave data that the Memory control module will read after time delay from memory bar is sent on output data bus, exports the data_valid signal simultaneously; The data that Read_FIFO will read from memory bar write FIFO; At the opposite side of read_FIFO, FPGA reads FIFO with 1/16 of DA clock, and 256 bit data that will read send into parallel serial conversion module, converts the data of 16 to and sends into DA and carry out digital-to-analog conversion; Convert continuous read and write to step read-write in FPGA inside by a large amount of FIFO;

Waveform compilation based on triggering mode and triggering playback unit, by inner editing machine, or by interface GPIB or USB, by outer computer, the waveform expression formula being transformed to Wave data is stored in wave memorizer, control the address that address generator changes wave memorizer, export corresponding Wave data, until the end of waveform segment; Mean waveform by outer computer in the mode of text, by revising text in order to reach the purpose of output different wave signal.

The above-mentioned waveform compilation based on triggering mode comprises that with the triggering playback unit reading address of waveform produces subelement and complex wave synthon unit, and the reading address of waveform wherein produces subelement and comprises:

Pulse gate module, using trigger pip as gate-control signal, when trigger pip is effective, play waveform; Trigger useful signal directly as the enable signal of waveform address totalizer, carry out clock one time, totalizer adds 1, and relatively, if equal waveform length, the zero clearing totalizer, make totalizer restart to add up for the output of totalizer and waveform length; Input and the addition of waveform start address of totalizer simultaneously, the reading address of generation waveform;

Trigger module, using trigger pip as an initial signal, trigger pip is sent and is risen or the negative edge useful signal, the waveform address totalizer starts to add up, and carrys out a clock, and totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, the zero clearing totalizer, make totalizer restart to add up; Input and the addition of waveform start address of totalizer simultaneously, the reading address of generation waveform; The trigger pip of outside input acts on the waveform totalizer after edge sense circuit.

Trigger reseting module, using first trigger pip as start signal, follow-up trigger pip is as reset signal, and trigger pip is sent first rising or negative edge useful signal, and the waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, the zero clearing totalizer, make totalizer restart to add up; Simultaneously, trigger pip also, as while totalizer reset signal, is carried out a trigger pip, zero clearing one-accumulate device; The output of totalizer and the addition of waveform start address, the reading address of generation waveform; The trigger pip of the back totalizer that all will reset, make waveform restart to play; The trigger pip of outside input acts on the waveform totalizer after edge sense circuit;

The waveform trigger module, using trigger pip as start signal, trigger pip is sent and is risen or the negative edge useful signal, and the waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, and zero clearing totalizer, forbid that totalizer is cumulative, until next effectively trigger pip enables totalizer simultaneously; The output of totalizer and the addition of waveform start address, the reading address of generation waveform; If trigger while effectively occurring in the waveform broadcasting, trigger pip is invalid; The trigger pip of outside input acts on the waveform totalizer after edge sense circuit;

Waveform triggers reseting module, using trigger pip as start signal, trigger pip is sent and is risen or the negative edge useful signal, and the waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, and zero clearing totalizer, forbid that totalizer is cumulative, until next effectively trigger pip enables totalizer simultaneously; The output of totalizer and the addition of waveform start address, the reading address of generation waveform; If trigger while effectively occurring in the waveform broadcasting, the zero clearing totalizer, make waveform restart to play; The trigger pip of outside input acts on the waveform totalizer after edge sense circuit;

Waveform triggers buffer module, using trigger pip as start signal, trigger pip is sent and is risen or the negative edge useful signal, and the waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, and zero clearing totalizer, forbid that totalizer is cumulative, until next effectively trigger pip enables totalizer simultaneously; The output of totalizer and the addition of waveform start address, the reading address of generation waveform; If trigger while effectively occurring in the waveform broadcasting, trigger pip is until the waveform broadcasting finishes effectively rear; The trigger pip of outside input acts on the waveform totalizer after edge sense circuit;

The sequence trigger module, after receiving triggering, play waveform once, again triggers and play next waveform; Using trigger pip as start signal, trigger pip is sent and is risen or the negative edge useful signal, and the waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, and zero clearing totalizer, forbid that totalizer is cumulative, the sequence address totalizer adds 1, and start address and the waveform length of from the sequence memory the inside, reading next waveform, until next effectively trigger pip enables totalizer; The output of totalizer and the addition of waveform start address, the reading address of generation waveform; If trigger when effectively occurring in waveform and playing, trigger pip is invalid and ignore the waveform broadcasting time; The trigger pip of outside input acts on the waveform totalizer after edge sense circuit;

Sequence triggering replicated blocks, after receiving triggering, play waveform until again trigger next waveform of broadcasting; Using trigger pip as start signal, trigger pip is sent and is risen or the negative edge useful signal, the waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, the zero clearing totalizer, make totalizer restart to add up; After again triggering, the sequence totalizer adds 1, start address and the waveform length of from the sequence memory the inside, reading next waveform; The output of totalizer and the addition of waveform start address, the reading address of generation waveform; If trigger when effectively occurring in waveform and playing, trigger pip until current waveform play finish after effectively and ignore the waveform broadcasting time; The trigger pip of outside input acts on the waveform totalizer after edge sense circuit;

Sequence triggers module is set, and after reception triggers, after broadcasting waveform predetermined number of times, stops, and waits for again and triggering under broadcasting with waveform; Using trigger pip as start signal, trigger pip is sent and is risen or the negative edge useful signal, the waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, the zero clearing totalizer, make totalizer restart to add up, and waveform number of times totalizer adds 1 simultaneously; The value of waveform number of times totalizer and waveform number of times relatively, if the number of times totalizer equals the waveform number of times, forbid that the waveform address totalizer is cumulative; After again triggering, the sequence totalizer adds 1, the start address of from the sequence memory the inside, reading next waveform, waveform length and broadcasting time; The output of totalizer and the addition of waveform start address, the reading address of generation waveform; If trigger while effectively occurring in the waveform broadcasting, trigger pip is until the broadcasting of current waveform finishes effectively rear; The trigger pip of outside input acts on the waveform totalizer after edge sense circuit;

Complicated wave form synthon unit wherein, the reading address that above-mentioned a certain module is produced to waveform is sent into address counter, length counter and repeat counter; When the waveform multiplicity is greater than 1, after a waveform output, the parameter of address counter and length counter reloads, when a waveform end of output, the waveform end signal causes that the sequence address generator points to the address of next waveform, makes functional nucleotide sequence produce next waveform, after memory address is complete, repeat again above process, make output waveform continuous, the waveform by functional nucleotide sequence by the synthetic generation of comparatively simple waveform relative complex.

A kind of random waveform method for generation of the Wave data variable bit rate playback triggered based on complex combination comprises the following steps:

The Wave data access step, for the buffering that completes Wave data and the control of memory interface; To send into FPGA from 32 of PCI chip local bus data, become after 256 bit data bus and 25 s' address bus data writing FIFO and address FIFO respectively in FPGA inside through the pci interface module converts; The Memory control module is sent in Wave data and address that the Clockreading of inputting with the Memory control module at the opposite side of FIFO writes after handshake; The Memory control module by the Wave data of input and address according to the sequential write memory bar of memory bar; Under reading mode, produce and to read address and send into the Memory control module by reading address generating module, the Wave data that the Memory control module will read after time delay from memory bar is sent on output data bus, exports the data_valid signal simultaneously; The data that Read_FIFO will read from memory bar write FIFO; At the opposite side of read_FIFO, FPGA reads FIFO with 1/16 of DA clock, and 256 bit data that will read send into parallel serial conversion module, converts the data of 16 to and sends into DA and carry out digital-to-analog conversion; Convert continuous read and write to step read-write in FPGA inside by a large amount of FIFO;

Waveform compilation based on triggering mode and triggering replay procedure, by inner editing machine, or by interface GPIB or USB, by outer computer, the waveform expression formula being transformed to Wave data is stored in wave memorizer, control the address that address generator changes wave memorizer, export corresponding Wave data, until the end of waveform segment; Mean waveform by outer computer in the mode of text, by revising text in order to reach the purpose of output different wave signal.

The above-mentioned waveform compilation based on triggering mode comprises that with the triggering replay procedure reading address of waveform produces step and complex wave synthesis step, and the reading address of waveform wherein produces step and comprises a certain step in listed step below the selection application:

Pulse gate step, using trigger pip as gate-control signal, when trigger pip is effective, play waveform; Trigger useful signal directly as the enable signal of waveform address totalizer, carry out clock one time, totalizer adds 1, and relatively, if equal waveform length, the zero clearing totalizer, make totalizer restart to add up for the output of totalizer and waveform length; Input and the addition of waveform start address of totalizer simultaneously, the reading address of generation waveform;

Trigger step, using trigger pip as an initial signal, trigger pip is sent and is risen or the negative edge useful signal, the waveform address totalizer starts to add up, and carrys out a clock, and totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, the zero clearing totalizer, make totalizer restart to add up; Input and the addition of waveform start address of totalizer simultaneously, the reading address of generation waveform; The trigger pip of outside input acts on the waveform totalizer after edge sense circuit.

Trigger reset process, using first trigger pip as start signal, follow-up trigger pip is as reset signal, and trigger pip is sent first rising or negative edge useful signal, and the waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, the zero clearing totalizer, make totalizer restart to add up; Simultaneously, trigger pip also, as while totalizer reset signal, is carried out a trigger pip, zero clearing one-accumulate device; The output of totalizer and the addition of waveform start address, the reading address of generation waveform; The trigger pip of the back totalizer that all will reset, make waveform restart to play; The trigger pip of outside input acts on the waveform totalizer after edge sense circuit;

Waveform triggers step, using trigger pip as start signal, trigger pip is sent and is risen or the negative edge useful signal, and the waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, and zero clearing totalizer, forbid that totalizer is cumulative, until next effectively trigger pip enables totalizer simultaneously; The output of totalizer and the addition of waveform start address, the reading address of generation waveform; If trigger while effectively occurring in the waveform broadcasting, trigger pip is invalid; The trigger pip of outside input acts on the waveform totalizer after edge sense circuit;

Waveform triggers reset process, using trigger pip as start signal, trigger pip is sent and is risen or the negative edge useful signal, and the waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, and zero clearing totalizer, forbid that totalizer is cumulative, until next effectively trigger pip enables totalizer simultaneously; The output of totalizer and the addition of waveform start address, the reading address of generation waveform; If trigger while effectively occurring in the waveform broadcasting, the zero clearing totalizer, make waveform restart to play; The trigger pip of outside input acts on the waveform totalizer after edge sense circuit;

Waveform triggers buffer step, using trigger pip as start signal, trigger pip is sent and is risen or the negative edge useful signal, and the waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, and zero clearing totalizer, forbid that totalizer is cumulative, until next effectively trigger pip enables totalizer simultaneously; The output of totalizer and the addition of waveform start address, the reading address of generation waveform; If trigger while effectively occurring in the waveform broadcasting, trigger pip is until the waveform broadcasting finishes effectively rear; The trigger pip of outside input acts on the waveform totalizer after edge sense circuit;

Sequence triggers step, after receiving triggering, plays waveform once, again triggers and plays next waveform; Using trigger pip as start signal, trigger pip is sent and is risen or the negative edge useful signal, and the waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, and zero clearing totalizer, forbid that totalizer is cumulative, the sequence address totalizer adds 1, and start address and the waveform length of from the sequence memory the inside, reading next waveform, until next effectively trigger pip enables totalizer; The output of totalizer and the addition of waveform start address, the reading address of generation waveform; If trigger when effectively occurring in waveform and playing, trigger pip is invalid and ignore the waveform broadcasting time; The trigger pip of outside input acts on the waveform totalizer after edge sense circuit;

Sequence triggering repeating step, after receiving triggering, play waveform until again trigger next waveform of broadcasting; Using trigger pip as start signal, trigger pip is sent and is risen or the negative edge useful signal, the waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, the zero clearing totalizer, make totalizer restart to add up; After again triggering, the sequence totalizer adds 1, start address and the waveform length of from the sequence memory the inside, reading next waveform; The output of totalizer and the addition of waveform start address, the reading address of generation waveform; If trigger when effectively occurring in waveform and playing, trigger pip until current waveform play finish after effectively and ignore the waveform broadcasting time; The trigger pip of outside input acts on the waveform totalizer after edge sense circuit;

Sequence triggers setting steps, after reception triggers, after broadcasting waveform predetermined number of times, stops, and waits for again and triggering under broadcasting with waveform; Using trigger pip as start signal, trigger pip is sent and is risen or the negative edge useful signal, the waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, the zero clearing totalizer, make totalizer restart to add up, and waveform number of times totalizer adds 1 simultaneously; The value of waveform number of times totalizer and waveform number of times relatively, if the number of times totalizer equals the waveform number of times, forbid that the waveform address totalizer is cumulative; After again triggering, the sequence totalizer adds 1, the start address of from the sequence memory the inside, reading next waveform, waveform length and broadcasting time; The output of totalizer and the addition of waveform start address, the reading address of generation waveform; If trigger while effectively occurring in the waveform broadcasting, trigger pip is until the broadcasting of current waveform finishes effectively rear; The trigger pip of outside input acts on the waveform totalizer after edge sense circuit;

Complex wave synthesis step wherein, the reading address that above-mentioned selected a certain step is produced to waveform is sent into address counter, length counter and repeat counter; When the waveform multiplicity is greater than 1, after a waveform output, the parameter of address counter and length counter reloads, when a waveform end of output, the waveform end signal causes that the sequence address generator points to the address of next waveform, makes functional nucleotide sequence produce next waveform, after memory address is complete, repeat again above process, make output waveform continuous, the waveform by functional nucleotide sequence by the synthetic generation of comparatively simple waveform relative complex.

The present invention has following useful technique effect:

The present invention is based on the Real-time digital signal processing technology, complex combination triggering technique and variable bit rate Wave data playback technology, by digital large capacity waveform is synthetic, with complicated triggering mode, realize, Wave data is directly deposited in high-capacity and high-speed DDR2, realize the playback of Wave data by single triggering or complex combination triggering mode, can effectively solve the semiperiod, complete period, 1/4th cycles, the generation of the sophisticated signals such as arbitrarily/mono-cycle (start address is defined as the cycle to waveform length corresponding to the specified storage space of termination address), give full play to all-digital waveform synthetic, resolution is high, signal stabilization is good, the signal pattern is many, the advantages such as kind of modulation is many, and adopt variable sampling speed to realize the quick switching of signal frequency, change the advantages such as length of signal period.

Be in particular in:

(1) used the cycle index that can change signal in complicated triggering, signal arbitrarily/the time function such as edge of the frequency of a cycle, signal, signal, realized the variation of output signal pattern;

(2) utilize variable bandwidth speed playback technology can realize the generation of the sophisticated signals such as the continuously quick frequency variation signal of phase place produces, the generation of the time varying signal of SPA sudden phase anomalies, burr signal;

(3) adopt the all-digital waveform synthesis mode, simple in structure, favorable expandability, spuious low, the interior good frequency response of band of output signal.

The accompanying drawing explanation

Below in conjunction with accompanying drawing and embodiment, the present invention is further described:

Fig. 1 is the schematic block diagram that hardware involved in the present invention forms.

Fig. 2 is the schematic block diagram that the related hardware of the Wave data access unit in the present invention forms.

Fig. 3 is the schematic block diagram that the waveform compilation based on triggering mode in the present invention and the hardware that triggers playback unit form.

Fig. 4 is that the first in the present invention is play the waveform schematic diagram.

Fig. 5 is that the second in the present invention is play the waveform schematic diagram.

Fig. 6 is the third broadcasting waveform schematic diagram in the present invention.

Fig. 7 is that the 4th kind in the present invention play the waveform schematic diagram.

Fig. 8 is that the 5th kind in the present invention play the waveform schematic diagram.

Fig. 9 is that the 6th kind in the present invention play the waveform schematic diagram.

Figure 10 is that the 7th kind in the present invention play the waveform schematic diagram.

Figure 11 is that the 8th kind in the present invention play the waveform schematic diagram.

Figure 12 is that the 9th kind in the present invention play the waveform schematic diagram.

Embodiment

In conjunction with Fig. 1, Fig. 2 and Fig. 3, hardware involved in the present invention forms and can comprise: the FPGA(model is XC6VSX315t), PC (host computer or outer computer), DA converter (AD9736), low-pass filter, clock generation circuit and interface voltage converter.Above-mentioned FPGA is provided with parallel-serial conversion interface, DCM clock distributor, SPI interface, sequence memory, triggering administration module, Clock management module, data management module and sequence administration module.PC connects FPGA by pci interface and interface voltage converter, and FPGA connects the DA converter by parallel-serial conversion interface, SPI interface and DCM clock distributor, and clock generation circuit connects respectively FPGA and DA converter, and the DA converter connects low-pass filter.

Principle of work of the present invention is roughly: host computer (outer computer) first writes phase look-up table by Wave data by interface, during DDS work, the accumulation result of phase accumulator goes the addressing phase look-up table as address, the Wave data that reading phase is corresponding sends the data processing module of rear class to, then discrete Wave data is delivered to DAC.

The present invention adopts memory bar DDR2 as waveform, interface level 1.8V, and capacity is 512M*8bit, reference voltage 0.9V becomes DA(AD9736 to 256 bit data parallel serial conversions in FPGA internal data processing module) desired data 14 bit data.Using the data module of FPGA inside as the Wave data access unit.

A kind of random waveform generation systems of the Wave data variable bit rate playback triggered based on complex combination, comprise Wave data access unit and the waveform compilation based on triggering mode and trigger playback unit.

Above-mentioned Wave data access unit:

In conjunction with Fig. 2, the Wave data access circuit mainly completes the buffering of data and the control of memory interface, mainly contains the PCI control module, various FIFO, and the Memory control module, parallel serial conversion module and corresponding logic control form.

Send into FPGA from 32 of PCI chip local bus data, become after 256 bit data bus and 25 s' address bus data writing FIFO and address FIFO respectively in FPGA inside through the pci interface module converts.Memory control module (adopting ready-made controller) is sent in data and address that the Clockreading of inputting with the Memory control module at the opposite side of FIFO writes after handshake.The Memory control module by the data of input and address according to the sequential write memory bar of memory bar.Under reading mode, produce and to read address and send into the Memory control module by reading address generating module, the data that the Memory control module will read after time delay from memory bar are sent on output data bus, export the data_valid signal simultaneously.The data that Read_FIFO will read from memory bar write FIFO.At the opposite side of read_FIFO, FPGA reads FIFO with 1/16 of DA clock, and 256 bit data that will read send into parallel serial conversion module, converts the data of 16 to and sends into DA and carry out digital-to-analog conversion.Because there is the refresh cycle in memory bar, it is step causing at the read/write memory bar.So convert continuous read and write to step read-write in FPGA inside by a large amount of FIFO.

The above-mentioned waveform compilation based on triggering mode and triggering playback unit comprise reading address generation subelement and the complex wave synthon unit of waveform, and the reading address of waveform wherein produces subelement and comprises that pulse gate module, trigger module, triggering reseting module, waveform trigger module, waveform trigger reseting module, waveform triggering buffer module, sequence trigger module, sequence triggering replicated blocks and sequence triggering module is set.

A distinguishing feature of the present invention is that output signal is had to programmability and the custom feature of simplifying user's operation flexibly, thereby meets the user's request of different levels.Can or by outer computer, the waveform expression formula be transformed to Wave data by interface (GPIB or USB) by inner editing machine is stored in wave memorizer, control the address that address generator changes wave memorizer, export corresponding Wave data, until the end of waveform segment.Can mean waveform in the mode of text by computing machine like this, and can reach the purpose of output different wave signal by revising text.

In conjunction with Fig. 3, under the waveform play mode, address production electric circuit, for generation of the address of reading out data, is also the key point of FPGA indoor design.

Storage address is controlled and sequencer is the essential elements that produces complicated wave form, and the clock signal in Fig. 3 is for illustrating.Address generator circuit mainly comprises sequence memory (being realized by the FPGA internal RAM), totalizer, and comparer and various steering logic form.Sequence memory and wave memorizer are for the shape information storage, the parameter of sequence memory comprises start address (26), waveform length (26), the multiplicity (20) of each waveform, and the sequence counter counting region can be determined by the sequence memory size from 1 to 2K().Sequencer is converted to start address, waveform length and multiplicity by the parameter of list entries storer.While starting output waveform, according to the function difference of selecting, the mode that produces address is also different.

Above-mentioned pulse gate module:

In conjunction with Fig. 4, trigger pip (being a level useful signal), as gate-control signal (there is no functional nucleotide sequence), when trigger pip is effective, is play waveform.Trigger useful signal directly as the enable signal of waveform address totalizer, carry out clock one time, totalizer adds 1, and relatively, if equal waveform length, the zero clearing totalizer, make totalizer restart to add up for the output of totalizer and waveform length.Input and the addition of waveform start address of totalizer simultaneously, the reading address of generation waveform.This mode is fairly simple mode, is usually used in producing signal in arteries and veins.

Above-mentioned trigger module:

In conjunction with Fig. 5, trigger pip (be using pulse useful signal) is as an initial signal, trigger pip is sent and is risen or negative edge (user's setting) useful signal, the waveform address totalizer starts to add up, and carrys out a clock, and totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, the zero clearing totalizer, make totalizer restart to add up.Input and the addition of waveform start address of totalizer simultaneously, the reading address of generation waveform.In this manner, only effectively once, the trigger pip of back all will be less than effect for trigger pip.This mode is fairly simple mode, commonly used and generation continuous wave.In this manner, the trigger pip of outside input acts on the waveform totalizer after edge sense circuit.This kind of triggering is commonly used to produce continuous wave signal.

Above-mentioned triggering reseting module:

In conjunction with Fig. 6, first trigger pip is as start signal, follow-up trigger pip is as reset signal, and trigger pip is sent first rising or negative edge (user's setting) useful signal, and the waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, the zero clearing totalizer, make totalizer restart to add up.Simultaneously, trigger pip also, as while totalizer reset signal, is carried out a trigger pip, zero clearing one-accumulate device.The output of totalizer and the addition of waveform start address, the reading address of generation waveform.In this manner, the trigger pip of the back totalizer (make waveform restart play) that all will reset.In this manner, the trigger pip of outside input acts on the waveform totalizer after edge sense circuit.This kind of triggering can be used for producing the radar signal of two phase coding.When the trigger pulse edge is, sinusoidal wave SPA sudden phase anomalies 180 degree, in the middle of reality realizes, as long as suitably control the cycle of trigger pulse, just can simulate the radar signal of two phase coding.

Above-mentioned waveform trigger module:

In conjunction with Fig. 7, trigger pip is as start signal, trigger pip is sent and is risen or negative edge (user's setting) useful signal, and the waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, and zero clearing totalizer, forbid that totalizer is cumulative, until next effectively trigger pip enables totalizer simultaneously.The output of totalizer and the addition of waveform start address, the reading address of generation waveform.In this manner, if trigger while effectively occurring in the waveform broadcasting, trigger pip is invalid.In this manner, the trigger pip of outside input acts on the waveform totalizer after edge sense circuit.This kind of triggering can be used for producing the short-pulse radar signal.Only need to change carrier cycle, just can change pulse broadband.When sinusoidal wave frequency raises, the broadband of burst pulse is narrower.

Above-mentioned waveform triggers reseting module:

In conjunction with Fig. 8, trigger pip is as start signal, trigger pip is sent and is risen or negative edge (user's setting) useful signal, and the waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, and zero clearing totalizer, forbid that totalizer is cumulative, until next effectively trigger pip enables totalizer simultaneously.The output of totalizer and the addition of waveform start address, the reading address of generation waveform.In this manner, if trigger while effectively occurring in the waveform broadcasting, the zero clearing totalizer, make waveform restart to play.In this manner, the trigger pip of outside input acts on the waveform totalizer after edge sense circuit.This kind of triggering can be used for producing the semiperiod sinusoidal signal.Only need to change the recurrence interval, just can change sine wave period.

Above-mentioned waveform triggers buffer module:

In conjunction with Fig. 9, trigger pip is as start signal, trigger pip is sent and is risen or negative edge (user's setting) useful signal, and the waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, and zero clearing totalizer, forbid that totalizer is cumulative, until next effectively trigger pip enables totalizer simultaneously.The output of totalizer and the addition of waveform start address, the reading address of generation waveform.In this manner, if trigger while effectively occurring in the waveform broadcasting, trigger pip is until the waveform broadcasting finishes effectively rear.In this manner, the trigger pip of outside input acts on the waveform totalizer after edge sense circuit.The periodicity of crossing number decision sinewave output of trigger pulse.

Above-mentioned sequence trigger module:

In conjunction with Figure 10, after receiving triggering, play waveform once, again trigger and play next waveform.Under this pattern, trigger pip is as start signal, and trigger pip is sent and risen or negative edge (user's setting) useful signal, and the waveform address totalizer starts to add up, carry out a clock, totalizer adds 1, and the output of totalizer is compared with waveform length, if equal waveform length, zero clearing totalizer, forbid that totalizer is cumulative, the sequence address totalizer adds 1, start address and the waveform length of from the sequence memory the inside, reading next waveform.Until next effectively trigger pip enables totalizer.The output of totalizer and the addition of waveform start address, the reading address of generation waveform.In this manner, if trigger when effectively occurring in waveform and playing, trigger pip is invalid and ignore the waveform broadcasting time.In this manner, the trigger pip of outside input acts on the waveform totalizer after edge sense circuit.Can produce complicated wave form, each waveform is the monocycle.

Above-mentioned sequence triggers replicated blocks:

In conjunction with Figure 11, after receiving triggering, play waveform until again trigger next waveform of broadcasting.Under this pattern, trigger pip is as start signal, trigger pip is sent and is risen or negative edge (user's setting) useful signal, the waveform address totalizer starts to add up, and carrys out a clock, and totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, the zero clearing totalizer, make totalizer restart to add up.After again triggering, the sequence totalizer adds 1, start address and the waveform length of from the sequence memory the inside, reading next waveform.The output of totalizer and the addition of waveform start address, the reading address of generation waveform.In this manner, if trigger when effectively occurring in waveform and playing, trigger pip until current waveform play finish after effectively and ignore the waveform broadcasting time.In this manner, the trigger pip of outside input acts on the waveform totalizer after edge sense circuit.Can produce complicated multistage waveform, every section waveform is the multicycle, can slitless connection while changing the waveform pattern.And on phase zero points.

Above-mentioned sequence triggers module is set:

In conjunction with Figure 12, after reception triggers, after broadcasting waveform predetermined number of times, stop, waiting for again and triggering under broadcasting with waveform.Under this pattern, trigger pip is as start signal, trigger pip is sent and is risen or negative edge (user's setting) useful signal, and the waveform address totalizer starts to add up, and carrys out a clock, totalizer adds 1, the output of totalizer is compared with waveform length, if equal waveform length, and zero clearing totalizer, make totalizer restart to add up, waveform number of times totalizer adds 1 simultaneously.The value of waveform number of times totalizer and waveform number of times relatively, if the number of times totalizer equals the waveform number of times, forbid that the waveform address totalizer is cumulative.After again triggering, the sequence totalizer adds 1, start address, waveform length and the broadcasting time of reading next waveform from the sequence memory the inside.The output of totalizer and the addition of waveform start address, the reading address of generation waveform.In this manner, if trigger while effectively occurring in the waveform broadcasting, trigger pip is until the broadcasting of current waveform finishes effectively rear.In this manner, the trigger pip of outside input acts on the waveform totalizer after edge sense circuit.Can produce complicated multistage waveform, every section waveform is the multicycle.

Above-mentioned complicated wave form synthon unit, the reading address that above-mentioned a certain module is produced to waveform is sent into address counter, length counter and repeat counter; The output waveform address is also different.When the waveform multiplicity is greater than 1, after a waveform output, the parameter of address counter and length counter must reload.When a waveform end of output, the waveform end signal causes that the sequence address generator points to the address of next waveform, make functional nucleotide sequence produce next waveform, after memory address is complete, repeat again above process, make output waveform continuous, can be by the synthetic waveform that produces relative complex of comparatively simple waveform by functional nucleotide sequence.Can produce complicated multistage waveform, between waveform without docking.

FPGA kernel MIG(Memory control module in this system employing Fig. 1, Fig. 2) carry out the exchange of internal storage data, utilize exchanges data between pci bus and MIG, can be from the hard disk reading out data to memory bar, also can adopt the exchanges data between MIG and FIFO, carry out parallel serial conversion to 14 bit data from memory bar output data, finally export digital to analog converter to, obtain simulating signal.Also can realize the generation of complicated the multi-system signal in conjunction with utilize different triggering method and the variable sampling rate shown in Fig. 3.

The relevant technologies content of not addressing in aforesaid way is taked or is used for reference prior art and can realize.

It should be noted that, under the instruction of this instructions, those skilled in the art can also make such or such easy variation pattern, such as equivalent way, or obvious mode of texturing.Above-mentioned variation pattern all should be within protection scope of the present invention.

Claims

1. the random waveform generation systems of the Wave data variable bit rate playback triggered based on complex combination is characterized in that comprising:

The Wave data access unit, for the buffering that completes Wave data and the control of memory interface; To send into FPGA from 32 of PCI chip local bus data, become after 256 bit data bus and 25 s' address bus data writing FIFO and address FIFO respectively in FPGA inside through the pci interface module converts; The Memory control module is sent in Wave data and address that the Clockreading of inputting with the Memory control module at the opposite side of FIFO writes after handshake; The Memory control module by the Wave data of input and address according to the sequential write memory bar of memory bar; Under reading mode, produce and to read address and send into the Memory control module by reading address generating module, the Wave data that the Memory control module will read after time delay from memory bar is sent on output data bus, exports the data_valid signal simultaneously; The data that Read_FIFO will read from memory bar write FIFO; At the opposite side of read_FIFO, FPGA reads FIFO with 1/16 of DA clock, and 256 bit data that will read send into parallel serial conversion module, converts the data of 16 to and sends into DA and carry out digital-to-analog conversion; Convert continuous read and write to step read-write in FPGA inside by a large amount of FIFO;

2. the random waveform generation systems of a kind of Wave data variable bit rate playback triggered based on complex combination according to claim 1, it is characterized in that: the above-mentioned waveform compilation based on triggering mode comprises that with the triggering playback unit reading address of waveform produces subelement and complex wave synthon unit, and the reading address of waveform wherein produces subelement and comprises:

3. the random waveform method for generation of the Wave data variable bit rate playback triggered based on complex combination is characterized in that comprising the following steps:

4. the random waveform method for generation of a kind of Wave data variable bit rate playback triggered based on complex combination according to claim 3, it is characterized in that: the above-mentioned waveform compilation based on triggering mode comprises that with the triggering replay procedure reading address of waveform produces step and complex wave synthesis step, and the reading address of waveform wherein produces step and comprises a certain step in listed step below the selection application: