CN115150004A - Narrow pulse generator - Google Patents
Narrow pulse generator Download PDFInfo
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- CN115150004A CN115150004A CN202210769530.7A CN202210769530A CN115150004A CN 115150004 A CN115150004 A CN 115150004A CN 202210769530 A CN202210769530 A CN 202210769530A CN 115150004 A CN115150004 A CN 115150004A
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- 238000013500 data storage Methods 0.000 claims abstract description 22
- 238000004891 communication Methods 0.000 claims abstract description 21
- 230000005540 biological transmission Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/50—Transmitters
- H04B10/508—Pulse generation, e.g. generation of solitons
Abstract
The invention provides a narrow pulse generator which comprises a communication module, a waveform data storage module, a waveform playing module and a high-speed output interface module, wherein the communication module is connected with the waveform data storage module and is bidirectionally connected with the waveform playing module, the waveform data storage module is connected with the waveform playing module, the waveform playing module is connected with the high-speed output interface module, and the narrow pulse generator is in data communication with an upper computer through the communication module. The invention outputs narrow pulse signals through the high-speed output interface module, the narrowest pulse width and the time precision of the narrow pulse signals are irrelevant to the clock period and are only relevant to the transmission rate of the high-speed output interface module, and meanwhile, in order to increase the dynamic range, the narrow pulse signals are combined with the coding design, when the wide pulse signals are output, the storage space is saved, and the sequence length is not limited.
Description
Technical Field
The invention relates to the technical field of pulse generators, in particular to a narrow pulse generator.
Background
The existing high-precision pulse signal generation is realized by adjusting the edge position of a signal. Although the method can realize high precision, the shortest pulse width is limited, and narrow pulse signal output cannot be realized.
Disclosure of Invention
The invention provides a narrow pulse generator, which aims at solving the problem that the existing pulse signal generation technology cannot realize narrow pulse signal output.
A narrow pulse generator comprises a communication module, a waveform data storage module, a waveform playing module and a high-speed output interface module, wherein the communication module is connected with the waveform data storage module and is connected with the waveform playing module in a bidirectional mode;
when the narrow pulse generator is in a waveform storage mode, the upper computer encodes a waveform and packs the waveform according to a communication protocol rule, the waveform is input into the waveform data storage module through the communication module, and the waveform data storage module stores the waveform code according to an address in a data packet sent by the upper computer;
when the narrow pulse generator is in a waveform playing mode, the upper computer sends a playing instruction to the waveform playing module through the communication module, the waveform playing module reads a waveform code from the waveform data storage module according to a playing address in the playing instruction, correspondingly decodes the waveform code according to a coding rule, and outputs a target waveform through the high-speed output interface module.
Furthermore, the waveform data storage module checks whether the waveform codes are in compliance before storing the waveforms, and only stores the waveform codes in compliance.
Further, the waveform coding rule is as follows: each group of 16-bit data is a group, and when the most significant bit [15] =0 and the next most significant bit [14] =0, a continuous high level is indicated; when the most significant bit [15] =0 and the second most significant bit [14] =1, the continuous low level exists, and the continuous level duration bit [13 ] is determined by the numerical value, and the unit is 8ns; when the most significant bit [15] =1, the data represented by bit [7 ].
The invention outputs narrow pulse signals through the high-speed output interface module, the narrowest pulse width and the time precision of the narrow pulse signals are irrelevant to the clock period and are only relevant to the transmission rate of the high-speed output interface module, and meanwhile, in order to increase the dynamic range, the narrow pulse signals are combined with the coding design, when the wide pulse signals are output, the storage space is saved, and the sequence length is not limited.
Drawings
FIG. 1 is a block diagram of a narrow pulse generator;
fig. 2 is a waveform diagram of an example of embodiment 1.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description. The embodiments of the present invention have been presented for purposes of illustration and description, and are not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Example 1
A narrow pulse generator is shown in figure 1 and comprises a communication module, a waveform data storage module, a waveform playing module and a high-speed output interface module, wherein the communication module is connected with the waveform data storage module and is connected with the waveform playing module in a two-way mode, the waveform data storage module is connected with the waveform playing module, the waveform playing module is connected with the high-speed output interface module, and the narrow pulse generator is in data communication with an upper computer through the communication module.
When the narrow pulse generator is in a waveform storage mode, the upper computer encodes the waveform and packs the waveform according to communication protocol rules, the waveform is input into the waveform data storage module through the communication module, and the waveform data storage module stores the waveform code according to an address in a data packet sent by the upper computer.
When the narrow pulse generator is in a waveform playing mode, the upper computer sends a playing instruction to the waveform playing module through the communication module, the waveform playing module reads a waveform code from the waveform data storage module according to a playing address in the playing instruction, correspondingly decodes according to a coding rule, and outputs a target waveform through the high-speed output interface module.
The waveform data storage module checks whether the waveform codes are in compliance before storing the waveforms, and only stores the waveform codes of the compliance.
The waveform coding rule is not unique, and the embodiment provides one of the waveform coding rules: each set of 16 bits of data is a set. When the most significant bit [15] =0 and the second most significant bit [14] =0, continuous high level is represented; when the most significant bit [15] =0 and the second most significant bit [14] =1, the continuous low level exists, and the continuous level duration bit [13 ] is determined by the numerical value, and the unit is 8ns; when the most significant bit [15] =1, the data represented by bit [7 ].
Taking the waveform shown in fig. 2 as an example, data is a waveform code sent by an upper computer, and signal is a target waveform output by the high-speed output interface module.
The first complete 16-bit data is 0001 (0000, 0001), the value of its most significant bit [15] =0, the next most significant bit [14] =0, bit [13 ] is 1, and the output waveform is 1 high level of 8 ns.
The second complete 16-bit data is 8055 (1000, 0000, 0101), and its most significant bit [15] =1, so that the data 01010101 represented by bit [7 ].
It should be apparent that the described embodiments are only some of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by one of ordinary skill in the art and related arts based on the embodiments of the present invention without any creative effort, shall fall within the protection scope of the present invention. It is to be understood that the described embodiments are merely a few embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by one of ordinary skill in this and related arts based on the embodiments of the present invention without creative efforts, shall fall within the protection scope of the present invention.
Claims (3)
1. A narrow pulse generator is characterized by comprising a communication module, a waveform data storage module, a waveform playing module and a high-speed output interface module, wherein the communication module is connected with the waveform data storage module and is bidirectionally connected with the waveform playing module;
when the narrow pulse generator is in a waveform storage mode, the upper computer encodes a waveform and packs the waveform according to a communication protocol rule, the waveform is input into the waveform data storage module through the communication module, and the waveform data storage module stores the waveform code according to an address in a data packet sent by the upper computer;
when the narrow pulse generator is in a waveform playing mode, the upper computer sends a playing instruction to the waveform playing module through the communication module, the waveform playing module reads a waveform code from the waveform data storage module according to a playing address in the playing instruction, correspondingly decodes according to a coding rule, and outputs a target waveform through the high-speed output interface module.
2. The narrow pulse generator of claim 1, wherein the waveform data storage module checks whether the waveform code is compliant prior to storing the waveform, and stores only the compliant waveform code.
3. The narrow pulse generator of claim 1 or 2, wherein the waveform encoding rule is: each group of 16-bit data is a group, and when the most significant bit [15] =0 and the second most significant bit [14] =0, continuous high level is represented; when the most significant bit [15] =0, the next most significant bit [14] =1, it means that there is continuous low level, and the value of the continuous level duration bit [13 ] is determined, the unit is 8ns; when the most significant bit [15] =1, the data represented by bit [7 ].
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CN202210769530.7A CN115150004B (en) | 2022-07-01 | 2022-07-01 | Narrow pulse generator |
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Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070024271A1 (en) * | 2005-06-29 | 2007-02-01 | Saeed Azimi | Integrated systems testing |
US20090135863A1 (en) * | 2007-11-28 | 2009-05-28 | Industrial Technology Research Institute | Programmable laser device and method for controlling the same |
JP2010288122A (en) * | 2009-06-12 | 2010-12-24 | National Institute Of Advanced Industrial Science & Technology | Method for transmitting high speed serial signal, and modulator, demodulator |
CN103488244A (en) * | 2013-09-09 | 2014-01-01 | 中国电子科技集团公司第四十一研究所 | Arbitrary waveform generation system and method |
US20150303910A1 (en) * | 2014-04-22 | 2015-10-22 | Qualcomm Incorporated | Pulse-width modulation data decoder |
CN105718404A (en) * | 2016-01-18 | 2016-06-29 | 中国科学技术大学 | Square-wave generator and generating method based on FPGA |
CN106301296A (en) * | 2015-06-26 | 2017-01-04 | 飞思卡尔半导体公司 | Two-integrator impulse wave reshaper equipment, system and method |
CN108769572A (en) * | 2018-04-26 | 2018-11-06 | 国政通科技股份有限公司 | Monitor video file generated, device and terminal device |
US20190196999A1 (en) * | 2016-01-18 | 2019-06-27 | University Of Science And Technology Of China | Fpga-based square-wave generator and square-wave generation method |
US20210215744A1 (en) * | 2020-08-12 | 2021-07-15 | University Of Electronic Science And Technology Of China | System for data mapping and storing in digital three-dimensional oscilloscope |
-
2022
- 2022-07-01 CN CN202210769530.7A patent/CN115150004B/en active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070024271A1 (en) * | 2005-06-29 | 2007-02-01 | Saeed Azimi | Integrated systems testing |
US20090135863A1 (en) * | 2007-11-28 | 2009-05-28 | Industrial Technology Research Institute | Programmable laser device and method for controlling the same |
JP2010288122A (en) * | 2009-06-12 | 2010-12-24 | National Institute Of Advanced Industrial Science & Technology | Method for transmitting high speed serial signal, and modulator, demodulator |
CN103488244A (en) * | 2013-09-09 | 2014-01-01 | 中国电子科技集团公司第四十一研究所 | Arbitrary waveform generation system and method |
US20150303910A1 (en) * | 2014-04-22 | 2015-10-22 | Qualcomm Incorporated | Pulse-width modulation data decoder |
CN106301296A (en) * | 2015-06-26 | 2017-01-04 | 飞思卡尔半导体公司 | Two-integrator impulse wave reshaper equipment, system and method |
CN105718404A (en) * | 2016-01-18 | 2016-06-29 | 中国科学技术大学 | Square-wave generator and generating method based on FPGA |
US20190196999A1 (en) * | 2016-01-18 | 2019-06-27 | University Of Science And Technology Of China | Fpga-based square-wave generator and square-wave generation method |
CN108769572A (en) * | 2018-04-26 | 2018-11-06 | 国政通科技股份有限公司 | Monitor video file generated, device and terminal device |
US20210215744A1 (en) * | 2020-08-12 | 2021-07-15 | University Of Electronic Science And Technology Of China | System for data mapping and storing in digital three-dimensional oscilloscope |
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