JP2010288122A - Method for transmitting high speed serial signal, and modulator, demodulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for transmitting high speed serial signals, a modulator, a demodulator which do not depend on an input data pattern to avoid continuation of the same logic signal in order to prevent Inter Symbol Interference. <P>SOLUTION: A clock frequency of the modulator is set to a value of constant multiples of a clock signal of an original signal which should be transmitted before modulation, bit length of input data is extended to the same magnification as that of the clock frequency inside the modulator, and a dummy signal with a different logic is mixed with "0" or "1" before the modulation to be transmitted. Time when "1" continues as the dummy signal inserted when the input signal is "0" is always shorter than time when "1" continues among output signals to the input signal "1". The dummy signal is inserted so that long time average of duty ratio of a modulator output signal matches to a communication standard. At an input initial stage on the receiving side, the inserted dummy signal is removed by an analog element to reproduce an original signal in an RZ or NRZ format. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a data modulation / demodulation method and apparatus in a serial data transmission system, and more particularly to a technique for transferring data having an arbitrary duty ratio.

In high-speed serial data transfer, a modulation / demodulation method is used so as to avoid the H level (“1”) and L level (“0”) from continuing for a long time in the transferred digital data string. In a transmission line with large frequency dispersion, data that is logically equal to the transmission data without interfering with the level is not sufficiently lowered or fully raised if there is a short change after “1” or “0” continues for a long time, called Inter Symbol Interference. This is because the phenomenon of not necessarily being transferred occurs (see Non-Patent Document 1).
In order to avoid this problem, a modulation scheme is applied which avoids the same logic level being continued for a long time and ensures that the duty ratio of transferred data is close to 50%. For example, a modulation method called 8B / 10B conversion is frequently used in the current high-speed serial communication (see Non-Patent Document 2).

Satoshi Shida, “Introduction to High-Speed Digital Data Transmission”, Transistor Technology, March 2004 Franaszek et al., US Patent Number; 4,486,739, “BYTE ORIENTED DC BALANCED (0,4) 8B / 10B PARTITIONED BLOCK TRANSMISSION CODE”

The prior art disclosed in the above Non-Patent Document 1 is based on the premise that the modulated signal is decoded on the receiving side. However, there are many cases where existing decoders cannot be implemented because the conversion rules are complicated and the circuit scale is large.
In order to improve such a situation, there is a need for a communication means that maintains a 1-bit data string having an arbitrary pattern without having "1" and "0" continuing for a long time and having a duty ratio close to 50%. Yes.
Specifically, this applies to a case where a superconducting circuit including a Josephson element is provided on the receiving side, and a device provided with the superconducting circuit cannot use a conventional encoding device.

Although it is practically impossible to configure a demodulator circuit for 8B / 10B conversion or 64B / 66B conversion with a superconducting circuit, if an arbitrary waveform generator is produced using a superconducting circuit, any superconducting circuit can be used. Data pattern (a signal whose duty ratio is significantly lower than 50% and is outside the allowable range of the standard on the transmission side) needs to be transmitted and processed by the superconducting circuit. An arbitrary waveform generator based on the superconducting device that we have constructed is schematically shown in FIG.
FIG. 1 is a schematic diagram of a pulse-driven Josephson arbitrary waveform generator.
Arbitrary waveform generation device is 4 channel PPG (4 channel PPG) (device having 4 independent 1-bit voltage pulse train output ports, 4 outputs are synchronized), “4: 1 MUX with E / O” (It is a device having a 4-channel voltage pulse train input port and a 1-channel optical pulse train output port, and four input signals are sequentially output at a clock frequency four times that of the input signal). FiberAmp. (Apparatus for amplifying light pulse intensity), Att. (Apparatus for attenuating the intensity of light pulses) The 4K refrigerator is composed of a PD and a JAA.

4-channel PPG (4-channel PPG)
“4: 1 MUX with E / O” is a device for outputting voltage pulse trains that have entered four independent input ports as optical pulses at a clock frequency that is four times as high,
“FiberAmp., Att.” Is an apparatus for obtaining an optical pulse of arbitrary intensity by combining amplification and attenuation of the intensity of an optical pulse.
The PD of the 4K refrigerator is a device that converts an optical pulse train into a current pulse train,
4K refrigerator JA is an element in which Josephson junctions are connected in series.
The digitizer is a device for measuring the output voltage waveform of the Josephson junction,
The computer generates a pulse pattern to be output from the 4: 1 MUX with E / O, writes a data pattern necessary for generating the optical pulse pattern to the PPG, and performs the Att. Is a device that controls the intensity of the light pulse by adjusting the voltage and reads the measured data of the voltage waveform generated by JJA from the digitizer.
The arbitrary waveform generating apparatus having such a configuration as a whole generates a voltage waveform of an arbitrary shape according to the same principle as a certain portable music player, and the amplitude of the output voltage waveform is strictly defined mechanically. Operates to be a value.

In the arbitrary waveform generation device of FIG.
Light that generates an optical pulse pattern with a duty ratio of 25% at the transmitting side device, inputs the optical pulse converted to a current pulse at the receiving side, and inputs it to the Josephson junction, and inputs the average output voltage of the Josephson junction element FIG. 2 shows an observation as a function of the average power of the pulse signal.
The logical pattern of the input pulse waveform is shown as a 16-digit numerical value expressed in hexadecimal in FIG. 2 together with the average duty ratio.

FIG. 2 is a characteristic diagram of the average power (Optical Power) of the input optical pulse signal versus the average output voltage (Voltage) of the Josephson junction element in the arbitrary waveform generator.
FIG. 2 shows that when the duty ratio of the transmission data becomes 35% or less, the quantization step disappears and the transmission data does not reach the reception side (Josephson junction) correctly. This indicates that the transmission data is not correctly converted into an optical pulse by the optical pulse generator.
In FIG. 2, the vertical axis represents the average output voltage of the Josephson junction element, and the horizontal axis represents the average power of the optical pulse signal. “O” in FIG. 2 indicates a duty ratio of 48.4375%,
“●” indicates a duty ratio of 43.75%.
“□” indicates a duty ratio of 37.5%.
“-” Means a duty ratio of 31.25%,
“---” represents a characteristic with a duty ratio of 34.375%.

Theoretically, when the input waveform is correctly processed by the superconducting circuit, a quantized voltage step is observed in which the output voltage of the Josephson junction does not change with respect to the change in optical power. The magnitude of this quantization voltage step is a completely calculable value that depends only on the number of Josephson junctions and the number of pulses input to the Josephson junction array per unit time.
When the duty ratio is 48.4375%, 43.75%, or 37.5%, the quantization step appears. However, when the duty ratio is 34.375% or 31.25%, the quantization voltage step cannot be observed.

  This phenomenon is based on the premise that the optical pulse pattern generator used in this experiment (“4: 1 MUX with E / O” in FIG. 1) is used within a duty ratio of 35% to 65%. This is because the optical pulse pattern input to the Josephson junction is logically completely different from the data to be transmitted to the Josephson junction. It is common sense that the duty ratio of data transmitted in general serial data transmission, including optical communication in which this optical pulse generator is mainly used, is used near 50%, and the duty ratio deviates greatly from 50%. Modulation is performed using an encoding method that ensures that the duty ratio is approximately 50% for any possible signal.

In FIG. 2, a signal having a duty ratio of 35% or less causing the collapse of the quantization voltage step is transmitted using, for example, the 8B / 10B conversion or the 64B / 66B encoding method used for Ethernet communication. It is possible to adjust the optical pulse pattern so that the duty ratio is around 50%.
However, if the demodulator cannot be mounted on the superconducting circuit on the receiving side, the intended output signal cannot be obtained. The example shown in FIG. 2 is an experiment using test data with a duty ratio up to about 30%, but the data that we originally want to transmit is typically an arbitrary pulse pattern with a smaller duty ratio of 25%. The value of 25% is derived from the fact that the duty ratio is 25% when a mathematical sine wave is converted into a 1-bit return-to-zero data pattern by a kind of coarse / fine modulation called delta-sigma modulation. In our group, a current pulse train that is logically equal to this data pattern is input to the Josephson junction, and a quantized voltage pulse train that is logically equivalent to the input current pulse train is generated from the Josephson junction, and this voltage pulse train is low-pass. It aims to realize an AC voltage standard based on quantum mechanics by generating a quantized sinusoidal voltage signal through a filter (low-pass filter). When realizing an arbitrary voltage waveform generator including a DC offset voltage, the waveform output from the Josephson junction is not limited to a sine wave. In the worst case, the duty ratio of data input to the Josephson junction is 0%. It can be.

For this reason, it is necessary to develop a new encoding rule for logically operating the transmission-side device, and on the receiving side, a mechanism for correctly decoding the original signal by a small-scale circuit is developed. Is inevitable.
The above example is a case where a superconducting circuit is used for the receiving circuit that we faced, but the same applies to general electronic circuits and optical device circuits operating at room temperature where the size of the receiving circuit is limited. May cause problems.

  An object of the present invention is to prevent inter-symbol interference at the time of high-speed serial data transfer, so that the same logic signal is not continued during serial data transfer without depending on the data pattern of the input signal (signal to be transmitted). A high-speed serial signal transmission method, modulation, and demodulator are provided.

  In order to achieve the above object, according to the present invention, according to a predetermined data conversion rule, the clock frequency of the modulator is set to an integer multiple of the clock frequency of the original data before modulation (an arbitrary integer according to the data conversion rule ( N) times), and bit extension of the bit length to N times (arbitrary integer (N) times) (for example, 4 (arbitrary integer (N) times) for 1 bit of the original data) Bit) and dummy signals having different logics are mixed with “0” or “1” before modulation (sign extension). As a result, it is possible to avoid that “0” or “1” continues for 3 bits or more for an arbitrary data pattern, and the duty ratio (ratio of “1” in the data pattern) can be set to an arbitrary value, for example, It becomes possible to set it near 50%.

The modulator includes a code spreader, a frequency integer multiplier, a serializer (multiplexer), and the like.
The code spreader used in the modulator functions as a device for assigning an integer multiple (N) bits with a predetermined conversion rule and extending the code for one bit of the input 1-bit data string during input processing. When output, it functions as a device that outputs the extended N-bit code in parallel.
The data conversion rule satisfies one or more of the following conditions (1) to (4).
(1) Into N-bit data after sign extension, a dummy signal having a different logic from 0 or 1 before extension is mixed.
(2) Adjustment is made so that the duty ratio in the N bits after sign extension falls within the range of the physical system or communication standard used for communication.
(3) A time t0 in which “1” as a dummy signal inserted into the original data “0” continues is shorter than a time t1 in which “1” continues in data obtained by spreading the original data “1”. To do.
(4) The number of continuous 1 included in the output data (pulse area) is set to two types.

On the demodulator side, the dummy signal inserted on the modulator side is removed using an analog element or a digital circuit, and the original data is reproduced.
The demodulator stores N-bit data patterns assigned to “0” and “1” before sign extension, and stores N-bit data patterns input as modulator outputs. It is determined whether it corresponds to “0” or “1” before sign extension.
The specification of the demodulating functional element used in the demodulator outputs N for 1 as a dummy signal inserted with respect to the original 0 before sign extension, and N which sign-extends the original 1 before sign extension. 1 is output for consecutive 1 included in bit data, and 0 is always output for input 0.

Demodulation functional elements include, for example, Josephson junction elements, Schmitt trigger circuits,
Among these, in the case of a Josephson junction element, the input is an input current pulse, and the output is an output current pulse.
By adjusting the dummy signal pattern to be inserted according to the allowable duty ratio range of the circuit elements constituting the transmitter (including the modulator) and the receiver (including the demodulator), the operating margin on the receiving side is reduced. Accordingly, the probability of communication error can be further reduced.

Specifically, the following solution is adopted in order to achieve the above object.
(1) A high-speed serial signal transmission method uses a digital data string input signal transferred in a serial data transfer system as a bit of an integer N multiple of 3 or more for one bit of the 1-bit data string. In accordance with a predetermined data conversion rule, N-bit data after expansion is allocated so that dummy signals having different logics are mixed with 0 or 1 before expansion, and the allocated and expanded N-bit code is formed in parallel. , Sequentially transmitting the N-bit parallel code at a clock frequency N times the clock frequency of the digital data;
On the receiving side, an N-bit data pattern assigned to 0 and 1 before expansion based on the predetermined conversion rule is stored,
The N-bit data pattern of the data string signal received in order is inversely converted to 0 and 1 before the extension based on the predetermined conversion rule.

(2) The data conversion rule is set so that the number of consecutive 1s included in the expanded data becomes two types.
(3) The modulator receives the same clock frequency as the clock frequency of the serial data input signal, and outputs a bit of an arbitrary integer N of 3 or more to one bit of the 1-bit data string of the serial data input signal. According to a predetermined data conversion rule, N-bit data after expansion is allocated so that dummy signals having different logics are mixed with 0 or 1 before expansion, and the allocated and expanded N-bit code is output in parallel. A sign extender, and a frequency integer multiplier of a clock frequency that is inputted after being inputted with the same clock frequency as the clock frequency of the serial data input signal, is converted into a frequency that is a multiple of an arbitrary integer N of 3 or more of this clock frequency And the signals output in parallel from the sign extender in order based on the N times the clock frequency from the frequency integer multiplier. It consists of a serializer that outputs as a serial data output signal.

(4) The data conversion rule is set so that the number of consecutive 1s included in the expanded data becomes two types.
(5) In the data conversion rule, a dummy signal having a logic different from 0 or 1 before expansion is mixed in the expanded data.
(6) The data conversion rule is set so that the duty ratio in the extended N bits is within the range of the physical system or communication standard used for communication.
(7) The demodulator inputs the serial data output signal from the modulator according to any one of (1) to (6) above, and after expansion based on the data conversion rule of claim 3 from this input signal The dummy signal removing device for removing the dummy signal according to claim 3 is provided.

(8) A demodulator includes a clock extraction device that inputs the input signal and extracts a clock frequency, the dummy signal removal device that removes the dummy signal from an output signal of the clock extraction device, and a dummy signal removal device. An RZ / NRZ converter that performs RZ or NRZ conversion based on the clock frequency from the clock extractor is provided.
(9) The demodulator uses the dummy signal removal device as a Josephson junction element.
(10) The demodulator uses the dummy signal removal device as a Schmitt trigger circuit.
(11) The demodulator sets the data conversion rule so that the number of consecutive 1s included in the expanded data becomes two types.
(12) The demodulator mixes the data conversion rule with a dummy signal having a logic different from that of 0 or 1 before expansion in the expanded data.
(13) The demodulator sets the data conversion rule so that the duty ratio in the extended N bits falls within the range of the physical system or communication standard used for communication.

When the modulation method developed this time is applied to a signal with a duty ratio of 35% or less that would cause the optical pulse generator to malfunction in the non-modulated state, a signal with a duty ratio of 35% or more as shown in FIG. As with, the quantization step appears clearly, and it can be seen that the intended signal is correctly transferred.
FIG. 3 is a characteristic diagram of the average power (Optical Power) of the input optical pulse signal versus the average output voltage (Voltage) of the Josephson junction element in the arbitrary waveform generator of the present invention.
“●” in FIG. 3 indicates a duty ratio of 31.25%.
“○” indicates a duty ratio of 25.0%.
“-” Means a duty ratio of 25.00%,
Represents the characteristics of

FIG. 3 is a characteristic diagram of an embodiment in which a dummy code according to the present invention is inserted. A wide quantization step appears even in data with a duty ratio of 31.25% in which the quantization step collapse is seen in FIG. It can be seen that the data is also correctly transferred in the same manner for a 1-bit data string obtained by delta-sigma modulation of a regular signal having a duty ratio of 25% and a sine wave having the same duty ratio.
In particular, in the case indicated by “sine wave” in FIG. 3, a signal obtained by applying a low-pass filter to the output signal while fixing the optical power value proportional to the head value of the optical pulse to 14 mW is shown in FIG. 4. As shown, it is a sine wave, and it can be recognized more intuitively that the intended signal has been transmitted correctly.

4 shows the change in Josephson junction output voltage (vertical axis: Voltage) versus time applied to the low-pass filter (horizontal axis: time) when the optical power is fixed at 14 mW in the sine wave (line A) of FIG. FIG.
The characteristic diagram of FIG. 4 shows that the sine wave is reproduced and the data is transmitted correctly.

The embodiment of the present invention has the following features.
(1) Since the data conversion rule in the high-speed serial transfer is simpler than that of the existing technology, the electronic circuit necessary for the modulation is simplified, and the time required for the conversion can be shortened.
(2) When demodulating modulated data physically with an analog element, a logic circuit for demodulation is not required. When demodulating with a digital circuit, the logic is greatly simplified. In either case, it is possible to reduce the time required for data demodulation.
(3) When applied to waveform generation technology (D / A conversion), the structure of the apparatus is greatly simplified. The coding method of the present invention has a difficulty in that the frequency after the modulation becomes four times or more of the original signal, but the problem is that the original clock frequency is low like an audio signal having a sampling frequency of 44.1 kHz. There is no demerit in the case of signals. As we have shown in our experiments, the original signal operates without any problem until 10 Gbit / s.
(4) The receiving side of the digital waveform can decode any pulse pattern with a circuit that is virtually impossible to implement a demodulator of 8B / 10B encoding or 64B / 66B encoding, such as a superconducting circuit. .

The modulator of the present invention can avoid that “0” or “1” continues for 3 bits or more for an arbitrary data pattern, and the duty ratio (ratio of “1” in the data pattern) can be set. An arbitrary value, for example, close to 50% can be set.
On the demodulator side of the present invention, the dummy signal inserted on the modulator side is removed using an analog element or a digital circuit, and the original data is reproduced.
The operation margin on the receiving side is increased by adjusting the dummy signal pattern to be inserted according to the duty ratio range allowed by the circuit elements constituting the transmitter (including the modulator) and the receiver (demodulator). As a result, the probability of communication errors can be further reduced. As a result, malfunctions in high-speed serial communication such as Inter Symbol Interference phenomenon can be avoided.

It is a schematic diagram of a conventional pulse-driven Josephson arbitrary waveform generator. It is the average power (Optical Power) of the optical pulse signal to input in the conventional arbitrary waveform production | generation apparatus with respect to the average output voltage (Voltage) characteristic figure of a Josephson junction element. FIG. 5 is a characteristic diagram of an average power (Optical Power) of an input optical pulse signal versus an average output voltage (Voltage) of a Josephson junction element in the arbitrary waveform generation apparatus of the present invention. FIG. 4 is a time-varying characteristic diagram of a signal voltage obtained by applying a Josephson junction output voltage to a low-pass filter when the optical power is fixed at 14 mW in the sine wave of FIG. 3 (A line in the figure). A sine wave is reproduced, indicating that the data was transmitted correctly. It is a block diagram of the modulator of this invention. The case where the frequency supplied from the outside is equal to the clock frequency of the “sign extender” is shown. It is a block diagram of the other modulator of this invention. The case where the frequency supplied from the outside is equal to the clock frequency of the “serializer” is shown. It is a block diagram of the demodulator of this invention. The structure of a demodulator for obtaining a return-to-zero output is shown by configuring the dummy code removal device only with analog elements. It is a block diagram of the other demodulator of this invention. A circuit to obtain a non-return-to-zero output by mounting a demodulator dummy code removal device with analog elements. Indicates the type in which the clock frequency of the RZ / NRZ converter is input from the outside. It is a block diagram of the other demodulator of this invention. A circuit for implementing a non-return-to-zero output by implementing a demodulator dummy code removal device with a digital circuit is shown. This type supplies the clock frequency of the dummy code removal device from an external transmitter. It is a block diagram of the other demodulator of this invention. A circuit to obtain a non-return-to-zero output by mounting a demodulator dummy code removal device with analog elements. In this type, the clock frequency of the RZ / NRZ converter is extracted from the data modulated by the modulator. It is a block diagram of the other demodulator of this invention. A circuit for implementing a non-return-to-zero output by implementing a demodulator dummy code removal device with a digital circuit is shown. In this type, the clock frequency of the dummy code removing device is extracted from the data modulated by the modulator. It is operation | movement explanatory drawing of Example 1 of the modulator of this invention. In this example, the modulator clock is 4 times (N = 4, duty ratio 50%, margin index = 2). It is operation | movement explanatory drawing of Example 2 of the modulator of this invention. In this example, the modulator clock is 8 times (N = 8, duty ratio 50%, margin index = 4). It is operation | movement explanatory drawing of Example 3 of the modulator of this invention. In this example, the modulator clock is 8 times (N = 8, duty ratio 37.5% to 62.5%, margin index = 5). It is operation | movement explanatory drawing of Example 4 of the modulator of this invention. In this example, the modulator clock is 6 times (N = 6, duty ratio 50%, margin index = 3). It is operation | movement explanatory drawing of Example 5 of the modulator of this invention. In this example, the modulator clock is 5 times (N = 5, duty ratio 40% to 60%, margin index = 3). It is operation | movement explanatory drawing of Example 6 of the modulator of this invention. The current-voltage characteristic of a Josephson junction is shown. The horizontal axis is the average current value of the current pulse input to the Josephson junction, and the vertical axis is the average voltage value of the output voltage pulse. It is operation | movement explanatory drawing of the modulator and demodulator of this invention. It shows changes in the signal accompanying data modulation and demodulation. The block diagram of the transmission system of the high-speed serial signal of this invention is shown. The block diagram of a sign extender is shown. The block diagram of a serializer is shown. The block diagram of a frequency integer multiplier is shown. The block diagram of the 1st example of a dummy code removal apparatus is shown. The block diagram of the 2nd example of a dummy code removal apparatus is shown. The block diagram of the 3rd example of a dummy code removal apparatus is shown. The block diagram of the 4th example of a dummy code removal apparatus is shown. The structural example of DEMUX (demultiplexer) is shown. The block diagram of a clock extraction circuit is shown. The block diagram of a RZ / NRZ conversion circuit is shown.

Embodiments of the present invention will be described below.
The present invention relates to a high-speed serial signal transmission system comprising a combination of a modulator and a demodulator.
The transmission system 1 basically includes a modulator and a demodulator as components, and practically has a configuration as shown in FIG. 19, for example.
FIG. 19A shows an example of the transmission system 1 when a clock signal is not extracted from data on the demodulator side.
In FIG. 19A, based on the clock from the reference frequency generator (GPS), data obtained by code-spreading the original signal by the modulator 2 under the control of the control device 4 is serially transmitted. The demodulator 3 demodulates the original signal from the serial transmission signal based on the clock from the reference frequency generator (GPS).
FIG. 19B shows an example in which the clock signal is not extracted from the data on the demodulator side, in which the interface included in the control device in FIG. 19A and the memory included in the demodulator are clearly shown.
FIG. 19C shows an example in which a clock signal is extracted from data on the demodulator side.
In the following example 19 (a), the clock of the demodulator 3 is extracted from the received data.
The clock signal actually supplied to the modulator and demodulator is not necessarily supplied from the same device as shown in the revised version.
Also, the modulator and demodulator are installed in a remote place (for example, 100 km away) connected by an optical fiber. GPS signals (radio waves) are received by separate receivers and supplied to the modulator and demodulator, respectively. There may be an implementation that does. On the other hand, there may be a case where both the transmitter and the receiver are mounted in the same device. In this case, the reference frequency is supplied from the same instrument. In this case, a GPS signal is not always necessary.

The modulator includes a sign extender 8, a serializer 10, a frequency integer multiplier 9, and a frequency divider 11 as shown in FIG.
An example of the sign extender 8 is shown in FIG. The example of FIG. 20 shows a case of mounting by hardware, and is an example of a quadruple sign extender. The sign extender 8 in FIG. 20 holds a value of 1, a register 21a that outputs a value of 1 to dout1, a value of 0, a register 21b that outputs a value of 0 to dout4, and an input din The value X is directly output to dout2 via the branch path, and the X bar inverted by the NOT (logic inversion) circuit 22 is output to dout3.
When the function of the sign extender is implemented by software, especially in the case of a quadruple sign extender, the following method was used.
“Din [I]: = x; // Input signal x is 0 or 1, I is an integer
// Output signal dout1 [I]: = 1;
dout2 [I]: = x;
dout3 [I]: = x bar; // logic inversion dout4 [I]: = 0; "

Next, an example of the serializer (or multiplexer) 10 is shown in FIG.
The clock frequency of the serializer is N (N is an arbitrary integer) times the clock frequency of the input data. In the example of FIG. 21, N = 4. The serializer 10 in FIG. 21 is configured so that the switches are sequentially switched every time a clock is input.

An example of the frequency integer multiplier 9 is shown in FIG. The frequency integer multiplier 9 has the same function as a PLL (Phase-Locked-Loop) circuit.
The frequency integer multiplier 9 in FIG. 22 connects the VCO 23, the frequency divider 24, the counter 25b, and the comparator 26 in order to form a parallel circuit, and inputs it to the comparator 26 via the other counter 25a. The output is made from the connection point of the frequency divider 24.
“Frequency integer multiplier” is used in the same meaning as “Phase Locked Loop (PLL)”. The clock extraction circuit is a technology called “clock data recovery (CDR)”, and there are some other names for the same technology.

FIG. 5 shows a block diagram of the modulator of the present invention. The case where the frequency supplied from the outside is equal to the clock frequency of the sign extender is shown.
In the modulator 2a of FIG. 5, the sign extender inputs 8 serial data inputs and also inputs a clock frequency (fc) input, creates a 4-channel parallel output and outputs it to the serializer. The frequency integer multiplier 9 receives a clock frequency (fc) input, creates a clock frequency Nfc that is N (N is an arbitrary integer based on the data conversion rule) times the clock frequency (fc), and inputs the clock frequency Nfc to the serializer. . The serializer 10 outputs a 4-channel parallel output as serial data according to the clock frequency Nfc.
As a result, the serial data output signal of the serializer 10 is a signal obtained by dividing the serial data input signal input to the sign extender 8 by N, and is input to a demodulator (not shown).

FIG. 6 shows another block diagram of the modulator of the present invention. The case where the frequency supplied from the outside is equal to the clock frequency of the serializer is shown.
The modulator 2b shown in FIG. 6 includes a sign extender 8, a frequency integer multiplier 9, a frequency divider 11, and a serializer 10.
In the modulator 2b of FIG. 6, the frequency divider 11 inputs the clock frequency Nfc of the frequency integer multiplier 9 to create the clock frequency fc, inputs this clock frequency fc to the sign extender 8, and out of the modulator. Output.
The sign extender 8 receives serial data input and clock frequency (fc) input, creates a 4-channel parallel output, and outputs it to the serializer 10.
The serializer 10 outputs a 4-channel parallel output as serial data according to the clock frequency Nfc of the frequency integer multiplier 9.
As a result, the serial data output signal of the serializer 10 is a signal obtained by dividing the serial data input signal input to the sign extender 8 by N, and is input to a demodulator (not shown).

First, the structure of the modulators 2a and 2b will be described.
The sign extender 8 of the modulators 2a and 2b is a device that assigns an integer multiple (N) bits to a single bit of an input 1-bit data string according to a predetermined conversion rule.
The implementation method of the conversion rule will be described in detail later. The sign extender 8 has expanded (here, sign expansion means that N bits (b0, b1, b2, .., bn) are applied to a 1-bit input signal in accordance with the value of the input signal. It is transmitted to the receiver side in order at a frequency N times the clock frequency of the input signal by the serializer arranged in the subsequent stage of the sign extender. The order is b0, b1, b2, .., bn, followed by the extended bits for the next input bit.) N-bit codes are output in parallel and transferred to the serializer 10 . The serializer 10 is a device that sequentially outputs signals output in parallel from the sign extender 8 at a clock frequency of N times. The serializer 10 is sometimes called a multiplexer, and is a common device often used in an electronic circuit or the like. The multiplexer is a mechanism that outputs two or more inputs as one signal. In electronics, a multiplexer or mux means a circuit that converts a plurality of electrical signals into one signal. The physical output signal from the serializer 10 selects a physical quantity that matches the input of the modulator. If the demodulator on the receiving side is a voltage input, it outputs a voltage pulse, if it is a current input, it outputs a current pulse, and if it is an optical input, it outputs an optical pulse.
When a clock signal having the same clock frequency as that of the serial data input signal is input from the outside of the modulators 2a and 2b, the clock frequency fc of the input clock signal is N times as high as the frequency integer multiplier 9 as shown in FIG. And is input to the serializer 10.
On the other hand, when a clock frequency Nfc that is N times the serial data input signal is supplied from the outside of the modulators 2a and 2b, the clock frequency Nfc is directly input to the serializer and is converted to a 1 / N frequency by the frequency divider 11. Is output to the outside.

The general operation of the sign extender will be described in detail.
Let F1 be the clock frequency of the original data you want to send. In the modulator 2 on the transmission side, this frequency is set to N times (N is an integer of 3 or more) based on the data conversion rule.
Next, 1-bit data to be transmitted is sign-extended to N-bit data. At this time, the code extension rate is N.
For example, when the code extension rate is 4 (N = 4), 4-bit data is assigned to 1-bit data to be transmitted (when the original data is “0”, “0000”, the original data is “ In the case of “1”, “1111” is assigned). The N-bit data after expansion is mixed with a dummy signal having a different logic from “0” or “1” before modulation. When the original data is “0”, the dummy signal is inserted by inserting “1” as a dummy signal in the signal string expanded to N bits and extending the original data “1” to N bits. For example, “0” is inserted. In either case, adjustment is made so that the duty ratio in the N bits after modulation falls within the range of the physical system or communication standard used for communication. Also, the time t ₀ when “1” as a dummy signal inserted into the original data “0” continues is shorter than the time t1 when “1” continues in the modulated data of the original data “1”. To do. Hereinafter, t ₁ / t ₀ is referred to as “margin index”. Data extended to N times the length is transmitted to the receiving side at a clock frequency N times that of the original data.

  Regarding the determination of N, it is most natural to select a multiple of 4 in consideration of use in a digital circuit. Generally, when N is an even number, there is always a modulation method (dummy signal insertion method) for setting the duty ratio to 50% for an arbitrary data pattern to be transmitted. When N is an odd number, the duty ratio is a value between 40% and 60% in the worst case (when N = 5). When N is an odd number, the upper and lower limits of the duty ratio can be made asymptotic to 50% as N increases (N = 7: 42.9% to 57.1%, N = 9: 44.4%) ~ 55.6%). In the case of N = 5 or more, there are a plurality of conversion rules other than the above, which are adapted to the duty ratio physically permitted by a device related to data transmission / reception or the range of the duty ratio determined by the communication standard.

  The demodulator on the receiving side performs the inverse conversion of the conversion described above. When the demodulator is mounted with a digital circuit, the N-bit data pattern assigned to “0” and “1” before modulation is stored in a register to determine whether it corresponds to “0” or “1”. If an analog element of the type described below is used for the first stage of the demodulator, the demodulator can be greatly simplified. The specification that the analog element satisfies is that N is obtained by outputting “0” for “1” as a dummy signal inserted with respect to the original “0” before modulation, and modulating the original “1” before modulation. It is an element that outputs “1” for continuous “1” included in bit data and always outputs “0” for input “0”.

  Data conversion rules in the modulator are limited to conversion rules in which the number of consecutive “1” s in the output data (pulse area) becomes two types. For example, when a conversion rule that converts “0” to “1010” and “1” to “1100” is applied to an arbitrary serial data string, the output pulse waveform of the modulator is one isolated pulse, 2 Two outputs of consecutive pulses are obtained. This conversion rule is therefore compatible. On the other hand, when a conversion rule that converts “0” to “0101” and “1” to “1100” is applied to an arbitrary serial data string, the output pulse waveform of the modulator is an isolated pulse, Three outputs are obtained: two consecutive pulses and three consecutive pulses. Therefore, this conversion rule is incompatible. Similarly, when a conversion rule that converts “0” to “0001” and “1” to “1110” is applied to an arbitrary serial data string, the output pulse waveform of the modulator is an isolated pulse, Three outputs are obtained: three consecutive pulses and four consecutive pulses. Therefore, this conversion rule is also irrelevant.

When the code expansion rate, margin index, and duty ratio worst value (duty ratio of the output waveform of the modulator when the input values are all “0” and all “1”) match in the two types of conversion rules. A bit shift operation (cyclically shifts the conversion bit string to the left or right), a replacement operation of adjacent bits, a bit inversion operation, an operation that repeats them, or an operation that combines them. Is applied, the two sets of conversion rules are considered to be essentially equivalent conversion rules. For example, the conversion rule that associates “0” with “0010” and “1” with “1110” is “0”. If the second and third bits are interchanged, “0” is changed to “0100”, “ It matches the conversion rule that associates “1” with “1110”. The two sets of conversion rules have the same sign expansion rate, margin index, and worst duty ratio. Therefore, the two sets of conversion rules can be regarded as equivalent conversion rules. As another example, if a bit inversion operation is applied to both of the conversion rules that correspond “0” to “0101” and “1” to “0011”, “0” becomes “1010” and “1” becomes “10”, respectively. The conversion rule corresponds to 1100 ″. The expansion rate, the margin index, and the worst duty ratio are the same for both codes. Therefore, also in this case, the two sets of conversion rules can be regarded as equivalent conversion rules.
The implementation of the conversion rule in the sign extender will be described in more detail with five examples.
Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 12 is a diagram for explaining the operation of the first embodiment of the modulator of the present invention. In this example, the modulator clock is 4 times (N = 4, duty ratio 50%, margin index = 2).
Based on FIG. 12, the conversion rule in the modulator will be described for the case where N = 4, which is the most natural as the clock magnification (N) on the modulator side. In the case of N = 4, when a conversion rule is applied in which “0” corresponds to “1010” and “1” corresponds to “1100”, the duty ratio of the output signal is always 50% and “1” in the output data. There are only two consecutive numbers of 1 or 2, and therefore the margin index is always 2 (FIG. 12). When the input / output relationship of this conversion rule is logically expressed, (output first bit) = (always 1), (output second bit) = (same value as input data), (output third bit) = (Value obtained by logically inverting the input data), (the fourth bit of the output) = (always 0). When N = 4, conversion rules other than the above do not uniquely determine the number of consecutive “1” s in the output signal depending on the pattern of the input signal, or the duty ratio of the output pattern deviates significantly from 50%. There is a possibility that data is not logically transmitted correctly.

FIG. 13 is a diagram for explaining the operation of the second embodiment of the modulator of the present invention. In this example, the modulator clock is 8 times (N = 8, duty ratio 50%, margin index = 4). FIG. 13A shows original data before modulation, and FIG. 13B shows data after modulation.
As shown in FIG. 13, when N = 8 is selected as the clock magnification (N) on the modulator side, the margin index can be increased compared to the case where N = 4. When “10101010” is associated with “0” and “11110000” is associated with “1”, the duty ratio of the output signal is always 50%, and the number of consecutive “1” s in the output data is 1. Alternatively, there are only two types of 4, and therefore the margin index is always 4 (FIG. 13).

FIG. 14 is a diagram for explaining the operation of the third embodiment of the modulator according to the present invention. In this example, the modulator clock is 8 times (N = 8, duty ratio 37.5% to 62.5%, margin index = 5). FIG. 14A shows the original data before modulation, and FIG. 14B shows the data after modulation.
In FIG. 14, when N = 8 is selected as the clock multiplication factor (N) on the modulator side, when the duty ratio allowed by the device related to transmission / reception is large (for example, a range of 35% to 65% is allowed), The margin index can be further increased as compared with the second embodiment. When “10101000” is associated with “0” and “11111000” is associated with “1”, the duty ratio of the output signal is 37.5% to 62.5%, and “1” in the output data. There are only two consecutive numbers of 1 or 5, and therefore the margin index is always 5 (FIG. 14). In the case of this modulation rule, the duty ratio is 62.5% which is the worst value when the input data is all “1”.

FIG. 15 is a diagram for explaining the operation of the modulator according to the fourth embodiment of the present invention. In this example, the modulator clock is 6 times (N = 6, duty ratio 50%, margin index = 3). FIG. 15A shows original data before modulation, and FIG. 15B shows data after modulation.
In FIG. 15, it is also possible to select a value that is not a multiple of 4, for example, N = 6, as the clock magnification (N) on the modulator side. In this case as well, the margin index can be increased compared to the case of the first embodiment (N = 4) as in the second and third embodiments. When “101010” is associated with “0” and “111000” is associated with “1”, the duty ratio of the output signal is always 50%, and the number of consecutive “1” s in the output data is 1. Alternatively, there are only two types of 3, so the margin index is always 4 (FIG. 15).

FIG. 16 is a diagram for explaining the operation of the fifth embodiment of the modulator of the present invention. In this example, the modulator clock is 5 times (N = 5, duty ratio 40% to 60%, margin index = 3). FIG. 16A shows original data before modulation, and FIG. 16B shows data after modulation.
In FIG. 16, it is also possible to select an odd number, for example, N = 5, as the clock magnification (N) on the modulator side. In this case as well, the margin index can be increased compared to the case of the first embodiment (N = 4) as in the second and third embodiments. When “01010” is associated with “0” and “11100” is associated with “1”, the duty ratio of the output signal is always 40% to 60%, and “1” continues in the output data. There are only two types, 1 or 3, so the margin index is always 3 (FIG. 16).
Next, the receiver will be described. The receiver is a circuit composed of any one of a digital circuit, an analog circuit, and an analog / digital mixed circuit, and an output is a digital signal. When the demodulator is composed of a digital circuit, the output can be in either a return-to-zero (RZ) format or a non-return-to-zero (NRZ) format (corresponding to FIG. 8). When the modulator is composed only of an analog circuit, the output is in RZ format (corresponding to FIG. 6). If the output is to be in the NRZ format, an RZ / NRZ converter is disposed in the subsequent stage (corresponding to FIG. 8). RZ / NRZ converters are devices that are commonly used in electronic circuits. The dummy code removing device in FIG. 7 is an analog circuit, and it is not necessary to input a synchronization signal from the outside.

Examples of the dummy code removing device are shown in FIGS. The dummy code removing device shown in FIG. 23 is composed of a Josephson junction element. FIG. 23A shows that when a current pulse is input to a series of Josephson element arrays (indicated by “X” in the figure) connected in series, the current pulse passes through the high-frequency transmission line and is input to the Josephson junction, and is input to each Josephson element. Generate an output voltage and output the output voltage to the voltage reading terminal. Josephson junctions connect a plurality of junctions in series to increase the output voltage.
FIG. 23B shows the structure of the Josephson junction element. The superconducting electrodes S, S on both sides are configured such that the central normal conductor or insulator thin film X is short-circuited with a normal metal, or the laminate X composed of an insulator / normal metal / insulator is sandwiched. .
The dummy code removing device 12b of FIG. 24 shows a case where it is mounted with an optical detector.
FIG. 24A shows an example of a dummy code removing device 12b using an MSM type photodetector, which is configured such that a central insulator or semiconductor S (Semiconductor) is sandwiched between metal electrodes M on both sides. The response speed of the distance d between the insulators or the semiconductors between the metal electrodes M on both sides decreases as the distance d increases. When an insulator or semiconductor portion is irradiated with light, a photocurrent is generated.
FIG. 24B shows an example of a photodiode as a general electronic circuit component, and the response speed depends on the electrode interval and the carrier mobility.

Although a general photodiode has been exemplified as the photodetector, there are actually photodetectors that are not diodes, such as MSM type photodetectors. In the present invention, any optical detector may be used as long as it does not respond to a dummy pulse with a narrow response speed and has a response speed that responds to a wide signal to be actually transmitted.
FIG. 25 shows an example of a dummy code removing device 12c mounted with a general Schmitt trigger circuit element.
FIG. 26 shows an example of the dummy code removing device 12d in the case where the code extension rate N = 4, which is an example implemented by a digital circuit.
In FIG. 26, four input signals din are output in synchronization with the clock signal (clock) and input to four XOR (exclusive OR) circuits 29, respectively. On the other hand, the four outputs of the register 21C according to the shift rule for “1” are input to the four XOR (exclusive OR) circuits 29, respectively. The four XOR (exclusive OR) circuits 29 input their respective outputs in series to the next four NOT (logic negation) circuits 22. The outputs of the four NOT (logical negation) circuits 22 are input to one AND (logical product) circuit 30. The output of this one AND (logical product) circuit 30 is output as dout.

FIG. 27 shows a configuration example of the DEMUX in FIG.
The input signal din is sequentially switched and connected by a toggle switch mechanism of a DEMU (demultiplexer) X28 in synchronization with the clock signal (clock), and is output in order to dout1, dout2, dout3 and dout4.
FIG. 29 shows a configuration example of the RZ / NRZ conversion circuit 13.
FIG. 29A shows an example in the case of inputting a signal of a superconducting device, a photodetector output, and a Schmitt trigger circuit element. An RZ format data input din is input to a D-FF (D-flip-flop) circuit 33 serving as the RZ / NRZ conversion circuit 13 based on a signal that is always high, and an NRZ format data output dout is output.
FIG. 29B shows an example in which an RZ format signal of a normal logic circuit is input.
An RZ-format data input din is input to a D-FF (D-flip-flop) circuit 33 serving as the RZ / NRZ conversion circuit 13 based on an output of an edge detector 34 that detects an edge in synchronization with a clock signal. NRZ format data output dout is output.
Note that the illustrated examples from FIG. 20 are examples of mounting, and other mounting is possible, and these components can also be used in general commercial products.

8 and 9, it is necessary to supply a clock frequency from the outside to the modulator in order to extract output data. In the data to be transmitted, the number of consecutive “1” s or “0” s can be limited to a small value, so that the clock frequency can be extracted from the data itself. FIG. 10 shows a circuit that reads a clock from a signal transmitted from a modulator and drives an RZ / NRZ converter with the clock signal. FIG. 11 shows a circuit that reads a clock from data and removes a dummy code by a digital circuit using the clock.
FIG. 28 shows the configuration of the clock extraction circuit 14 using the clock data recovery circuit.
FIG. 28A shows an example in which the clock extraction circuit 14 is configured by a PLL (Phase-Locked-Loop) circuit 31.
In FIG. 28B, the input signal din is input to one of the NAND (negative AND) circuits 32, the output of the NAND (negative AND) circuit 32 is output as the output signal dout, and the NOT (logical NOT) circuit 22. To the other of the NAND (Negative AND) circuit 32.

On the other hand, the demodulator is configured by combining the dummy code removing device 12, the RZ / NRZ converting device 13, and the clock extracting device 14, and there are variations as shown in FIGS.
FIG. 7 is a block diagram of the demodulator of the present invention. The structure of a demodulator for obtaining a return-to-zero output is shown by configuring the dummy code removal device only with analog elements.
FIG. 8 is a block diagram of another demodulator of the present invention. A circuit to obtain a non-return-to-zero output by mounting a demodulator dummy code removal device with analog elements. Indicates the type in which the clock frequency of the RZ / NRZ converter is input from the outside.
FIG. 9 is a block diagram of another demodulator of the present invention. A circuit for implementing a non-return-to-zero output by implementing a demodulator dummy code removal device with a digital circuit is shown. This type supplies the clock frequency of the dummy code removal device from an external transmitter.

FIG. 10 is a configuration diagram of another demodulator of the present invention. A circuit to obtain a non-return-to-zero output by mounting a demodulator dummy code removal device with analog elements. In this type, the clock frequency of the RZ / NRZ converter is extracted from the data modulated by the modulator.
FIG. 11 is a block diagram of another demodulator of the present invention. A circuit for implementing a non-return-to-zero output by implementing a demodulator dummy code removal device with a digital circuit is shown. In this type, the clock frequency of the dummy code removing device is extracted from the data modulated by the modulator.
The demodulator 3a shown in FIG. 7 includes a dummy code removing device 12 made of, for example, an element such as a Josephson junction element, inputs a serial data input signal from the modulator, and outputs a serial data output signal (RZ format). To do. The demodulator 3a does not require the clock frequency fc or Nfc.

The demodulator 3b shown in FIG. 8 includes a dummy code removing device 12 and an RZ / NRZ converter 13 connected in series. The dummy code removing device 12 inputs a serial data input signal and outputs a serial data output signal (RZ format). The RZ / NRZ converter 13 receives the serial data output signal (RZ format) and outputs a serial data output signal (NRZ format) based on the clock frequency fc input.
The demodulator 3c in FIG. 9 includes a frequency integer multiplier 9 and a dummy code removing device 12. The dummy code removing device 12 inputs a serial data output signal from the modulator, and converts the clock frequency fc to the frequency integer multiplier 9. The dummy code is removed based on the clock frequency Nfc multiplied by N, and a serial data output signal (NRZ format) is output.

The demodulator 3d shown in FIG. 10 includes a clock extracting device 14, a dummy code removing device 12, and an RZ / NRZ converter 13 connected in series. The serial data is output from the serial data output signal from the modulator by the clock extracting circuit. In addition to the output signal, the clock frequency fc is separated and extracted. The dummy code removing device 12 outputs a serial data output (RZ format) signal from which the dummy code is removed from the “serial data output signal from the modulator” which is the output of the clock extracting circuit 14. The RZ / NRZ converter 13 performs RZ / NRZ conversion on the serial data output (RZ format) signal, which is the output of the dummy code removing device 12, at the clock frequency fc from the clock extraction circuit 14, and outputs a serial data output signal (NRZ format). ) Is output.
A demodulator 3e in FIG. 11 is formed by connecting a clock extracting device 14 and a dummy code removing device 12 in series. The clock extracting device 14 converts a serial data output signal from a modulator into a clock frequency fc in addition to the serial data output signal. Is extracted. The dummy code removal device 12 removes the dummy code at the clock frequency fc from the clock extraction circuit 14 from the “serial data output signal from the modulator” which is the output of the clock extraction circuit 14 and outputs a serial data output (NRZ format) signal. Is output.

When the demodulator on the receiving side is implemented with an analog circuit, “0” is output for the dummy signal “1” inserted for duty ratio adjustment, and the dummy signal corresponding to the original data “1” is output. An element that outputs “1” is used in the first stage for “1” that is longer than the signal. As such an analog circuit, an element having a waveform shaping function or an element having a response speed that does not respond to a narrow pulse but responds to a wide pulse is used. The output waveform of the analog element is obtained by converting original data to be transmitted before passing through the modulator into RZ. If this RZ signal is converted into an NRZ signal, an original signal completely before modulation can be obtained.
FIG. 18 shows a summary of the case where the original data to be transmitted is encoded by the modulator and returned to the original signal by the demodulator in the case of the code extension rate 4.
FIG. 18 is an explanatory diagram of the operation of the modulator and demodulator of the present invention. It shows changes in the signal accompanying data modulation and demodulation.

18 (a) is the original data, FIG. 18 (b) is the data after modulation, FIG. 18 (c) is the data after double tone, FIG. 18 (d) is the data after double tone, and FIG. 18 (e). Indicates the original data.
The original data (11010) shown in FIG. 18 (a) is converted into data in which three or more “1” s or “0” s do not continue as shown in FIG. 18 (b) by a sign extender. In FIG. 18B, there are two types of pulses, that is, one isolated pulse (dummy pulse) and two pulses in succession for two areas. The dummy pulse is removed by the demodulator and becomes a waveform as shown in FIG. This signal is equivalent to that shown in FIG. 18 (d), which is equivalent to the result of RZ conversion of FIG. 18 (a). When NRZ format data is required in a circuit subsequent to the demodulator, NRZ format data (completely the same as the original data) as shown in FIG. 18E can be obtained with a simple circuit.

Specifically, it was implemented with a superconducting device called a Josephson junction that operates at cryogenic temperatures. This receiving element is not a logic device but an analog device. Josephson junctions can be regarded as a kind of pulse shaper. When a current pulse is input to the Josephson junction, the integral value of the output voltage pulse of the Josephson junction is always strictly shaped to an integral multiple of (h / 2e) according to the magnitude of the time integration of the input current pulse. There are features (FIG. 17).
FIG. 17 is a diagram for explaining the operation of Embodiment 6 of the modulator of the present invention. The current-voltage characteristic of a Josephson junction is shown. The horizontal axis is the average current value of the current pulse input to the Josephson junction, and the vertical axis is the average voltage value of the output voltage pulse.
Here, h and e are the Planck constant and the elementary charge, respectively. When the amplitude of the input current pulse is adjusted and one isolated current pulse is input as shown in FIG. 17 (b), the area of the output voltage pulse becomes zero, and the area is doubled as shown in FIG. 17 (c). Can be adjusted so that the magnitude of the output voltage pulse is (h / 2e). When the input is zero as shown in FIG. 17A, the output is naturally zero. Using this property, a voltage pulse with an integral value (h / 2e) is output for a current pulse corresponding to a pulse pattern of “1100” (this corresponds to “1” in the pulse pattern before modulation). ), The integrated value of the output voltage can be made to correspond to zero (corresponding to “0” in the pulse pattern before modulation) for the current pulse corresponding to the pulse pattern “1010”. (This was confirmed by experiments. The results are as described in the section “Problems to be solved by the invention”)

  A general semiconductor device having a waveform shaping function can be used instead of the Josephson junction in the example of the sixth embodiment. As a semiconductor device having a waveform shaping function, there is a Schmitt trigger element. The Schmitt trigger element is a logical device that outputs “1” for input values exceeding a certain threshold and outputs “0” for input values below that, but has a hysteresis and is somewhat slow in response speed. Therefore, it is not used as a component of the synchronization circuit. Conversely, this property may be used to remove pulse noise in serial data transfer. Specifically, it may be used to prevent chattering. It is possible to convert “1010” to an output waveform of “0000” by removing a short pulse intentionally mixed in data transmitted at high speed with a device having a waveform shaping function such as a Schmitt trigger element. it can. On the other hand, when “1100” corresponding to “1” in the original data is input to the Schmitt trigger circuit, the output becomes “1100”. Finally, if it is converted to an NRZ signal, the original data can be completely reproduced.

  In place of the Josephson junction in the example of the sixth embodiment, a general photodetector having a waveform shaping function may be used. Specifically, when a narrow dummy pulse is input, a sufficient output current pulse cannot be obtained due to the slow response speed, and when a non-dummy pulse with a long pulse width is input, the pulse width is sufficiently long. Therefore, an optical detector (photodiode) is used that has an output current that exceeds a certain threshold. Alternatively, depending on the response speed of the optical detector, a dummy code having a narrow width that cannot be responded by the optical detector when the dummy code is inserted may be added to the original signal to be transmitted.

  The outputs obtained in the sixth, seventh, and eighth embodiments are all in the return-to-zero format. However, if data in the non-return-to-zero format is required, the return code is returned to the subsequent stage of the dummy code removing device. A device (RZ / NRZ converter) for converting a -Zero format signal into a Non-Return-to-Zero format signal may be arranged. Accordingly, the demodulator is provided with a port for inputting a clock signal having the same frequency as that of the original signal, and the clock frequency is supplied to the RZ / NRZ converter.

  When the demodulator on the receiving side is implemented with only a digital circuit, the data sent from the transmitting side is stored in a register every N bits in order from the start bit, and the value matches the conversion rule “0” Outputs “0”, otherwise it outputs “1”. The output of the demodulator is logically the same as the original data before modulation, and the clock rate is also the same.

DESCRIPTION OF SYMBOLS 1 High-speed serial signal transmission system 2 Modulator 3 Demodulator 8 Sign extender 9 Frequency integer multiplier 10 Serializer 11 Frequency divider 12 Dummy code removal device 13 RZ / NRZ converter 14 Clock extraction device 21 Register 22 NOT (logic Denial) Circuit 23 VCO (Voltage Controlled Oscillator)
24 Frequency Divider 25 Counter 26 Comparator 27 Schmitt Trigger Element 28 DEMUX (Demultiplexer)
29 XOR (Exclusive OR) circuit 30 AND (Logical product) circuit 31 PLL (Phase-Locked-Loop) circuit 32 NAND (Negative logical product) circuit 33 D-FF (D-flip flop) circuit 34 Edge Detection circuit

Claims (13)

A digital data string input signal transferred in a serial data transfer system is an N bit after extending a bit of an integer N multiple of 3 or more to one bit of the 1-bit data string in accordance with a predetermined data conversion rule Are assigned so that dummy signals having different logics are mixed with respect to 0 or 1 before extension, and the assigned extended N-bit code is formed in parallel, and the N-bit parallel code is The digital data is sequentially transmitted at a clock frequency N times the clock frequency of the digital data, and the N-bit data pattern assigned to 0 and 1 before expansion based on the predetermined conversion rule is stored on the receiving side. The N-bit data pattern of the data string signal received in order is inversely converted to 0 and 1 before the extension based on the predetermined conversion rule. Method of transmitting high-speed serial signal, wherein the door. 2. The high-speed serial signal transmission method according to claim 1, wherein the data conversion rule is such that the number of consecutive 1s included in the expanded data is two. The same clock frequency as that of the serial data input signal is input, and one bit of the 1-bit data string of the serial data input signal is expanded in accordance with a predetermined data conversion rule. A sign extender for assigning a dummy signal having a different logic to 0 or 1 before expansion to the subsequent N-bit data, and outputting the assigned extended N-bit code in parallel; and the serial A clock frequency that is the same as the clock frequency of the data input signal is input, is converted to a frequency that is a multiple of an integer N that is 3 or more of this clock frequency, and is output; The serially output signals are output in parallel based on the N times clock frequency from the frequency integer multiplier. Modulator characterized by comprising a serializer for outputting as a signal. 4. The modulator according to claim 3, wherein the data conversion rule is such that the number of consecutive 1s included in the expanded data is two types. 4. The modulator according to claim 3, wherein the data conversion rule is such that a dummy signal having a logic different from 0 or 1 before expansion is mixed in the expanded data. 4. The modulator according to claim 3, wherein the data conversion rule is such that a duty ratio in N bits after expansion falls within a range of a physical system or a communication standard used for communication. A serial data output signal from the modulator according to any one of claims 1 to 6 is input, and the expanded dummy signal according to claim 3 is removed from the input signal based on the data conversion rule of claim 3. A demodulator having a dummy signal removal device. A clock extraction device that inputs the input signal and extracts a clock frequency, the dummy signal removal device that removes the dummy signal from an output signal of the clock extraction device, and an output of the dummy signal removal device from the clock extraction device 8. The demodulator according to claim 7, further comprising an RZ / NRZ conversion device that performs RZ or NRZ conversion based on the clock frequency of the RZ / NRZ. 8. The demodulator according to claim 7, wherein the dummy signal removing device is a Josephson junction element. 8. The demodulator according to claim 7, wherein the dummy signal removing device is a Schmitt trigger circuit. The demodulator according to any one of claims 7 to 10, wherein the data conversion rule is such that the number of consecutive 1s included in the expanded data is two types. The demodulation according to any one of claims 7 to 10, wherein a dummy signal having a logic different from 0 or 1 before expansion is mixed in the data after expansion according to the data conversion rule. vessel. The demodulation according to any one of claims 7 to 10, wherein the data conversion rule is such that a duty ratio in N bits after expansion falls within a range of a physical system or a communication standard used for communication. vessel.

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