CN103513231A - Chirp signal generating method for three-dimensional imaging microwave altimeter and chirp signal generator - Google Patents

Abstract

The invention provides a chirp signal generating method for a three-dimensional imaging microwave altimeter and a chirp signal generator, wherein the signal generator is used for generating a direct digital frequency synthesis-direct waveform storage dual-mode broadband digital chirp signal. The signal generator successively comprises a waveform data generation unit, a dual-channel digital-to-analog conversion unit, and a quadrature modulation unit, wherein the three units are connected in series. To be specific, the waveform data generation unit that is based on an FPGA chip is used for generating waveform data by using a direct digital frequency synthesis method or a direct waveform storage method and dividing the generated waveform data into two paths of quadrature waveform data for outputting. The dual-channel digital-to-analog conversion unit based on a dual-channel digital-to-analog converter is used for receiving the waveform data that are outputted by the waveform data generation unit, carrying out digital-to-analog conversion on the data and generating two paths of baseband signals for outputting. And the quadrature modulation unit is used for receiving the two paths of baseband signals outputted by the dual-channel digital-to-analog conversion unit, carrying out quadrature modulation, and generating a chirp signal applied to a three-dimensional imaging microwave altimeter.

Description

A kind of Chirp signal generating method and generator for three-dimensional imaging microwave altimeter

Technical field

The present invention relates to hardware design and the Software for Design field of Radar Signal Generator, be particularly related to the high performance digital Chirp signal generating method that is applicable to three-dimensional imaging microwave altimeter system in broadband, can according to parameter request, automatically generate waveform simultaneously, or read out pre-stored data and generate waveform, the invention provides a kind of Chirp signal generating method and generator for three-dimensional imaging microwave altimeter.

Background technology

The Chirp signal that produces broadband has very important significance to improving the range resolution of three-dimensional imaging microwave altimeter system.Digital form is programmable, and waveform parameter configuration is very convenient, and circuit flexibly and be convenient to integratedly, is widely used.Numeral chirp technology mainly contains Direct Digital synthesis method of the frequency and the two kinds of basic implementations of Direct Digital Waveform synthetic method based on waveform storage direct-reading based on phase accumulator.They have good performance on bandwidth, frequency resolution, frequency switching time, phase continuity.Direct Digital synthesis method of the frequency was suggested from 1971, had had so far the development of nearly 40 years, along with developing rapidly of microelectric technique, in waveform generation field, was widely used.Development along with high-speed large capacity memory part, direct waveform memory technology progresses into practical, and it can realize various complicated wave forms easily, can also adopt pre-distortion technology to improve waveform simultaneously, improve system performance, be widely used in producing the occasion of non-rule waveform.

The develop rapidly of field programmable gate array (FPGA) device, the circuit that makes to utilize high performance FPGA device to meet oneself needs in conjunction with other chip design becomes good thinking.The form that no matter generates phase accumulator and table look-up in Direct Digital Frequency Synthesizer Technology, or frequency control word is provided to special-purpose directly frequency synthesis chip, or directly in waveform storage, data are being read DAC from storage chip, FPGA has brought into play very large effect.Along with the develop rapidly of chip technology, digital form produces Chirp signal huge growing space, and it is higher towards frequency of operation, and resolution is higher, and stability is better, and bandwidth can increase, and clutter noise more and more less future development.The design's hardware aspect has been contained quadrature modulation circuit, clock generating and distribution system and power distribution system, and software aspect comprises different running software process flow diagram under DDFS and two kinds of patterns of DDWS, the service condition of FPGA resource and simulation result.

Summary of the invention

The object of the invention is to, for overcoming the problems referred to above of prior art, thereby proposed a kind of Chirp signal generating method and generator for three-dimensional imaging microwave altimeter.

Design of the present invention can realize direct frequency combining method and the digital Chirp signal source that directly the high performance bandwidth of waveform storage means is 220MHz simultaneously, comprises its hard ware & soft ware design.

To achieve these goals, the invention provides a kind of Chirp signal generator for three-dimensional imaging microwave altimeter, be used to three-dimensional imaging microwave altimeter system to produce Direct Digital frequency synthesis and store double mode wideband digital chirp signal with direct waveform, it is characterized in that, described signal generator comprises successively and to be connected in series:

Wave data generation unit ，Gai unit is based on fpga chip, for adopt direct frequency combining method or directly waveform storage means generate Wave data, and the Wave data that the Wave data of generation is divided into two-way quadrature is exported;

Binary channels D/A conversion unit ，Gai unit is based on a slice binary channels digital to analog converter, and this digital to analog converter, for receiving the Wave data from the output of Wave data generation unit, is carried out digital-to-analogue conversion, produces the two-way baseband signal line output of going forward side by side; With

Orthogonal modulation unit, for receiving the two-way baseband signal of described binary channels D/A conversion unit output and carrying out orthogonal modulation, produces the Chirp signal for three-dimensional imaging microwave altimeter.

In technique scheme, described Wave data generation unit further comprises:

Be used to described fpga chip to provide the clock generating of clock to distribute subelement and clock line;

Be used to described fpga chip that the power distribution subelement of power supply is provided; With

The Wave data that is used to described fpga chip to produce is stored, or will store the storing sub-units of the required Wave data of this FPGA at the initial phase of described fpga chip work.

In technique scheme, described storing sub-units further comprises: two DDR2SDRAM chips and a slice Dataflash chip, and wherein DDR2 provides real-time storage fast, and Dataflash provides jumbo low speed storage, power down is obliterated data not; If fpga chip is operated under direct waveform memory module, it is read into Wave data FIFO wherein and goes from Dataflash, if data volume is larger, data is read in DDR2SDRAM and is gone.

In technique scheme, the clock that described clock generating distributes subelement specifically to adopt CDCM61004 clock chip to produce; And the clock producing offers fpga chip by LVDS clock line, fpga chip produces and has the clock of certain time-delay and offer binary channels D/A conversion unit by LVDS clock line by DCM module; And that the clock between fpga chip and DDR2 is used is difference SSTL18.

In technique scheme, between described binary channels D/A conversion unit and orthogonal modulation unit, be also connected with a passive low ventilating filter.Described passive low ventilating filter is π type passive low ventilating filter.

In technique scheme, described fpga chip further comprises:

Direct frequency synthesis module, for three-dimensional imaging microwave altimeter system in orbit during, according to length and the spectrum width by uploading frequency word and the frequency step value change waveform of command, and then generation Wave data, and this direct frequency synthesis module is produced by the IP kernel of Virtex5 series; With

Directly waveform memory module, for when three-dimensional imaging microwave altimeter system integration and test and initial stage in orbit, adopts this module to receive and inputs Wave data wherein by outer computer.

In technique scheme, described binary channels D/A conversion unit specifically adopts AD9779A, and described orthogonal modulation unit adopts the quadrature modulator of ADL5371 model;

Wherein, the binary channels D/A conversion unit of above-mentioned model and orthogonal modulation unit can carry out " seamless interfacing ".

Based on above-mentioned signal generator the present invention, also provide a kind of Chirp signal generating method for three-dimensional imaging microwave altimeter, the method is used to three-dimensional imaging microwave altimeter system that its required Chirp signal is provided, and described method comprises:

When three-dimensional imaging microwave altimeter system integration and test and initial stage in orbit, based on fpga chip, adopt the mode of waveform storage to produce Wave data;

When three-dimensional imaging microwave altimeter system is in orbit in process, based on fpga chip, by the method for direct frequency synthesis, obtain optimum pulse width and the spectrum width of system, and by upper teletype command, optimum pulse width and waveform parameter corresponding to spectrum width are modified, produce required Wave data;

The Wave data that one of above-mentioned two kinds of modes are produced adopts a slice binary channels digital to analog converter to carry out digital-to-analog conversion and adopt quadrature modulator to carry out orthogonal modulation, the final Chirp signal for three-dimensional imaging microwave altimeter of output;

Above-mentioned optimum pulse is wide can select 10us, and the wide selection of this optimum pulse is according to as follows:

(1) restriction of PRF, defines maximum pulse width;

(2) restriction of data transfer rate, if too wide, data transfer rate is too high;

(3) time, with long-pending restriction, this determines the pulse width after final compression;

(4) utilize the wide and large bandwidth of long pulse to obtain large time band long-pending, thereby obtain high impulse compressibility, from this angle, define minimum pulse width; Too little pulsewidth is unfavorable for the transmission of microwave energy, is difficult to obtain large signal to noise ratio (S/N ratio);

In a word, can under the comprehensive constraint of above several factors, select best pulse wide, but because constraint is not very strict, so just selected the integer of individual 10us; As for described spectrum width: directly respective distances is to resolution, deltaR=c/2B.

Described method also comprises: a certain control port of monitoring FPGA is known the step of the producing method of Wave data, and this step is specially:

When being high level, port is operated in direct frequency synthesis pattern, automatically toward binary channels digital to analog converter output data;

When port is low level, be waveform memory module, wait outer computer to start toward binary channels digital to analog converter output data after fpga chip is downloaded waveform;

Wherein, when under direct frequency synthesis pattern, user sets frequency control word and initial phase, just can obtain corresponding Chirp signal;

When under waveform memory module pattern, Wave data is calculated by PC, by parallel port simulative serial port, via FPGA, downloads in dataflash and preserves; After fpga chip powers on, first binary channels digital to analog converter is configured, also serial ports is monitored simultaneously, if host computer has the request of downloading data, carry out down operation, if there is no request, sense data from dataflash, be stored in the FIFO opening in fpga chip, if data length is longer, data are stored in DDR2, after initialization, from FIFO or DDR2, read data high-speed, be defeated by binary channels digital to analog converter.

Compared with prior art, technical advantage of the present invention is:

The signal generating portion that the present invention is directed to three-dimensional imaging microwave altimeter is improved, and former DDS adopts waveform storage mode, spaceborne, is not easy to produce as required waveform; Original scheme is that the Data-Link in remote-control romote-sensing link is via satellite uploaded waveform, the design of hardware and software build-up of pressure of the data transfer rate of its generation to the 1553B of satellite communication link and system; The mode that increases direct frequency synthesis in new design, the length and the spectrum width that change waveform only need upload frequencies word and frequency step value, and its instruction of uploading only needs 42 bit.And be enough to support while uploading Wave data when satellite communication link bandwidth and data transfer rate, we can say that the waveform after pre-distortion uploads, can effectively improve waveform, improve the index performance transmitting, signal that can be follow-up is processed provides a good stable signal source.Therefore, Direct Digital Frequency Synthesizer Technology and waveform memory technology complement each other and complement each other, and can select flexibly according to experimental result or technical requirement.

Accompanying drawing explanation

The hardware block diagram of the direct frequency synthesis pattern that Fig. 1 relates in designing for the present invention;

The hardware block diagram of the direct waveform memory module that Fig. 2 relates in designing for the present invention;

Fig. 3 is the hardware system block diagram of employing of the present invention;

Fig. 4 is the Software for Design process flow diagram under direct waveform memory module;

Fig. 5 is I, Q road and the details thereof of the output base band of direct frequency synthesis pattern;

Fig. 6 is I, Q road and the details thereof of the output base band of direct waveform memory module;

Fig. 7 is spectrogram after the orthogonal modulation of direct frequency synthesis pattern;

Fig. 8 is spectrogram after the orthogonal modulation of direct waveform memory module.

Embodiment

Below in conjunction with accompanying drawing, embodiments of the present invention are further described.

The present invention is the different demands with answering system in conjunction with DDFS and two kinds of methods of DDWS, at system integration and test and initial stage in orbit, what adopt is the mode of waveform storage, facilitate like this us to the distortion of whole transmitting receiver waveform, to analyze, this distortion is revised in original waveform, so just can obtain the higher waveforms of parameter index such as the linearity, phase distortion, thereby be conducive to the accurate estimation of the performance of three-dimensional imaging microwave altimeter.

In orbit in process, can obtain by the method for direct frequency synthesis optimum pulse width and the spectrum width of system, now by upper teletype command, waveform parameter is modified, can obtain easily required signal, thereby the optimum mode of operation of system is assessed.

The present invention stores in conjunction with waveform and direct two kinds of methods of frequency synthesis, the ability that has increased the dirigibility of system and configured as required, thus make native system obtain best observation.

This system relates to a kind of Chirp signal source generator for three-dimensional imaging microwave altimeter, whole hardware system is divided into six major parts, be respectively clock and power distribution system high-speed memory analyzing logic control system 1-Q modulation systems, can realize the double mode wideband digital chirp of DDFS and DDWS signal.First logic control system adopts programmable device FPGA, can generate desired waveform according to parameter request, also can read out the pre-stored data in high-speed memory system and be generated again waveform, two kinds of mode something in commons be by the digital signal in Wave data generation unit through digital-to-analog conversion be converted into simulating signal again in 1-Q modulation systems orthogonal modulation chip modulate, use quadrature modulation circuit, can make to modulate the twice that rear bandwidth is baseband bandwidth.The present invention has adopted digital-to-analog conversion rate to reach 16 DAC of 1Gsps, and under the over-sampling rate of 8 times, exportable base band highest frequency reaches 110MHz.By orthogonal modulation, bandwidth can reach 220MHz.The carrier frequency of quadrature modulation circuit leaks be less than-49dBc, image frequency inhibition-41dBc, and the maximum spur in < 2GHz frequency range is-31dBc, be less than-34dBc of second harmonic amplitude.

FPGA code is write and is mainly divided into two parts, and the one, DAC is configured, the 2nd, generate I, Q Wave data.DAC configuration communicates by spi bus and DAC.After FPGA powers on normal operation, first carry out the configuration operation of DAC, all register datas are all written to DAC by SPI.This single stepping is all applicable to DDFS pattern or DDWS pattern.Switching between two kinds of patterns realizes by a control port of monitoring FPGA.During this port high level, system works is at direct frequency synthesis pattern DDFS, automatically toward DAC output data.Under low level, be waveform memory module DDWS, etc. the PC in system, after FPGA downloads waveform, start normally toward DAC output data.

Under DDFS pattern, utilize Xilinx company that the IP kernel of DDFS is provided, user only need to set output figure place, and the requirements such as frequency resolution can generate VHDL code.In program, set frequency control word and initial phase, just can obtain corresponding Chirp signal.Under DDWS pattern, Wave data is calculated by PC, by parallel port simulative serial port, via FPGA, downloads in dataflash and preserves.After FPGA powers on, first DAC is configured, also serial ports is monitored simultaneously, if host computer has the request of downloading data, carry out down operation, if not request, sense data from dataflash, be stored in the FIFO opening in FPGA, if data length is grown (as in application scenarios such as analogue echoes), data be stored in DDR2.After initialization, from FIFO or DDR2, read data high-speed, be defeated by DAC.

In sum, the present invention has adopted following technical scheme:

The invention discloses a kind of Chirp signal generator for three-dimensional imaging microwave altimeter, its hardware comprises Wave data generative circuit and binary channels digital-to-analog conversion and quadrature modulation circuit two large divisions, and Software for Design comprises direct frequency combining method and direct two patterns of waveform storage means.It is characterized in that:

The Wave data generative circuit of hardware components comprises fpga chip and peripheral configuration circuit (comprising PROM and JTAG downloading wire) thereof.The clock circuit being connected with FPGA in addition, memory circuit part.

Clock chip is connected with FPGA, provides system needed 250MHz clock.Memory circuit is also connected with FPGA, and Wave data can be deposited in this, and the initial phase of working at FPGA reads in Wave data in the FIFO in FPGA.

This part has comprised binary channels DAC, passive low-pass filter circuit, quadrature modulator digital-to-analog conversion and quadrature modulation circuit.Binary channels DAC receives the two-way Wave data producing from FPGA, and its digital-to-analogue is changed into simulating signal.Passive low-pass filter circuit is connected on the rear class of DAC, the spurious signal of filtering DAC and high fdrequency component, and quadrature modulator is connected on the rear class of low-pass filter, produces the signal after modulation.

Owing to having adopted above design proposal, the useful effect of sending of the present invention is: the one, adopted the framework of FPGA+DAC, can realize direct frequency combining method and direct waveform storage means generation waveform, the framework of the relative FPGA+DDS of waveform generating mode is very flexible simultaneously; The 2nd, by orthogonal modulation, the bandwidth that the present invention can produce is the twice of DAC highest frequency, has reduced the rate requirement to DAC and FPGA; The 3rd, in the present invention, adopt a slice binary channels DAC to replace two single channel DAC, this can reduce interchannel imbalance of amplitude and phase, improves the purity of frequency spectrum of the signal generating, simultaneously simple than the signal source circuit of two single channel DAC of existing use; Finally, " seamless " interface between DAC and quadrature modulator has been simplified circuit on the one hand, has brought high s/n ratio, makes on the other hand system have high carrier frequency and reveals and mirror image rejection.

The digital Chirp generator target in kind of developing sees the following form.

Systematic parameter	Index
		System clock	250MHz

DAC figure place	16
		DAC inputs data transfer rate	250Msps
DAC output data rate (after interpolation)	1Gsps
		Stored waveform time span	500us
Local oscillator leakage	-49dBc
		Image frequency suppresses	-41dBc
Base band highest frequency	110MHz
		Wide T during pulse	10us
Waveform Jitter	<160ps
		Uneven degree in passband	<0.4dB

Software workflow of the present invention divides two kinds of patterns to process.

When it is operated in direct frequency synthesis pattern lower time, I, the Q two paths of data direct frequency synthesis computing module in FPGA calculates in real time, and it is upper to be sent to DAC, produces IQ two-way baseband signal.This real-time computing to FPGA has proposed very large requirement, the direct frequency synthesis module in FPGA calculate and table look-up, all require while exporting data very efficient with accurately.In the design, the IP kernel that directly frequency synthesis module is provided by Xilinx company produces.

When it is operated in direct waveform memory module lower time, I, Q two paths of data produce from computing machine, and download in FLASH via FPGA by parallel port simulative serial port.When system initialization, FPGA loads data in the FIFO opening FPGA inside (if data volume has exceeded the size of FIFO from FLASH, deposit in DDR2), during signal generation work, by FPGA, the data in DDR2 are read on DAC, the I producing, Q two-way baseband signal is inputted quadrature modulator after filtering afterwards.

After system realizes, directly waveform time-domain diagram and the details thereof of the base band of frequency synthesis pattern, direct waveform memory module are shown in respectively Fig. 5, Fig. 6, and after orthogonal modulation, spectrogram is shown in respectively Fig. 7, Fig. 8.

By spectrogram, can be obtained, for direct frequency synthesis and direct waveform memory module, with respect to the energy in carrier frequency bandwidth, second harmonic average is all-below 35dB, be about-20dB of third harmonic average.Spurious frequency and the amplitude of 500MHz-1500MHz are as shown in the table.Due to from passband away from, these are spuious little to systematic influence, as long as the wave filter (centre frequency 1GHz, bandwidth 400MHz) that is greater than 2.5 by Q value, these humorously can be involved to the spuious very low level that is suppressed to.For example, at the 128 rank FIR wave filters that are 2.5 by Q value by it, the following@1266MHz of maximum spur can be suppressed to-36dB.

The IQ two-way amplitude imbalance degree of real system is less than 1:1.01, and phase unbalance degree is less than 0.01rad.

The spurious frequency of 500MHz-1500MHz and amplitude

Spurious frequency	Spuious amplitude/the dB of DDFS	Spuious amplitude/the dB of DDWS
			586MHz	-27.5	-28.2
683MHz	-23.1	-24.1
			1266MHz	-27.8	-24.9
1400MHz	-26.6	-27.3

As shown in Figure 1, this figure is that the equipment that the present invention realizes under direct frequency synthesis DDFS pattern forms frame diagram, and data are produced by the phase-accumulated unit in the built-in DDS IP kernel of xilinx and table look-up (LUT) by FPGA inside, then pass through DAC data transformation.

As shown in Figure 2, this figure is that the equipment that the present invention realizes under direct waveform storage DDWS pattern forms frame diagram, and Wave data calculates by outer PC, then, by parallel port simulative serial port, via FPGA, in flash, preserves.When system initialization, FPGA is sense data from flash, be stored in the FIFO opening in FPGA, when data length, grow (as in application scenarios such as analogue echoes), FPGA is first stored in data coupled DDR2(second generation double data rate Synchronous Dynamic Random Access Memory) in.After initialization, FPGA reads Wave data at high speed from FIFO or DDR2, is defeated by DAC.

As can be seen here, only need to revise FPGA internal processes, just can on the hardware platform of direct waveform memory module, realize direct frequency synthesis pattern.Therefore, the design frame chart of hardware just be take the hardware block diagram of direct waveform memory module and is that basis launches, and the final system chart adopting as shown in Figure 3.

The parts selection of data generating circuit: in the selection of FPGA, first consider frequency of operation, with the interface of high-speed memory and whether have the IO mouth of DDR function, what select is the Virtex5 series of Xilinx company.In the selection of high speed memory devices, the support according to the Vrtex5 series of Xilinx to memory device, considers the requirement of the needed storage speed of system, has selected the DDR2 of Micron company, and model is MT47H16M16BG-37E.That low-speed memory part Flash adopts is the AT45DB041D of atmel corp, and AT45DB041D is a 2.5V or 2.7V power supply, the FLASH storer of serial line interface.

Applied in the present invention orthogonal modulation, orthogonal modulation can make to modulate the twice that rear bandwidth reaches the maximum output frequency of DAC, can reduce the requirement of system to device.Because the requirement for synchronous (consistance of amplitude, phase place) of I, Q circuit-switched data on quadrature modulation circuit is very high, if select two DAC to export respectively I, Q two-way, be easy to occur nonsynchronous problem.First the present invention considers this point when selector, and the DAC monolithic of selecting just has I, the input and output of Q two-way.The AD9779A of selected model WeiAD company, it is to have twin-channel, 16, the digital to analog converter of wide dynamic range, it can pass through programming Control DAC, gains and the compensation and calibration of setovering, and reaches best image frequency and suppress and carrier frequency leaking performance when modulation.AD9779A can TongAD company the analogue quadrature moducator of ADL537x FMOD series carry out " seamless interfacing ", they have identical bias level and the simulating signal amplitude of oscillation.Because its interface circuit is very simple, components and parts used are few, so can not increase noise and insertion loss because increasing element, make whole circuit can keep high s/n ratio, therefore the present invention has selected this serial quadrature modulator, its concrete model is ADL5371, and its operating frequency range is 500MHz～1500MHz, and the 3dB baseband bandwidth that is greater than 500MHz is provided.

The interface of each intermodule of hardware of the present invention is such:

Clock line: the clock that CDCM61004 clock chip produces offers FPGA by LVDS, FPGA produces the clock that has certain time-delay by DCM module, by LVDS, offer DAC.And clock between FPGA and DDR2 uses, be difference SSTL18

Data are downloaded and configuration: PC downloading data is to Flash, and FPGA is from Flash reading, and FPGA configures to DAC, use be all spi bus.

FPGA communicates by letter with DDR2's: the DDR2 standard according to JEDEC is carried out.

2 passage 16 position digital signals of FPGA and DAC: by LVCMOS25 level

The two-way baseband signal of the interface of DAC and LPF and quadrature modulator: DAC output all has the biasing of 0.5V, and the single-ended signal amplitude of oscillation is 1V p-p, and its differential swings is 2V p-p.And the desired input of quadrature modulator is also the biasing that has equally 0.5V, differential swings representative value is 1.4V p-p.

FPGA Software for Design

By above-mentioned hardware block diagram, can be obtained, two kinds of patterns can be used same hardware platform on hardware, and just FPGA internal code is different.Introducing two kinds of FPGA codes under pattern below writes:

Under direct frequency synthesis pattern, code generates by the IP kernel of the direct frequency synthesis that provides of Xilinx company, only needs the requirements such as setpoint frequency resolution and initial phase can generate VHDL code.

The calculating of the step value of frequency control word is according to existing strict science formula, to input formula in matlab to calculate, and concrete formula and computing method are as follows:

Frequency control word establishing method: what frequency control word was corresponding is the address stepping numerical value of direct frequency synthesis module, and frequency control word is it is also one and related amount of time, thus the step value of other setpoint frequency control word, for:

${\mathrm{\&Delta;\&theta;}}_{\mathrm{inc}}=\frac{d\left(\mathrm{\&Delta;\&theta;}\right)}{\mathrm{dt}}\&CenterDot;\mathrm{\&Delta;t}=\frac{B\&CenterDot;2^{B_n}}{T\&CenterDot;f_{\mathrm{clk}}\&CenterDot;f_{\mathrm{clk}}}---\left(1\right)$

The calculation of initial value of frequency control word, considers at t=T/2 place, and frequency control word is zero, anti-while shifting t=0 onto,

Δθ ₀=-Δθ _inc×N=-Δθ _inc×f _clk×T/2 (2)

It is a negative value.In the expression of FPGA, by Δ θ _inc* f _clk* T/2 step-by-step negate again+1, can obtain this negative value.

Directly the Wave data under waveform memory module is calculated by PC, by parallel port simulative serial port, via FPGA, downloads in flash and preserves.After FPGA powers on, first DAC is configured, also serial ports is monitored simultaneously, if host computer has the request of downloading data, carry out down operation, if not request, sense data from flash, be stored in the FIFO opening in FPGA, if data length is grown (as in application scenarios such as analogue echoes), data be stored in DDR2.After initialization, from FIFO or DDR2, read data high-speed, be defeated by DAC.Its flow process is shown in Fig. 5.

It should be noted last that, above embodiment is only unrestricted in order to technical scheme of the present invention to be described.Although the present invention is had been described in detail with reference to embodiment, those of ordinary skill in the art is to be understood that, technical scheme of the present invention is modified or is equal to replacement, do not depart from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of claim scope of the present invention.

Claims (10)

1. the Chirp signal generator for three-dimensional imaging microwave altimeter, be used to three-dimensional imaging microwave altimeter system to produce Direct Digital frequency synthesis and store double mode wideband digital chirp signal with direct waveform, it is characterized in that, described signal generator comprises successively and to be connected in series:

Wave data generation unit ，Gai unit is based on fpga chip, for adopt direct frequency combining method or directly waveform storage means generate Wave data, and the Wave data that the Wave data of generation is divided into two-way quadrature is exported;

Binary channels D/A conversion unit ，Gai unit is based on a slice binary channels digital to analog converter, and this digital to analog converter, for receiving the Wave data from the output of Wave data generation unit, is carried out digital-to-analogue conversion, produces the two-way baseband signal line output of going forward side by side; With

Orthogonal modulation unit, for receiving the two-way baseband signal of described binary channels D/A conversion unit output and carrying out orthogonal modulation, produces the Chirp signal for three-dimensional imaging microwave altimeter.

2. the Chirp signal generator for three-dimensional imaging microwave altimeter according to claim 1, is characterized in that, described Wave data generation unit further comprises:

Be used to described fpga chip to provide the clock generating of clock to distribute subelement and clock line;

Be used to described fpga chip that the power distribution subelement of power supply is provided; With

The Wave data that is used to described fpga chip to produce is stored, or will store the storing sub-units of the required Wave data of this FPGA at the initial phase of described fpga chip work.

3. the Chirp signal generator for three-dimensional imaging microwave altimeter according to claim 2, it is characterized in that, described storing sub-units further comprises: two DDR2 SDRAM chips and a slice Dataflash chip, wherein DDR2 provides real-time storage fast, and Dataflash provides jumbo low speed storage, power down is obliterated data not; If fpga chip is operated under direct waveform memory module, it is read into Wave data FIFO wherein and goes from Dataflash, if data volume is larger, data is read in DDR2SDRAM and is gone.

4. the Chirp signal generator for three-dimensional imaging microwave altimeter according to claim 3, is characterized in that, the clock that described clock generating distributes subelement specifically to adopt CDCM61004 clock chip to produce; And the clock producing offers fpga chip by LVDS clock line, fpga chip produces and has the clock of certain time-delay and offer binary channels D/A conversion unit by LVDS clock line by DCM module; And that the clock between fpga chip and DDR2 is used is difference SSTL18.

5. the Chirp signal generator for three-dimensional imaging microwave altimeter according to claim 1, is characterized in that, between described binary channels D/A conversion unit and orthogonal modulation unit, is also connected with a passive low ventilating filter.

6. the Chirp signal generator for three-dimensional imaging microwave altimeter according to claim 5, is characterized in that, described passive low ventilating filter is π type passive low ventilating filter.

7. the Chirp signal generator for three-dimensional imaging microwave altimeter according to claim 1, is characterized in that, described fpga chip further comprises:

Direct frequency synthesis module, for three-dimensional imaging microwave altimeter system in orbit during, according to length and the spectrum width by uploading frequency word and the frequency step value change waveform of command, and then generation Wave data, and this direct frequency synthesis module is produced by the IP kernel of Virtex5 series; With

Directly waveform memory module, for when three-dimensional imaging microwave altimeter system integration and test and initial stage in orbit, adopts this module to receive and inputs Wave data wherein by outer computer.

8. the Chirp signal generator for three-dimensional imaging microwave altimeter according to claim 1, is characterized in that, described binary channels D/A conversion unit specifically adopts AD9779A, and described orthogonal modulation unit adopts the quadrature modulator of ADL5371 model;

Wherein, the binary channels D/A conversion unit of above-mentioned model and orthogonal modulation unit can carry out " seamless interfacing ".

9. for a Chirp signal generating method for three-dimensional imaging microwave altimeter, the method is used to three-dimensional imaging microwave altimeter system that its required Chirp signal is provided, and described method comprises:

When three-dimensional imaging microwave altimeter system integration and test and initial stage in orbit, based on fpga chip, adopt the mode of waveform storage to produce Wave data;

When three-dimensional imaging microwave altimeter system is in orbit in process, based on fpga chip, by the method for direct frequency synthesis, obtain optimum pulse width and the spectrum width of system, and by upper teletype command, optimum pulse width and waveform parameter corresponding to spectrum width are modified, produce required Wave data;

The Wave data that one of above-mentioned two kinds of modes are produced adopts a slice binary channels digital to analog converter to carry out digital-to-analog conversion and adopt quadrature modulator to carry out orthogonal modulation, the final Chirp signal for three-dimensional imaging microwave altimeter of output.

10. the Chirp signal generating method for three-dimensional imaging microwave altimeter according to claim 9, is characterized in that, described method also comprises:

The a certain control port of monitoring FPGA is known the step of the producing method of Wave data, and this step is specially:

When being high level, port is operated in direct frequency synthesis pattern, automatically toward binary channels digital to analog converter output data;

When port is low level, be waveform memory module, wait outer computer to start toward binary channels digital to analog converter output data after fpga chip is downloaded waveform;

Wherein, when under direct frequency synthesis pattern, user sets frequency control word and initial phase, just can obtain corresponding Chirp signal;

When under waveform memory module pattern, Wave data is calculated by PC, by parallel port simulative serial port, via FPGA, downloads in dataflash and preserves; After fpga chip powers on, first binary channels digital to analog converter is configured, also serial ports is monitored simultaneously, if host computer has the request of downloading data, carry out down operation, if there is no request, sense data from dataflash, be stored in the FIFO opening in fpga chip, if data length is longer, data are stored in DDR2, after initialization, from FIFO or DDR2, read data high-speed, be defeated by binary channels digital to analog converter.

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