CN1832350A - Multiple carrier-frequency digital frequency source - Google Patents

Abstract

This invention discloses a multi-carrier frequency digital frequency source including a computer interface circuit, a clock and drive circuit, a field programmable gate array FPGA unit, a direct digital synthesizing DDS sub-system, in which, said clock and drive circuit provides clock signals with strong driving ability to FPGA and DDS units in the system, said FPGA unit controls multiple same DDS sub-systems, each of which forms an independent channel output to generate different signal kinds, signals of different modulations, different frequencies and phases according to the time sequence sent by the FPGA unit and generates echo analog signals by simulating actual signals, especially the LFMICW signals.

Description

Multiple carrier-frequency digital frequency source

Technical field

The invention belongs to electronic information technical field, it is synthetic to relate to numerical frequency, and specifically a kind of multiple carrier-frequency digital frequency source can be used for the occasion that fields such as radar, communication require to provide simultaneously a plurality of synchronous intermediate-freuqncy signals source.

Background technology

For the design in numerical frequency source, adopt following several method usually:

1. low noise high-resolution design of Direct Digital Frequency Synthesizer is as " wideband radar signal generating technique, Fei Yuanchun etc. write, Beijing, National Defense Industry Press, 2002.1 ".This method adopts compositions such as digital controlled oscillator, level translator, digital-to-analogue D/A converter, low pass filter and single chip machine controlling circuit, can reach good spectral performance.But this method resolution element is too much, and consistency is difficult to control, is not suitable for the use under the overloading frequency situation.

2. adopt the Direct Digital frequency synthesis source of computer bus control, as " being used for the Direct Digital frequency synthesis source ， Jiang Yun of nulcear magnetic resonance (NMR) etc., Wave Spectrum magazine, the 18th volume, the fourth phase, 2001.12 ".Used three DDS chips in the frequency source of this method design, and it is operated on the same ISA plug-in card, data/address bus, address bus and the power supply directly enjoying isa bus and provided.By programmable logic device PLD the address on the isa bus is deciphered, the work of 3 DDS of control. though this method has reduced cost, can directly control by computer, but owing to there is not filter, signal to noise ratio is not enough, and the I/O read or write speed is limited, has limited the speed that frequency and phase place are switched, and key is to be unfavorable for overloading expansion frequently.

3. based on the signal simulator of DDS technology, as " based on the sonar signal simulator of DDS technology, Gao Peng; Sang Enfang; communication and TV, 2003 the 10th phases ", this method has proposed a kind of implementation of the digital versatile sonar signal simulator based on the DDS technology.By the output that the amplitude and the phase place of control DDS device output signal are come the analog imaging sonar transducer array, can simulate accurately target echo on any distance and the orientation, and echo-signal that can the skimulated motion target.This method has extended capability preferably, is suitable for the application of simulator, but this method is too narrow at face, is not easy to as the universal frequency source.

The content of invention

The objective of the invention is to avoid the deficiency of above-mentioned prior art, a kind of multiple carrier-frequency digital frequency source is provided, produce the signal of unlike signal type, different modulating, different frequency and phase place, can effectively simulate actual signal environment and a plurality of controlled signal source, to solve the practical problem that a plurality of synchronous intermediate-freuqncy signals source need be provided simultaneously in fields such as electronics, communications.

Technical scheme of the present invention is achieved in that

Multiple carrier-frequency digital frequency source of the present invention comprises: computer interface circuit, clock and drive circuit, on-site programmable gate array FPGA unit, synthetic DDS subsystem four parts of Direct Digital, its main feature is to adopt a plurality of identical DDS subsystems of a slice FPGA unit controls, each DDS subsystem constitutes an independently passage output, realizes the generation and the control of its waveform parameter of any multiple signals.

Above-mentioned multiple carrier-frequency digital frequency source, wherein the FPGA unit comprises: computer interface control module, DDS kernel control module, fault detection module.This computer interface control module is used for carrying out exchanges data with computer, and the control command that is about to the computer reception is transferred to the DDS kernel control module and handles, and becomes corresponding sequential and makes the DDS subsystem according to the designated parameters output waveform; State information with the DDS subsystem work feeds back to computer simultaneously; This DDS kernel control module is used for the DDS subsystem is produced timing control signal, promptly obtains the parameters of system from Computer Interface Module, and the parameters of control DDS subsystem output waveform makes it to satisfy system requirements; Whether this fault detection module is used for the signal that the DDS subsystem feeds back is analyzed, detect in real time whether current module is in normal operating conditions and be the signal of default.

Above-mentioned multiple carrier-frequency digital frequency source, wherein each DDS subsystem is made up of DDS unit and signal conditioning circuit, and the DDS unit is given and is outputed to port after signal conditioning circuit is handled according to the LFMICW signal of the timing sequence generating relevant parameter of FPGA unit transmission.

Above-mentioned multiple carrier-frequency digital frequency source, wherein clock and drive circuit are made up of constant-temperature crystal oscillator or outside input clock and multipath clock drive circuit, the clock signal that is used to FPGA unit in the system and DDS unit that strong driving force is provided, and satisfy clock synchronization between each DDS subsystem by the wiring of clock circuit, with obtain output signal synchronously.

Utilize the said frequencies source to produce the method for linear FMICW LFMICW signal, carry out according to the following procedure:

(1) according to the time-frequency characteristic of LFMICW by the control interface of user by computer, the waveform parameter of LFMICW is set;

(2) the computer interface circuit sends this waveform parameter to the FPGA unit and handles and preserve, and produces the LFMICW control timing, is sent to the synthetic DDS subsystem of at least one road Direct Digital;

(3) after each road DDS subsystem is handled this control timing, output LFMICW signal.The process that above-mentioned FPGA unit produces the LFMICW control timing is as follows:

(1) the DDS chip in the DDS subsystem is resetted, and empty high impulse of phase accumulator register generation;

(2) in the DDS chip, select linear frequency modulation Chirp pattern, and chirp rate, initial frequency and first phase are set;

(3) sequential of DDS kernel control module output is judged, if then empty phase accumulator register full modulation period;

(4) judge whether output timing arrives duty cycle, if not, circulation then continued up to duty cycle, the work of pulse repetition period * LFMICW of duty cycle=LFMICW ratio;

The range value of the LFMICW duty cycle that (5) user is configured writes the amplitude registers of DDS chip;

(6) whether judge output timing to stand-down, if not, then continue circulation up to stand-down, stand-down=LFMICW the pulse repetition period * (work of 100%-LFMICW than);

(7) empty amplitude registers in the DDS chip, return step (3) and continue circulation and carry out.

The present invention has following effect:

1. the present invention is owing to adopt identical DDS subsystem, thereby can carry out completely that circuit duplicates, and can keep the consistency of output signal well; Be consistent on performance owing to each subsystem of the present invention simultaneously, so also can exchange between these subsystems, improved the adaptation ability of DDS subsystem;

2. the present invention is owing to adopt the DDS unit, can produce dissimilar signals such as single-frequency, AM, FM, linear frequency modulation CHIRP, linear frequency modulation interruption continuous wave LFMICW, two-phase sign indicating number, radar echo simulation flexibly, can also design random waveform easily according to customer requirements;

3. the LFMICW signal that the present invention produced can be widely used in high-frequency ground wave radar, the accurate terminal guidance of guided missile, bury ground object detection, comprises aspects such as metal or nonmetallic mine, scene monitoring, meteorological observation and CAS;

4. the present invention can be widely used in electronics, communication etc. needs in the overloading system frequently, both reduced the development time of project, the debugging and the test of project have also been made things convenient for, generation to any multiple signals can be simulated, the emission driving source that not only can be used as phased array radar, and configuration constant-temperature crystal oscillator or atomic clock, can obtain high stable, low Spurious Free Dynamic Range SFDR, low signal of making an uproar mutually.

Description of drawings

Fig. 1 is a theory of constitution block diagram of the present invention

Fig. 2 is clock of the present invention and drive circuit figure

Fig. 3 is the differential amplifier circuit figure in the signal conditioning circuit of the present invention

Fig. 4 is the filter composition figure in the signal conditioning circuit of the present invention

Fig. 5 is the drive circuit figure in the signal conditioning circuit of the present invention

Fig. 6 is the flow chart that the present invention produces the LFMICW signal

Fig. 7 is the procedure chart that FPGA of the present invention unit produces control timing

Fig. 8 is the sequential chart that FPGA of the present invention unit produces the LFMICW signal

Fig. 9 is specific embodiments of the invention figure

Figure 10 is the system phase noise pattern of the embodiment of the invention

Figure 11 is the domain waveform figure of LFMICW local time that the embodiment of the invention produces

Figure 12 is the LFMICW frequency domain spectrogram that the embodiment of the invention produces

Embodiment

With reference to Fig. 1, the present invention is made up of FPGA, a plurality of DDS subsystem, clock and drive circuit, computer interface circuit, and each DDS subsystem constitutes the output of a passage, and the structure of each parts is as follows:

1.FPGA unit

This FPGA or ASIC unit can adopt the FPGA programming or be converted into asic chip realizes that this unit comprises logical gates such as DDS kernel control module, fault detection module, computer interface control module.Wherein the DDS kernel control module produces the timing control signal to the DDS subsystem, promptly obtain the parameters of system from Computer Interface Module, the parameters of control DDS subsystem output waveform makes it to satisfy system requirements, and the sequential of this output waveform is to decide according to the DDS chip that system selects for use.Whether fault detection module is in order under the situation about breaking down in system the user to be pointed out, and promptly the signal that the DDS subsystem is fed back is analyzed, detect in real time whether current module is in normal operating conditions and be the signal of default.The computer interface control module is to dispose according to the selected computer interface of system, be used for carrying out exchanges data with computer, be about to computer reception control command and be transferred to the processing of DDS kernel control module, become corresponding sequential and make the DDS subsystem according to the designated parameters output waveform; State information with the DDS subsystem work feeds back to computer simultaneously.

2. clock and drive circuit

Clock and drive circuit such as Fig. 2 are made up of frequency multiplier U3, clock driver chip U4 and peripheral element, and wherein R17～R27 is a build-out resistor, is used for reducing the ringing effect on the clock line; E5, C9 are decoupling capacitor; J2 connects the output of constant-temperature crystal oscillator or atomic clock.Clock signal is given clock driver chip U4 after frequency multiplier U3 frequency multiplication, when increasing the output driving force, guaranteed interchannel consistency, finish the clock signal that the FPGA unit in the system and DDS unit is provided strong driving force, and clock line is carried out isometric estimation by arrangement architecture that the wiring of clock circuit is arranged to crawl.For crosstalking of reducing to crawl and connect up and bring, around clock line, cover the copper floor file and protected, satisfy the clock synchronization between each DDS subsystem, to obtain the synchronous of output signal.When needing high stable, low signal output of making an uproar mutually, system should adopt constant-temperature crystal oscillator or atomic clock as the input clock source.

3. computer interface circuit

The computer interface circuit can be determined by the interface that system need dispose, can adopt the pairing interface circuit of computer interfaces such as serial ports, parallel port, USB to realize, finish and set up data interaction with FPGA or ASIC unit with computer system and be connected, make the user can control the parameters of output signal by computer interface, make FPGA or ASIC unit that the state information of DDS subsystem is returned to computer simultaneously, understand the operating state of system for the user from computer interface.The computer interface circuit is the optional part of system, and this system also can the divorced from computer isolated operation.

4.DDS subsystem

Each DDS subsystem is made up of DDS unit and signal conditioning circuit, can adopt the DDS+PLL technology that frequency band is expanded under broadband and ultra broadband occasion.Wherein:

(1) the DDS unit can adopt DDS integrated chip and peripheral circuit thereof to form, for example AD9854, AD9858 etc.The control of DDS unit is finished by the FPGA unit, and its clock is provided by clock circuit and drive circuit thereof.

(2) signal conditioning circuit is made of differential amplifier circuit, filter circuit and drive circuit.

This differential amplifier circuit adopts differential mode output shown in Figure 3, is made up of differential amplifier MAX436 and peripheral element, and wherein R1, R2 are the input build-out resistor, and R5 is the output build-out resistor, for input and output are mated, disturbs to reduce ring; E1, E2, C2, C3, C4, C5 are decoupling capacitor, and Z1, Z2 are the high frequency magnetic bead, all are for to power filter, reduce the influence of power supply noise pair amplifier; R3 is a mutual conductance resistance; The output current of C6 and R4 Combination Control amplifier.

This filter circuit considers that the output of DDS unit contains a large amount of harmonic componentss, will reduce the discontinuity of phase place as far as possible in the filtering harmonic component, thus designed 11 rank Chebyshev passive low ventilating filters, as shown in Figure 4.

This drive circuit adopts the in-phase proportion structure for amplifying, as shown in Figure 5.Wherein U1 is a low-noise wide-band amplifier, and R6, R7 are the input build-out resistor, and R11 is the output build-out resistor; E3, E4, C7, C8 are decoupling capacitor, and Z3, Z4 are the high frequency magnetic bead, and R8, R9 and R10 are the amplifier gain controlling resistance.

With reference to Fig. 6, the process that the present invention produces the LFMICW signal is as follows:

(1) user is by the waveform parameter of the control layout setting LFMICW of computer, this waveform parameter comprises initial frequency, initial phase, amplitude, chirp rate, work ratio, pulse repetition period, modulation period of each road signal etc., and wherein fire pulse width is T _e, the pulse repetition period is T _r, be T modulation period _m, T _m=MT _r, M is a transmitted pulse number in modulation period, then transmits and can be expressed as:

$s\left(t\right)=g\left(t\right)e^{j({2\mathrm{\&pi;f}}_{0}t-\mathrm{\&pi;\&mu;}{t}^2+{\mathrm{\&phi;}}_0)},0\&le;t<T_m$

Wherein g (t) is pulse-modulated signal or claims gate-control signal,

$g\left(t\right)=\underset{m=0}{\overset{M-1}{\mathrm{\&Sigma;}}}\mathrm{rect}(t-m{T}_r),\mathrm{rect}\left(t\right)=\left\{\begin{array}{c}\mathrm{1,0}\&le;t<{\mathrm{<figure-callout\; id="0"\; label="T\; e"\; filenames="A20061004267900161.png,A20061004267900181.png"\; state="\{\{state\}\}">T</figure-callout>}}_e\\ 0,T_e\&le;t\&le;T_r\end{array}\right.$

f ₀Be carrier frequency; μ is a chirp rate; φ ₀Be first phase.Operating frequency is from f ₀To f ₀+ B _μ, modulating bandwidth B _μ=μ T _m

(2) pass a parameter, promptly send waveform parameter to the FPGA unit by the computer interface circuit;

(3) receive, handle and preserve parameter, promptly be responsible for receiving and it handled the back preserve by the computer interface control module of FPGA unit;

(4) the FPGA unit produces control timing such as Fig. 8 according to the parameter of preserving according to process shown in Figure 7, and control a plurality of DDS unit and produce multichannel LFMICW signal, and through outputing to each passage after signal conditioning circuit filtering, the amplification.

With reference to Fig. 7, the process that the FPGA unit produces control timing is as follows:

(1) the DDS chip that resets earlier;

(2) empty phase accumulator register, on CLR ACC2 position, produce a high impulse;

(3) select the Chirp pattern, MODE=011 is set;

(4) chirp rate is set;

The value of the value of chirp rate=step frequency register/stepping time register

Value=the step frequency of step frequency register * 2 ⁴⁸/ DDS working clock frequency

Value=the stepping time of stepping time register * DDS working clock frequency

(5) initial frequency and first phase are set;

Value=the initial frequency of FREQUENCY CONTROL word register * 2 ⁴⁸/ DDS working clock frequency

Value=the first phase of first phase control register * 2 ¹⁴/ 2 π

(6) judge whether output signal expires a modulation period, if empty amplitude registers earlier;

(7) judge whether duty cycle, if not, circulation continued;

Duty cycle=pulse repetition period * work ratio

(8) amplitude registers is set, the range value that configures is write amplitude registers;

(9) judge whether stand-down, if not, circulation continued;

Stand-down=pulse repetition period * (100%-works and compares)

(10) empty amplitude registers, return step (6) and continue circulation.

With reference to Fig. 8, the sequential that FPGA of the present invention unit produces the LFMICW signal obtains according to the process that the FPGA unit produces control timing.Provided the time-frequency characteristic of LFMICW among Fig. 8, wherein T _eBe fire pulse width, T _rBe the pulse repetition period, T _mBe frequency modulation(FM) cycle, f ₀Be carrier frequency, μ is a chirp rate, φ ₀Be first phase, B _μBe modulating bandwidth.MODE is the mode of operation control bit of AD9854, produces LFMICW and requires MODE=" 011 "; FTW1 is No. 1 FREQUENCY CONTROL word register of AD9854, is used for controlling the initial frequency of LFMICW; DFW is the step frequency control word register of AD9854, is used for controlling the step frequency of LFMICW in the unit stepping time; RAMP RATE is the stepping time register of AD9854, and it and DFW have determined the chirp rate of LFMICW jointly; SHAPE MULTI is the amplitude registers of AD9854, controls stand-down and the duty cycle of LFMICW by it is set; CLR ACC2 be AD9854 empty the accumulator register position, whether empty accumulator register by its decision is set; UPD CLK is that the FPGA unit is used for controlling the clock that AD9854 upgrades its register value, upgrades the register value of AD9854 at UPD CLK rising edge.

With reference to Fig. 9, concrete implement to adopt 1 FPGA and 8 DDS chip AD9854 and peripheral circuit thereof to form for one of the present invention.DDS subsystem and FPGA module are positioned on the same circuit board.Clock signal is provided by constant-temperature crystal oscillator, gives FPGA and each DDS subsystem through frequency multiplier and clock driving.Computer sends the radar emission signal parameter to FPGA by serial ports, handles the output of back control 8 road DDS subsystems by FPGA, makes and satisfies certain frequency and phase relation between each output signal, gives transmitting antenna after output signal being amplified through filtering again.Its output frequency of low pass filter in this DDS subsystem is between 6～8MHz, bandwidth is 8.5M, less than-29.4dB, the rejection ratio of triple-frequency harmonics can suppress harmonic component and the outer High-frequency Interference of band effectively less than-53.1dB in the harmonic wave rejection ratio at second harmonic place.

System index of the present invention is as follows:

A) reference frequency output

System adopts the 20M clock, and the synchronous circuit design is all adopted in FPGA inside, can effectively reduce burr, improves the stability of system.The internal work clock of AD9854 adopts the design of 15 frequencys multiplication, can reach 300M.According to nyquist sampling theorem, the theoretical exportable frequency of DDS is 0～150M, owing to generally get its 4/5 on the engineering, so actual exportable frequency range is 0～120M.

B) system's output frequency stepping

When AD9854 worked under the 300MHZ clock, its frequency resolution can reach 300M/2 ⁴⁸≈ 1 μ Hz.

C) system's index of making an uproar mutually

Figure 10 has provided at 204.8s and in the time frequency source output signal has been gathered and results of spectral, and visible noise power at offset carrier 1Hz place is P _m=-115.1dBm handles bandwidth B _m=10mHz, then its phase noise is

ψ(f _m＝1Hz)＝P _m-P _s-10log(B _m/B _M)+C _m

＝-115.1-10log(10 ^-2)+2.5

＝-92.6(dBc/Hz)

B wherein _MBe equivalent 1Hz noise bandwidth, C _mFor the measuring system correction error, get 2.5dB.As seen, the phase noise in this numerical frequency source is low, satisfies systems such as radar and carried out the requirement of long-time coherent accumulation in hundreds of seconds time.

Test result

Test condition: crystal oscillator: constant-temperature crystal oscillator 10M * 2

DDS power supply: 3.3V 15A linear power supply

AD9854 work clock: 20M*15=300MHz

Filter network: 11 rank Chebyshev low pass LC passive filters

Tester: 500M Agilent 4395A network/electric impedance analyzer

500M TDS3054 digital oscilloscope

Test waveform: in overloading frequently under the situation, can obtain the signals such as single-frequency, CHIRP, LFMICW, two-phase sign indicating number, radar echo simulation of controllable parameters such as frequency, amplitude, phase place by this frequency source.Randomly drawed by any two passages in 8 passages of frequency source system and to obtain two-way LFMICW signal, its phase place is set to 0 ° and 180 ° respectively.Its local time's domain waveform such as Figure 11.As seen from Figure 11, the phase place of two passages be provided with consistently, be respectively 0 ° and 180 °, this waveform has also embodied the temporal signatures of LFMICW.The frequency domain frequency spectrum that this signal is obtained by spectrum analyzer through external trigger as shown in figure 12, as seen from Figure 12, the Spurious Free Dynamic Range SFDR of the LFMICW signal that is obtained by this frequency source is better than-55dB.

Claims (8)

1. multiple carrier-frequency digital frequency source, comprise computer interface circuit, clock and drive circuit, on-site programmable gate array FPGA unit, the synthetic DDS subsystem of Direct Digital, it is characterized in that adopting a plurality of identical DDS subsystems of a slice FPGA unit controls, each DDS subsystem constitutes an independently passage output, realizes the generation and the control of its waveform parameter of any multiple signals.

2. multiple carrier-frequency digital frequency source according to claim 1 is characterized in that the FPGA unit comprises:

The computer interface control module, be used for carrying out exchanges data with computer, the control command that is about to the computer reception is transferred to the DDS kernel control module and handles, become corresponding sequential and make the DDS subsystem according to the designated parameters output waveform, the state information with the DDS subsystem work feeds back to computer simultaneously;

The DDS kernel control module is used for the DDS subsystem is produced timing control signal, promptly obtains the parameters of system from Computer Interface Module, and the parameters of control DDS subsystem output waveform makes it to satisfy system requirements;

Whether fault detection module is used for the signal that the DDS subsystem feeds back is analyzed, detect in real time whether current module is in normal operating conditions and be the signal of default.

3. multiple carrier-frequency digital frequency source according to claim 1, it is characterized in that each DDS subsystem is made up of DDS unit and signal conditioning circuit, the DDS unit is given and is outputed to port after signal conditioning circuit is handled according to the waveform of the timing sequence generating relevant parameter of FPGA unit transmission.

4. multiple carrier-frequency digital frequency source according to claim 3, it is characterized in that signal conditioning circuit is made of differential amplifier circuit, filter circuit and drive circuit, this differential amplifier circuit adopts differential mode output, transfer single ended mode to through differential amplifier, this filter circuit is multistage Chebyshev passive low ventilating filter, this drive circuit adopts the in-phase proportion structure for amplifying, to reduce output impedance, increases the driving force of input impedance and output signal.

5. multiple carrier-frequency digital frequency source according to claim 1, it is characterized in that clock and drive circuit be made up of constant-temperature crystal oscillator or outside input clock and multipath clock drive circuit, the clock signal that is used to FPGA unit in the system and DDS unit that strong driving force is provided, and satisfy clock synchronization between each DDS subsystem by the wiring of clock circuit, with obtain output signal synchronously.

6. multiple carrier-frequency digital frequency source according to claim 5 is characterized in that the wiring of clock circuit is the arrangement architecture that crawls.

7. method of utilizing claim 1 to produce linear FMICW LFMICW signal, carry out according to the following procedure:

(1) according to the time-frequency characteristic of LFMICW by the control interface of user by computer, the waveform parameter of LFMICW is set;

(2) the computer interface circuit sends this waveform parameter to the FPGA unit and handles and preserve, and produces the LFMICW control timing, sends the synthetic DDS subsystem of at least one road Direct Digital to;

(3) after each road DDS subsystem is handled this control timing, output LFMICW signal.

8. method according to claim 7 is characterized in that the process of FPGA unit generation LFMICW control timing is as follows:

(1) the DDS chip in the DDS subsystem is resetted, and empty high impulse of phase accumulator register generation;

(2) in the DDS chip, select linear frequency modulation Chirp pattern, and chirp rate, initial frequency and first phase are set;

(3) sequential of DDS kernel control module output is judged, if then empty phase accumulator register full modulation period;

(4) judge whether output timing arrives duty cycle, if not, then continue circulation up to duty cycle,

The work ratio of pulse repetition period * LFMICW of duty cycle=LFMICW;

The range value of the LFMICW duty cycle that (5) user is configured writes the amplitude registers of DDS chip;

(6) whether judge output timing to stand-down, if not, then continue circulation up to stand-down,

Stand-down=LFMICW the pulse repetition period * (100%-LFMICW work than);

(7) empty amplitude registers in the DDS chip, return step (3) and continue circulation and carry out.

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