CN109656857A - A kind of multifrequency point based on FPGA is switched fast output control method - Google Patents
A kind of multifrequency point based on FPGA is switched fast output control method Download PDFInfo
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- CN109656857A CN109656857A CN201811555169.8A CN201811555169A CN109656857A CN 109656857 A CN109656857 A CN 109656857A CN 201811555169 A CN201811555169 A CN 201811555169A CN 109656857 A CN109656857 A CN 109656857A
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- fpga
- phaselocked loop
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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Abstract
The invention discloses a kind of multifrequency points based on FPGA to be switched fast output control method, belong to electronic technology field, establish multifrequency point fast switch circuit, multifrequency point fast switch circuit includes FPGA, four throw switch of 4 PLL phaselocked loop devices and hilted broadsword, 4 PLL phaselocked loop devices pass through SPI interface and communicate with FPGA, 4 PLL phaselocked loop devices pass through four throw switch of hilted broadsword output frequency point, four throw switch of hilted broadsword carries out the switching of control channel by FPGA, the present invention is designed using FPGA, eliminate external storage chip, I/O resource is relatively abundant, save interconnection resource；The present invention parallel performance powerful using FPGA, substantially increases frequency handover performance, completely can be with the requirement of system handoff delay；Present invention employs the design philosophys of module duplication and state machine, improve designed reliability and stability.
Description
Technical field
The invention belongs to field of communication technology, in particular to a kind of multifrequency point based on FPGA is switched fast output controlling party
Method.
Background technique
The technical requirement of current three audio range frequencies integration module needs to generate starting frequency point 8GHz, terminates frequency point and is
12GHz, step frequency are the output frequency point of 10MHz, the output of a total of 400 frequency handovers, and when each frequency handover is childlike
It in 200us, and is the switching of 4 channels back and forth, each channel switching duration is less than 50ns.
Design traditional at present generally uses main control chip of the single-chip microcontroller device as PLL phaselocked loop device, configures to it
Frequency point output, while doing switching processing.But there is the following in the design scheme:
1. due to needing to generate 400 frequency points, for the frequency point configuration register of PLL phaselocked loop device, it is necessary to store 400
A configuration register value, so as to real-time query and configuration, this requires single-chip microcontrollers to need an additional small storage chip, such as
E2PROM chip.The layout area for both having increased PCB in this way, increases cost, and adds additional and match from storage chip reading
The additional operational overhead of confidence breath.
2. needing to carry out 4 PLL phaselocked loop devices configuration control in real time in design, frequency point selection and channel switching are used
11 IO send parallel data and are controlled, and have 4 road chip SPI configuration pins to be connected, higher to I/O resource demand, it is contemplated that
Miniaturization Design, common singlechip chip are difficult to meet the requirement.
3. the delay of frequency point selection and channel switching is respectively to be less than 200us and be less than 50ns, this is just to main control chip
Real-time proposes very high requirement, it is clear that the serial operating mechanism of single-chip microcontroller is difficult to meet this requirement.
Summary of the invention
The object of the present invention is to provide a kind of multifrequency points based on FPGA to be switched fast output control method, solves tradition
Technical deficiency.
To achieve the above object, the invention adopts the following technical scheme:
A kind of multifrequency point based on FPGA is switched fast output control method, packet following steps:
Step 1: establishing multifrequency point fast switch circuit, multifrequency point fast switch circuit includes FPGA, 4 PLL phaselocked loops
Four throw switch of device and hilted broadsword, 4 PLL phaselocked loop devices pass through SPI interface and communicate with FPGA, and 4 PLL phaselocked loop devices are equal
Frequency point is exported by four throw switch of hilted broadsword,
Four throw switch of hilted broadsword carries out the switching of control channel by FPGA；
Step 2: major state machine, ROM memory module and PLL configuration driven tfi module, ROM storage are set in FPGA
Module is used to store the configuration parameter of 400 frequency points in a manner of frequency point mapping table；
Step 3: after multifrequency point fast switch circuit powers on, FPGA successively carries out initialization to 4 PLL phaselocked loop devices and matches
Set: FPGA configures 113 24bit array registers to each PLL phaselocked loop device by SPI interface, and FPGA once configures one
A PLL phaselocked loop device is reconfigured next PLL phaselocked loop device after the PLL phaselocked loop device configures；
After step 4:FPGA carries out initial configuration whole to 4 PLL phaselocked loop devices, FPGA, which is waited and judged, is
The no switching for receiving headend equipment updates pulse command: if received, major state machine parses pulse command, according to pulse
Instruction reselects the channel of configuration PLL, and major state machine is according to the frequency point corresponding relationship preset in ROM memory module
Table, and with lookup table mode, selection switches the register value of frequency point, and using the value as register updated value, issues PLL configuration and drive
Dynamic tfi module, meanwhile, major state machine is updated to PLL configuration driven tfi module transmitter register value requests, and executes step
5；If do not received, 4 are thened follow the steps；
After step 5:PLL configuration driven tfi module receives register value update request, the control of PLL phaselocked loop device is generated
SPI timing processed, and configured according to ordered pair PLL phaselocked loop device when control SPI, after configuration successful, returns and complete signal
Give major state machine；
Step 6: after major state machine receives completion signal, into standby mode and executing step 4.
Preferably, when executing step 4, FPGA is communicated by serial ports with headend equipment, and the headend equipment is PC computer.
Preferably, the frequency point mapping table includes the frequency of frequency point, the value of register and channel handoff parameter.
Preferably, the model LMX2594 of the PLL phaselocked loop device.
A kind of multifrequency point based on FPGA of the present invention is switched fast output control method, is set using FPGA
Meter eliminates external storage chip, and I/O resource is relatively abundant, saves interconnection resource；The present invention concurrency powerful using FPGA
Can, frequency handover performance is substantially increased, it completely can be with the requirement of system handoff delay；Present invention employs module duplication and shapes
The design philosophy of state machine, improves designed reliability and stability.
Detailed description of the invention
Fig. 1 is master-plan configuration diagram of the invention；
Fig. 2 is FPGA system module diagram of the invention；
Fig. 3 is control flow chart of the invention；
Fig. 4 is the reading configuration data timing diagram of PLL configuration driven tfi module and PLL phaselocked loop device.
Specific embodiment
A kind of multifrequency point based on FPGA as Figure 1-Figure 4 is switched fast output control method, packet following steps:
Step 1: establishing multifrequency point fast switch circuit, multifrequency point fast switch circuit includes FPGA, 4 PLL phaselocked loops
Four throw switch of device and hilted broadsword, 4 PLL phaselocked loop devices pass through SPI interface and communicate with FPGA, and 4 PLL phaselocked loop devices are equal
Frequency point is exported by four throw switch of hilted broadsword,
Four throw switch of hilted broadsword carries out the switching of control channel by FPGA；
The control terminal of four throw switch of hilted broadsword is controlled by two I/O pins of FPGA, and the input interface of four throw switch of hilted broadsword is connected to
The frequency point output interface of 4 PLL, by the control of the digital signal of FPGA, the delivery outlet output 4 of four throw switch of hilted broadsword selects 1
As a result.
Step 2: major state machine, ROM memory module and PLL configuration driven tfi module, ROM storage are set in FPGA
Module is used to store the configuration parameter of 400 frequency points in a manner of frequency point mapping table；
Step 3: after multifrequency point fast switch circuit powers on, FPGA successively carries out initialization to 4 PLL phaselocked loop devices and matches
Set: FPGA configures 113 24bit array registers to each PLL phaselocked loop device by SPI interface, and FPGA once configures one
A PLL phaselocked loop device is reconfigured next PLL phaselocked loop device after the PLL phaselocked loop device configures；
It is built-in register that PLL phaselocked loop device, which configures 113 24bit array registers, can refer to LM2594 chip
Detail file.
After step 4:FPGA carries out initial configuration whole to 4 PLL phaselocked loop devices, FPGA, which is waited and judged, is
The no switching for receiving headend equipment updates pulse command: if received, major state machine parses pulse command, according to pulse
Instruction reselects the channel of configuration PLL, and major state machine is according to the frequency point corresponding relationship preset in ROM memory module
Table, and with lookup table mode, selection switches the register value of frequency point, and using the value as register updated value, issues PLL configuration and drive
Dynamic tfi module, meanwhile, major state machine is updated to PLL configuration driven tfi module transmitter register value requests, and executes step
5；If do not received, 4 are thened follow the steps；
After step 5:PLL configuration driven tfi module receives register value update request, the control of PLL phaselocked loop device is generated
SPI timing processed, and configured according to ordered pair PLL phaselocked loop device when control SPI, after configuration successful, returns and complete signal
Give major state machine；
PLL configuration driven tfi module is the series arrangement timing provided according to LM2594, the single configuration feature of realization
Function defines as shown in table 1 for the interface of PLL configuration driven tfi module and PLL phaselocked loop device, as shown in figure 4, being PLL
The reading configuration data timing diagram of configuration driven tfi module and PLL phaselocked loop device.
Table 1
Sck_o is the SCK signal in Fig. 4, and sda_o is the SDA signal in Fig. 4, and csb_o is the CSB letter in Fig. 4
Number, the output signal for the detection pin that MUXout is LM2594.
Step 6: after major state machine receives completion signal, into standby mode and executing step 4.
Preferably, when executing step 4, FPGA is communicated by serial ports with headend equipment, and the headend equipment is PC computer.
Preferably, the frequency point mapping table includes the frequency of frequency point, the value of register and channel handoff parameter.
Preferably, the model LMX2594 of the PLL phaselocked loop device.
A kind of multifrequency point based on FPGA of the present invention is switched fast output control method, is set using FPGA
Meter eliminates external storage chip, and I/O resource is relatively abundant, saves interconnection resource；The present invention concurrency powerful using FPGA
Can, frequency handover performance is substantially increased, it completely can be with the requirement of system handoff delay；Present invention employs module duplication and shapes
The design philosophy of state machine, improves designed reliability and stability.
Claims (4)
1. a kind of multifrequency point based on FPGA is switched fast output control method, it is characterised in that: packet following steps:
Step 1: establishing multifrequency point fast switch circuit, multifrequency point fast switch circuit includes FPGA, 4 PLL phaselocked loop devices
With four throw switch of hilted broadsword, 4 PLL phaselocked loop devices pass through SPI interface and communicate with FPGA, and 4 PLL phaselocked loop devices pass through
Four throw switch of hilted broadsword exports frequency point,
Four throw switch of hilted broadsword carries out the switching of control channel by FPGA；
Step 2: major state machine, ROM memory module and PLL configuration driven tfi module, ROM memory module are set in FPGA
For storing the configuration parameter of 400 frequency points in a manner of frequency point mapping table；
Step 3: after multifrequency point fast switch circuit powers on, FPGA successively carries out initial configuration to 4 PLL phaselocked loop devices:
FPGA configures 113 24bit array registers to each PLL phaselocked loop device by SPI interface, and FPGA once configures one
PLL phaselocked loop device is reconfigured next PLL phaselocked loop device after the PLL phaselocked loop device configures；
After step 4:FPGA carries out initial configuration whole to 4 PLL phaselocked loop devices, FPGA is waited and is judged whether to connect
The switching for receiving headend equipment updates pulse command: if received, major state machine parses pulse command, according to pulse command
Reselect configuration PLL channel, major state machine according to the frequency point mapping table preset in ROM memory module, and
With lookup table mode, selection switches the register value of frequency point, and using the value as register updated value, when issuing PLL configuration driven
Sequence module, meanwhile, major state machine is updated to PLL configuration driven tfi module transmitter register value requests, and executes step 5；Such as
Fruit does not receive, and thens follow the steps 4；
After step 5:PLL configuration driven tfi module receives register value update request, the control of PLL phaselocked loop device is generated
SPI timing, and configured according to ordered pair PLL phaselocked loop device when control SPI, after configuration successful, returns to completion signal and give
Major state machine；
Step 6: after major state machine receives completion signal, into standby mode and executing step 4.
2. a kind of multifrequency point based on FPGA as described in claim 1 is switched fast output control method, it is characterised in that:
When executing step 4, FPGA is communicated by serial ports with headend equipment, and the headend equipment is PC computer.
3. a kind of multifrequency point based on FPGA as described in claim 1 is switched fast output control method, it is characterised in that: institute
Stating frequency point mapping table includes the frequency of frequency point, the value of register and channel handoff parameter.
4. a kind of multifrequency point based on FPGA as described in claim 1 is switched fast output control method, it is characterised in that: institute
State the model LMX2594 of PLL phaselocked loop device.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1832350A (en) * | 2006-04-14 | 2006-09-13 | 西安电子科技大学 | Multiple carrier-frequency digital frequency source |
| CN101917187A (en) * | 2010-07-16 | 2010-12-15 | 中国兵器工业第二○六研究所 | Stepped frequency signal generation method based on frequency selective output of initialize switch of phase-locked loop |
| CN102073032A (en) * | 2010-11-02 | 2011-05-25 | 中国兵器工业第二○六研究所 | Modular generation method for multi-waveform radar signal |
| CN102097049A (en) * | 2011-03-14 | 2011-06-15 | 昆山精讯电子技术有限公司 | Signal self-adaption device and method for liquid crystal module testing |
| CN102185608A (en) * | 2011-05-12 | 2011-09-14 | 中国兵器工业第二○六研究所 | Method for generating stepped frequency signals based on combination of direct digital synthesis (DDS) and ping-pong phase locked loop |
| CN104320135A (en) * | 2014-11-03 | 2015-01-28 | 成都赛英科技有限公司 | High-purity frequency source |
| CN207968464U (en) * | 2018-05-17 | 2018-10-12 | 石家庄雷迅电子科技有限公司 | Agile frequency source based on high-speed DDS |
-
2018
- 2018-12-19 CN CN201811555169.8A patent/CN109656857A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1832350A (en) * | 2006-04-14 | 2006-09-13 | 西安电子科技大学 | Multiple carrier-frequency digital frequency source |
| CN101917187A (en) * | 2010-07-16 | 2010-12-15 | 中国兵器工业第二○六研究所 | Stepped frequency signal generation method based on frequency selective output of initialize switch of phase-locked loop |
| CN102073032A (en) * | 2010-11-02 | 2011-05-25 | 中国兵器工业第二○六研究所 | Modular generation method for multi-waveform radar signal |
| CN102097049A (en) * | 2011-03-14 | 2011-06-15 | 昆山精讯电子技术有限公司 | Signal self-adaption device and method for liquid crystal module testing |
| CN102185608A (en) * | 2011-05-12 | 2011-09-14 | 中国兵器工业第二○六研究所 | Method for generating stepped frequency signals based on combination of direct digital synthesis (DDS) and ping-pong phase locked loop |
| CN104320135A (en) * | 2014-11-03 | 2015-01-28 | 成都赛英科技有限公司 | High-purity frequency source |
| CN207968464U (en) * | 2018-05-17 | 2018-10-12 | 石家庄雷迅电子科技有限公司 | Agile frequency source based on high-speed DDS |
Non-Patent Citations (1)
| Title |
|---|
| 吴厚航: "《深入浅出玩转FPGA（第2版）》", 31 July 2013 * |
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Application publication date: 20190419 |