CN114244909A - Protocol conversion circuit and related device - Google Patents
Protocol conversion circuit and related device Download PDFInfo
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- CN114244909A CN114244909A CN202111545978.2A CN202111545978A CN114244909A CN 114244909 A CN114244909 A CN 114244909A CN 202111545978 A CN202111545978 A CN 202111545978A CN 114244909 A CN114244909 A CN 114244909A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
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Abstract
The embodiment of the invention provides a protocol conversion circuit, which comprises a transceiver circuit module, a register, an interface circuit module and a control circuit module, wherein the transceiver circuit module comprises a first interface circuit and a second interface circuit; the receiving and transmitting circuit module is used for being in communication connection with the computer terminal; the register is used for storing data; the interface circuit module is used for generating an MIPI-RFFE protocol command sequence and is in communication connection with a plurality of external mobile terminals; the control circuit module is used for controlling the working state of the transceiver circuit module, generating a UART read-write command according to the working state, and performing read-write operation on the plurality of registers according to the UART read-write command so as to realize that the computer terminal accesses and controls the mobile terminal through the interface circuit module. The embodiment of the invention also provides test equipment. The protocol conversion circuit and the test equipment have simple circuit structures and are easy to test.
Description
Technical Field
The invention relates to the field of interface circuits, in particular to a protocol conversion circuit and test equipment applied to a mobile phone radio frequency front end.
Background
At present, the development of mobile communication technology, and the application of mobile phone radio frequency chip is more and more extensive. The function test of the radio frequency chip of the mobile phone is an important chip test function, wherein the MIPI-RFFE interface is used for controlling the normal work of the radio frequency front-end device of the mobile phone, and the MIPI-RFFE interface is an important test component.
The MIPI-RFFE interface of the related art generally uses a dedicated chip to generate a corresponding control command, so as to control the radio frequency chip of the mobile phone, and further test the function of the radio frequency chip of the mobile phone.
However, the chip dedicated to the MIPI-RFFE interface of the related art requires a customized test board, the circuit of the chip is complex and costly, and it is not easy to dynamically adjust the test command during the test, and the test process is not easy to develop.
Therefore, there is a need to provide a new circuit and apparatus to solve the above problems.
Disclosure of Invention
In view of the above deficiencies of the prior art, the present invention provides a protocol conversion circuit and a test device with simple circuit structure and easy test.
In order to solve the above technical problem, in a first aspect, an embodiment of the present invention provides a protocol conversion circuit, where the protocol is converted into a UART protocol to MIPI-RFFE protocol, and the protocol conversion circuit includes a transceiver circuit module, a register, an interface circuit module, and a control circuit module;
the receiving and transmitting circuit module is used for being in communication connection with an external computer terminal so as to realize serial port software data communication with the computer terminal;
the register is used for storing data, and comprises a plurality of registers which are respectively in communication connection with the transceiver circuit module;
the interface circuit module is used for generating an MIPI-RFFE protocol command sequence, and comprises a plurality of interfaces which are respectively in communication connection with a plurality of external mobile terminals so as to realize access and control on the plurality of mobile terminals;
the control circuit modules comprise a plurality of control circuit modules, each control circuit module is in communication connection with one register, and each control circuit module is in communication connection with all the interface circuit modules; the control circuit module is used for controlling the working state of the transceiver circuit module, generating a UART read-write command according to the working state, and performing read-write operation on the plurality of registers according to the UART read-write command so as to realize that the computer terminal accesses and controls the mobile terminal through the interface circuit module;
the input end of the transceiver circuit module is used as the input end of the protocol conversion circuit, and the input end of the transceiver circuit module is used for connecting a serial port software output port of the computer terminal;
the output end of the transceiver circuit module comprises a plurality of first output ends and a plurality of second output ends; each first output end is connected to the first end of a corresponding register;
each second output end is connected to the first input end of a corresponding control circuit module;
the second end of each register is connected to the second input end of a corresponding control circuit module, and the output end of each control circuit module is respectively connected to the input ends of the plurality of interface circuit modules;
the output end of the interface circuit module is used as the output end of the protocol conversion circuit, and the output end of the interface circuit module is used for connecting with the corresponding data interface of the mobile terminal.
Preferably, the transceiver circuit module includes a UART clock generation sub-module, a UART receiving circuit sub-module and a UART transmitting circuit sub-module,
the UART clock generating submodule is used for generating a synchronous clock;
the UART receiving circuit submodule is connected with the UART clock generating submodule and used for synchronizing a data signal input by a serial port software output port of the computer terminal through the synchronous clock and sending the synchronized data signal to the UART sending circuit submodule;
and the UART sending circuit submodule is used for sending the synchronized data signal to the register connected with the UART sending circuit submodule.
Preferably, the frequency of the synchronous clock is 9.6KHz, and the UART baud rate of the transceiver circuit module is 9600 bps.
Preferably, the control circuit module is specifically configured to decode a read-write address in the UART read-write command and generate a corresponding address chip selection signal; the address chip selection signal is used for selecting the corresponding register so as to write or read data corresponding to the read-write address into or from the register.
Preferably, the UART read-write command includes a read command and a write command,
the read command comprises a read command start sequence, read-write addresses of registers corresponding to the read command and read data sent to the control circuit module by the transceiver circuit module, the read command start sequence is arranged in a 0XF5 field, the read-write addresses of the registers corresponding to the read command are arranged in a field after the sorting of the 0XF5 field, and the read data are arranged in two fields after the sorting of the 0XF5 field;
the write command comprises a write command start sequence, a read-write address of a register corresponding to the write command and write data which are sequentially arranged, the write command start sequence is arranged in a 0xFA field, the read-write address of the register corresponding to the write command is arranged in a field after the 0xFA field is sequenced, and the write data is arranged in two fields after the 0xFA field is sequenced.
Preferably, the number of the interface circuit modules is 4, the number of the control circuit modules is 4, and the number of the registers is 4.
Preferably, the MIPI-RFFE protocol command sequence includes 8 types, and data of the MIPI-RFFE protocol command sequence is dynamically configurable.
In a second aspect, an embodiment of the present invention provides a test apparatus, which includes the above protocol conversion circuit provided by the embodiment of the present invention.
Preferably, the test equipment further comprises a field programmable gate array development board, and the protocol conversion circuit is arranged on the field programmable gate array development board.
Compared with the prior art, the protocol conversion circuit and the test equipment are in communication connection with an external computer terminal through the transceiving circuit module, and data are stored through the register; the control circuit module controls the working state of the transceiver circuit module; generating a UART read-write command according to the working state, and performing read-write operation on a plurality of registers according to the UART read-write command so as to realize that the computer terminal accesses and controls the mobile terminal through the interface circuit module; the interface circuit module generates an MIPI-RFFE protocol command sequence and is in communication connection with a plurality of external mobile terminals so as to access and control the mobile terminals. The circuit structure of the protocol conversion circuit is simple, the special chip function of the MIPI-RFFE interface can be realized, and the MIPI-RFFE protocol command sequence can be generated through the interface circuit module to realize the test function adjustment, so that the protocol conversion circuit and the test equipment are easy to test.
Drawings
The present invention will be described in detail below with reference to the accompanying drawings. The foregoing and other aspects of the invention will become more apparent and more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings. In the drawings, there is shown in the drawings,
fig. 1 is a diagram of an application circuit structure of a protocol conversion circuit according to an embodiment of the present invention;
fig. 2 is a circuit configuration diagram of a transceiver circuit module of the protocol conversion circuit according to the embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings.
The embodiments/examples described herein are specific embodiments of the present invention, are intended to be illustrative of the concepts of the present invention, are intended to be illustrative and exemplary, and should not be construed as limiting the embodiments and scope of the invention. In addition to the embodiments described herein, those skilled in the art will be able to employ other technical solutions which are obvious based on the disclosure of the claims and the specification of the present application, and these technical solutions include those which make any obvious replacement or modification of the embodiments described herein, and all of which are within the scope of the present invention.
The invention provides a protocol conversion circuit 100. The protocol is converted into a UART protocol to MIPI-RFFE protocol. The UART protocol is a protocol applied to a computer terminal. The MIPI-RFFE protocol is a protocol applied to a radio frequency front-end interface of a mobile phone. Referring to fig. 1, fig. 1 is a circuit diagram of an application of a novel protocol conversion circuit 100 according to an embodiment of the present invention.
The protocol conversion circuit 100 includes a transceiver circuit module 1, a register 2, an interface circuit module 3, and a control circuit module 4.
The transceiver circuit module 1 is used for being in communication connection with an external computer terminal PC so as to realize data communication with serial port software of the computer terminal PC.
Referring to fig. 2, fig. 2 is a circuit structure diagram of a transceiver circuit module 1 of a protocol conversion circuit 100 according to an embodiment of the present invention. Specifically, the transceiver module 1 includes a UART clock generation sub-module 11, a UART receiving circuit sub-module 12, and a UART transmitting circuit sub-module 13.
The UART clock generation submodule 11 is configured to generate a synchronous clock.
The UART receiving circuit submodule 12 is connected to the UART clock generating submodule 11, and is configured to synchronize a data signal input from a serial port software output port of the computer terminal PC with the synchronous clock, and send the synchronized data signal to the UART sending circuit submodule 13.
In this embodiment, the frequency of the synchronous clock is 9.6KHz, and the UART baud rate of the transceiver circuit module 1 is 9600 bps. The synchronous clock and the UART baud rate are respectively set to be 9.6KHz and 9600bps, so that the circuit efficiency of the transceiver circuit module 1 is high under the condition of low power consumption.
The UART transmitting circuit submodule 13 is configured to transmit the synchronized data signal to the register 2 connected thereto.
The register 2 is used to store data. The register 2 comprises a plurality of registers and is respectively connected with the transceiver circuit module 1 in a communication way.
In the present invention, a plurality means the exclusion of one, that is, a plurality means two or more.
The interface circuit module 3 is used for generating an MIPI-RFFE protocol command sequence, and the interface circuit module 3 includes a plurality of interfaces and is respectively in communication connection with a plurality of external mobile terminals TM, so as to access and control the plurality of mobile terminals TM. The data of the MIPI-RFFE protocol command sequence is dynamically configurable. The interface circuit module 3 generates an MIPI-RFFE protocol command sequence to realize test function adjustment, so that the protocol conversion circuit 100 of the present invention is easy to test.
The MIPI-RFFE protocol command sequence includes 8 kinds. Specifically, the MIPI-RFFE protocol command sequence includes a Masked Write command sequence, a Register 0Write command sequence, a Register Read command sequence, an Extended Register Write Long command sequence, and an Extended Register Read Long command sequence.
The control circuit module 4 is configured to control a working state of the transceiver circuit module 1, generate a UART read-write command according to the working state, and perform read-write operation on the plurality of registers 2 according to the UART read-write command, so that the computer terminal PC accesses and controls the mobile terminal TM through the interface circuit module 3.
The control circuit module 4 comprises a plurality of control circuit modules 4, each control circuit module 4 is in communication connection with one register 2, and each control circuit module 4 is in communication connection with all the interface circuit modules 3.
The control circuit module 4 is specifically configured to decode a read-write address in the UART read-write command and generate a corresponding address chip select signal; the address chip select signal is used to select the corresponding register 2, so as to write or read data corresponding to the read/write address into or from the register 2.
The UART read-write command comprises a read command and a write command.
The read command includes the read command start sequence arranged in proper order, the read-write address of the register 2 corresponding to the read command and the read-write address of the control circuit module 4 are sent to the read data of the control circuit module 4, the read command start sequence is set in the 0XF5 field, the read-write address of the register 2 corresponding to the read command is set in the last field of the sorting of the 0XF5 field, and the read data is set in the two fields of the sorting of the 0XF5 field.
The protocol conversion circuit 100 of the present invention operates in the circuit of the read command as follows:
when the protocol conversion circuit 100 receives a data of 0xF5, it indicates that a read command sequence is entered; the protocol conversion circuit 100 receives a data again, and the data is the read address data of the read command; the protocol conversion circuit 100 sends a data to be read, which is the read data of the read command. Wherein the circuit operates in the 52M clock domain.
The write command comprises a write command start sequence, a read-write address of the register 2 corresponding to the write command and write data which are sequentially arranged, the write command start sequence is arranged in a 0xFA field, the read-write address of the register 2 corresponding to the write command is arranged in a field which is the last field of the 0xFA field after sequencing, and the write data is arranged in two fields of the 0xFA field after sequencing.
The protocol conversion circuit 100 of the present invention operates in the circuit of the write command as follows: when the protocol conversion circuit 100 receives a data of 0xFA, it indicates entering a write command sequence; the protocol conversion circuit 100 receives a data again, and the data is the write address data of the write command; the protocol conversion circuit 100 receives a data again, and the data is the write data of the write command. This circuit operates in the 52M clock domain.
The UART read-write command specifies that external serial software of the computer terminal PC must read and write the MIPI-RFFE control register according to the sequence of the read command and the write command, thereby completing the MIPI-RFFE protocol command sequence of the interface circuit module 3 to output external multiple mobile terminals TM.
The serial port software python of the computer terminal PC is realized by calling a third-party serial library to be used as UART serial port communication. The specific technical method is to create a data.txt text to store the MIPI-RFFE protocol command sequence to be transmitted. Specific signals in the MIPI-RFFE protocol communication process are stored in an out1.txt text after software operation is finished.
The control circuit module 4 controls the register value of the register 2. When the value of the command register set in the register 2 is changed, the interface circuit module 3 starts to send the MIPI-RFFE protocol command sequence to the mobile terminal TM, thereby implementing access and control on the mobile terminal TM. The working process enables the protocol conversion circuit 100 to realize the function of the conversion circuit, and the test of the mobile terminal TM is realized.
It should be noted that the circuit module 1, the register 2, the interface circuit module 3, and the control circuit module 4 adopted in the present invention all adopt circuit modules and components commonly used in the art, wherein the logic realized by the circuit module 1, the register 2, the interface circuit module 3, and the control circuit module 4 has self-contained program logic, but these programs are existing programs carried by the device itself, and these existing programs only need to initially set parameters of the programs when in use, but a user does not need to change and adjust the programs, and detailed description is omitted.
The circuit connection relationship of the protocol conversion circuit 100 is as follows:
the input end of the transceiver circuit module 1 is used as the input end of the protocol conversion circuit 100, and the input end of the transceiver circuit module 1 is used for connecting a serial port software output port of the computer terminal PC.
The output terminal of the transceiver module 1 includes a plurality of first output terminals and a plurality of second output terminals. Each of the first output terminals is connected to a first terminal of a corresponding one of the registers 2.
Each of the second output terminals is connected to the first input terminal of a corresponding one of the control circuit modules 4.
The second end of each register 2 is connected to the second input end of a corresponding one of the control circuit modules 4, and the output end of each control circuit module 4 is connected to the input ends of the plurality of interface circuit modules 3, respectively.
The output end of the interface circuit module 3 is used as the output end of the protocol conversion circuit 100, and the output end of the interface circuit module 3 is used for connecting the corresponding data interface of the mobile terminal TM.
From the circuit structure above, it follows: the protocol conversion circuit 100 of the present invention has a simple circuit structure. Namely, the protocol conversion circuit 100 can realize a special chip function for the MIPI-RFFE interface, so that a special chip for the MIPI-RFFE interface is not required, and the technical scheme has a simple circuit and a low cost. More preferably, each circuit module can be optimized according to the actual needs of the test without being limited by the functions and performances of a special chip, and the application is wider.
In this embodiment, the number of the interface circuit blocks 3 is 4, the number of the control circuit blocks 4 is 4, and the number of the registers 2 is 4. That is, the protocol conversion circuit 100 supports 4 mobile terminal TM connections for testing. Of course, the number of the interface circuit block 3, the control circuit block 4, and the register 2 is not limited thereto. The number of each module can be configured according to actual test requirements.
The present invention also provides a test apparatus including the protocol conversion circuit 100.
The test equipment is realized by a Field Programmable Gate Array (FPGA) development board. Specifically, the test equipment further comprises a field programmable gate array development board. The protocol conversion circuit 100 is disposed on the field programmable gate array development board. The field programmable gate array development board comprises a field programmable gate array FPGA. In this embodiment, the field programmable gate array FPGA is an AX515 model of the blackland ALTERA series. The FPGA is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), which not only solves the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited. The test equipment adopts a field programmable gate array FPGA to develop and realize the protocol conversion circuit 100, which is beneficial to the development and operation of tests.
Compared with the prior art, the protocol conversion circuit and the test equipment are in data connection with an external computer terminal through the transceiving circuit module, and store data through the register; the control circuit module controls the working state of the transceiver circuit module; generating a UART read-write command according to the working state, and performing read-write operation on a plurality of registers according to the UART read-write command so as to realize that the computer terminal accesses and controls the mobile terminal through the interface circuit module; the interface circuit module generates an MIPI-RFFE protocol command sequence and is in data connection with a plurality of external mobile terminals so as to access and control the mobile terminals. The circuit structure of the protocol conversion circuit is simple, the special chip function of the MIPI-RFFE interface can be realized, and the MIPI-RFFE protocol command sequence can be generated through the interface circuit module to realize the test function adjustment, so that the protocol conversion circuit and the test equipment are easy to test.
It should be noted that the above-mentioned embodiments described with reference to the drawings are only intended to illustrate the present invention and not to limit the scope of the present invention, and it should be understood by those skilled in the art that modifications and equivalent substitutions can be made without departing from the spirit and scope of the present invention. Furthermore, unless the context indicates otherwise, words that appear in the singular include the plural and vice versa. Additionally, all or a portion of any embodiment may be utilized with all or a portion of any other embodiment, unless stated otherwise.
Claims (9)
1. A protocol conversion circuit is characterized in that the protocol is converted into a UART protocol-to-MIPI-RFFE protocol, and the protocol conversion circuit comprises a transceiving circuit module, a register, an interface circuit module and a control circuit module;
the receiving and transmitting circuit module is used for being in communication connection with an external computer terminal so as to realize serial port software data communication with the computer terminal;
the register is used for storing data, and comprises a plurality of registers which are respectively in communication connection with the transceiver circuit module;
the interface circuit module is used for generating an MIPI-RFFE protocol command sequence, and comprises a plurality of interfaces which are respectively in communication connection with a plurality of external mobile terminals so as to realize access and control on the plurality of mobile terminals;
the control circuit modules comprise a plurality of control circuit modules, each control circuit module is in communication connection with one register, and each control circuit module is in communication connection with all the interface circuit modules; the control circuit module is used for controlling the working state of the transceiver circuit module, generating a UART read-write command according to the working state, and performing read-write operation on the plurality of registers according to the UART read-write command so as to realize that the computer terminal accesses and controls the mobile terminal through the interface circuit module;
the input end of the transceiver circuit module is used as the input end of the protocol conversion circuit, and the input end of the transceiver circuit module is used for connecting a serial port software output port of the computer terminal;
the output end of the transceiver circuit module comprises a plurality of first output ends and a plurality of second output ends; each first output end is connected to the first end of a corresponding register;
each second output end is connected to the first input end of a corresponding control circuit module;
the second end of each register is connected to the second input end of a corresponding control circuit module, and the output end of each control circuit module is respectively connected to the input ends of the plurality of interface circuit modules;
the output end of the interface circuit module is used as the output end of the protocol conversion circuit, and the output end of the interface circuit module is used for connecting with the corresponding data interface of the mobile terminal.
2. The protocol conversion circuit of claim 1, wherein the transceiver circuit module comprises a UART clock generation sub-module, a UART receiving circuit sub-module, and a UART transmitting circuit sub-module,
the UART clock generating submodule is used for generating a synchronous clock;
the UART receiving circuit submodule is connected with the UART clock generating submodule and used for synchronizing a data signal input by a serial port software output port of the computer terminal through the synchronous clock and sending the synchronized data signal to the UART sending circuit submodule;
and the UART sending circuit submodule is used for sending the synchronized data signal to the register connected with the UART sending circuit submodule.
3. The protocol conversion circuit of claim 2, wherein the frequency of the synchronous clock is 9.6KHz, and the UART baud rate of the transceiver circuit module is 9600 bps.
4. The protocol conversion circuit according to claim 1, wherein the control circuit module is specifically configured to decode a read/write address in the UART read/write command and generate a corresponding address chip select signal; the address chip selection signal is used for selecting the corresponding register so as to write or read data corresponding to the read-write address into or from the register.
5. The protocol conversion circuit of claim 1, wherein the UART read-write command comprises a read command and a write command,
the read command comprises a read command start sequence, read-write addresses of registers corresponding to the read command and read data sent to the control circuit module by the transceiver circuit module, the read command start sequence is arranged in a 0XF5 field, the read-write addresses of the registers corresponding to the read command are arranged in a field after the sorting of the 0XF5 field, and the read data are arranged in two fields after the sorting of the 0XF5 field;
the write command comprises a write command start sequence, a read-write address of a register corresponding to the write command and write data which are sequentially arranged, the write command start sequence is arranged in a 0xFA field, the read-write address of the register corresponding to the write command is arranged in a field after the 0xFA field is sequenced, and the write data is arranged in two fields after the 0xFA field is sequenced.
6. The protocol conversion circuit of claim 1, wherein the interface circuit block comprises 4, the control circuit block comprises 4, and the register comprises 4.
7. The protocol conversion circuit of claim 1, wherein the MIPI-RFFE protocol command sequence comprises 8, and wherein data of the MIPI-RFFE protocol command sequence is dynamically configurable.
8. A test apparatus comprising a protocol conversion circuit according to any one of claims 1 to 7.
9. The test apparatus of claim 8, further comprising a field programmable gate array development board, the protocol conversion circuit being provided to the field programmable gate array development board.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111545978.2A CN114244909B (en) | 2021-12-16 | 2021-12-16 | Protocol conversion circuit and related device |
| PCT/CN2022/132869 WO2023109429A1 (en) | 2021-12-16 | 2022-11-18 | Protocol conversion circuit and related device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111545978.2A CN114244909B (en) | 2021-12-16 | 2021-12-16 | Protocol conversion circuit and related device |
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| CN114244909A true CN114244909A (en) | 2022-03-25 |
| CN114244909B CN114244909B (en) | 2023-05-02 |
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| CN202111545978.2A Active CN114244909B (en) | 2021-12-16 | 2021-12-16 | Protocol conversion circuit and related device |
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| WO (1) | WO2023109429A1 (en) |
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| CN117956047A (en) * | 2024-03-25 | 2024-04-30 | 深圳飞骧科技股份有限公司 | Digital circuit and radio frequency device for multiple MIPI-RFFE interfaces |
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| CN117956047B (en) * | 2024-03-25 | 2024-06-18 | 深圳飞骧科技股份有限公司 | Digital circuit and radio frequency device for multiple MIPI-RFFE interfaces |
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| Publication number | Publication date |
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| WO2023109429A1 (en) | 2023-06-22 |
| CN114244909B (en) | 2023-05-02 |
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