CN112269123B - Universal configurable chip test circuit - Google Patents

Universal configurable chip test circuit Download PDF

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Publication number
CN112269123B
CN112269123B CN202011108514.0A CN202011108514A CN112269123B CN 112269123 B CN112269123 B CN 112269123B CN 202011108514 A CN202011108514 A CN 202011108514A CN 112269123 B CN112269123 B CN 112269123B
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chip
test
tested
main control
control fpga
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CN112269123A (en
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李鑫
曾永红
晋超超
徐艺轩
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Tianjin Jinhang Computing Technology Research Institute
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Tianjin Jinhang Computing Technology Research Institute
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31721—Power aspects, e.g. power supplies for test circuits, power saving during test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318314—Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention belongs to the technical field of hardware design, and particularly relates to a universal configurable chip test circuit, which comprises: the test chip socket, the master control FPGA and the peripheral interface circuits of various communication protocols; the test chip socket is used as a carrier of a tested chip to realize communication between the tested chip and a peripheral interface circuit and communication between the tested chip and the main control FPGA; the master control FPGA is responsible for generating different test vectors and communication protocols according to the functions and types of the chip to be tested and switching a test interface corresponding to the chip to be tested in the peripheral interface circuit; the peripheral interface circuit of the multiple communication protocols comprises peripheral test interfaces of the multiple communication protocols and is used for realizing test physical access of different chips to be tested. The invention effectively solves the problem that different chip tests need to carry out test board card design again, is suitable for different types of chip test systems with the same package, and can effectively test the functions of communication chips.

Description

Universal configurable chip test circuit
Technical Field
The invention belongs to the technical field of hardware design, and particularly relates to a universal configurable chip test circuit.
Background
With the rapid development of the integrated circuit industry, the feature size of a chip is smaller and smaller, the integration scale is larger and larger, and the realized functions are more and more complex, so that the integrated circuit chip is widely applied to various industries and becomes an indispensable part in human life. However, unlike the rapid development of the chip industry, the development of the chip testing method has not advanced with the increase of the complexity of the chip. In the face of chips with increasing functions and increasingly complex architectures, how to reduce the test cost in the face of chips with different functions has become an increasing concern in the industry.
The traditional test method mainly adopts a single circuit to test each function one by one according to the functions of a chip, and a test circuit usually adopts a CPU as a test excitation source and communicates with the chip to be tested through a peripheral communication interface to test the chip. The method is often limited by a CPU peripheral interface, and when different chips need to be tested, a test board card can only be redesigned, so that the cost of the system is increased invisibly.
Therefore, a circuit which has strong universality, can realize various communication protocol capabilities and can test different functional chips with the same package is required to be designed, the chips with the same package can be tested without newly designing a board card, the chip testing efficiency is effectively improved, and the research and development cost is saved.
Disclosure of Invention
Technical problem to be solved
The technical problem to be solved by the invention is as follows: how to test the chips with the same package without redesigning the board card, the chip testing efficiency is effectively improved, and the research and development cost is saved.
(II) technical scheme
To solve the above technical problem, the present invention provides a universal configurable chip test circuit, which includes: the test chip socket, the master control FPGA and the peripheral interface circuits of various communication protocols;
the test chip socket is used as a carrier of a tested chip to realize communication between the tested chip and a peripheral interface circuit and between the tested chip and the main control FPGA;
the master control FPGA is responsible for generating different test vectors and communication protocols according to the functions and types of the chip to be tested and switching a test interface corresponding to the chip to be tested in the peripheral interface circuit;
the peripheral interface circuit of the multiple communication protocols comprises peripheral test interfaces of the multiple communication protocols and is used for realizing test physical access of different chips to be tested.
The universal configurable chip test circuit is a universal configurable chip test circuit board card;
in the chip test circuit board card, a chip is arranged on the chip test circuit board card,
the chip test socket realizes the electrical connection of a chip to be tested with the main control FPGA and the peripheral interface circuit;
the main control FPGA is used for realizing a corresponding communication protocol according to the function of the chip to be tested; the peripheral test interface circuit is used for selecting a peripheral test interface in the peripheral interface circuit according to the function of the chip to be tested and connecting the peripheral test interface with the test physical channel; the test system is also used for generating a test vector according to the function of the chip to be tested; the test device is used for calling a corresponding communication protocol to send a test vector and receive a test result, and checking whether the function of the chip to be tested is correct or not;
the peripheral interface circuit is used for providing a test physical channel of a corresponding communication protocol.
The chip test circuit board card also comprises a peripheral power supply control module which is used for switching according to the power supply voltage and the power supply pins of different chips to be tested and ensuring that the power supply of the chips to be tested is correct.
The master control FPGA is internally integrated with a plurality of bus controllers including UART, SPI, I2C, SRIO, PCI-E, ISA and the like.
The chip to be tested and the main control FPGA adopt a full connection mode, namely all pins of the chip to be tested are connected into the main control FPGA, the main control FPGA carries out customized configuration according to functions to be tested, and corresponding test physical channels are selectively connected;
the master control FPGA selects a communication protocol according to a function to be tested and generates a test vector, the test vector is converted into a data packet which accords with the corresponding communication protocol and is sent to the chip to be tested, and the chip to be tested sends data through a peripheral test interface;
and the main control FPGA receives the test data returned by the peripheral test interface, decodes the test data through a built-in communication protocol and compares the decoded test data to obtain a test result.
In the chip test socket, the master control FPGA, the peripheral interface circuit and the peripheral power supply control module, the connection relationship among the modules is as follows:
(1) All pins of the chip to be tested need to be respectively connected with the main control FPGA and the peripheral power supply control module;
(2) A control selection pin of the peripheral power supply control module is connected with the main control FPGA;
(3) The data receiving end and the data sending end of the peripheral interface circuit are respectively connected with the main control FPGA, and the receiving and sending physical ends of the peripheral interface circuit with the same communication protocol are connected to form a self-sending and self-receiving loop test mode.
The main control FPGA is used as a core module of a chip test circuit and is used for electric communication between a chip to be tested and a peripheral interface circuit, generation of test vectors, collection of test results, configuration of a communication protocol and power supply control work of the chip to be tested;
the peripheral interface circuit is configured into a self-sending and self-receiving loop test channel, and data sent by the chip to be tested through the main control FPGA is sent back to the main control FPGA;
the peripheral power supply control module connects a power supply with the chip to be tested through a multi-way switch, the gating function of the power supply control module is controlled by the main control FPGA, and the main control FPGA determines which way of switch is switched on, so that the power supply is connected with a certain pin of the chip to be tested.
Wherein, master control FPGA has integrateed a plurality of submodule pieces as circuit core module, includes: the system comprises a time sequence control module, a configurable communication protocol generation module, a clock generation module, a peripheral interface gating module and a power control module; wherein, the first and the second end of the pipe are connected with each other,
the time sequence control module is used for realizing time sequence control of interface communication between the chip to be tested and the main control FPGA and the connection and control functions of all modules in the main control FPGA;
the configurable communication protocol generation module internally comprises: the system comprises a clock synchronization module, a data storage RAM module, a protocol configuration module, a logic control module, a serial-parallel conversion module and a communication protocol generation module, wherein the clock synchronization module is used for converting various serial or parallel communication protocols and receiving and transmitting data and supporting ISA (industry standard architecture) bus, SRIO (serial input output), PCI-E (peripheral component interconnect-express) bus, I2C (inter-integrated circuit), SPI (serial input output) and UART (universal asynchronous receiver/transmitter) communication protocols;
the clock generation module consists of a plurality of configured PLL circuits in the master control FPGA, and is used for receiving external crystal oscillator input, scheduling the internal PLL frequency division circuits to generate different clock outputs according to the clock requirements of different chips to be tested and using the different clock outputs as the reference clock of the test circuit;
the peripheral interface gating module is used for gating a receiving and transmitting pin of the chip to be tested and a peripheral interface circuit pin of a corresponding communication protocol according to the communication protocol to be configured so as to realize a test access of data;
and the power supply control module is used for controlling the power supply control module on the board according to the voltage required by the chip to be tested and the position of the specific power supply pin, gating the corresponding multi-way switch channel and connecting the correct power supply with the corresponding power supply pin of the chip to be tested.
The power supply control module is used for receiving a control signal transmitted by the main control FPGA, gating a corresponding channel according to the control signal and connecting a power supply with a power supply pin of the chip to be tested; the power supply control module comprises a group of multi-way switches, the input ends of the switches are connected with the outputs of different power supplies, and the output ends of the switches are connected with all pins of a chip to be tested; the routing control end is connected with the main control FPGA, the main control FPGA decodes the routing control end, and the corresponding gating input end is connected with the output end.
The testing process of the chip testing circuit comprises the following steps:
(1) After the power is on, firstly loading a test program by the main control FPGA, configuring the main control FPGA according to a communication protocol required by the test, and loading the corresponding communication protocol when the main control FPGA is in a corresponding working mode;
(2) The main control FPGA sends a command to the power supply control module according to the power supply requirement of the chip to be tested, and a power supply channel is gated;
(3) The main control FPGA establishes a test physical channel according to the type and the pin position of the chip to be tested;
(4) Performing basic test to test whether a fault exists between system buses, writing configuration data into a configuration register of a chip to be tested by the main control FPGA, and checking whether the configuration of a data bus between the main control FPGA and the chip to be tested is correct;
(5) The chip function test is carried out, the chip to be tested carries out the communication protocol test through the main control FPGA, the main control FPGA writes specific test data into the chip to be tested, the chip to be tested is sent to the peripheral test interface according to the corresponding communication protocol, the main control FPGA decodes the data after receiving the data sent by the peripheral interface, compares the data and tests whether the chip has the communication protocol problem.
(III) advantageous effects
The invention provides a universal configurable chip test circuit, which is realized by a set of configurable test vector generation circuit system capable of operating various communication protocols, takes a large-scale FPGA chip as a core and is realized by matching with a peripheral transceiver circuit, is mainly used for testing interface chips with the same encapsulation and different communication protocols, ensures the correct and reliable communication function of the interface chips, and is particularly suitable for testing chips with various communication protocols at the same time.
Compared with the prior art, the invention has the following beneficial effects:
(1) The invention effectively solves the problem that different chip tests need to carry out test board card design again, is suitable for different types of chip test systems with the same package, and can effectively test the functions of communication chips.
(2) The invention realizes a plurality of communication protocols and test vector generating systems in the master control FPGA, and can generate test vectors without external excitation. The cost of the test board card is saved.
(3) The invention designs the power supply control circuit, which can provide correct voltage input for chips with different power supply voltages and power supply pins and has good adaptability and flexibility.
Drawings
FIG. 1 is a diagram of a generic configurable chip test circuit architecture.
Fig. 2 is a main control FPGA module architecture diagram.
Fig. 3 is a diagram of a configurable communication protocol generation module architecture.
Fig. 4 is a test flow chart.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
To solve the problems in the prior art, the present invention provides a universal configurable chip test circuit, as shown in fig. 1, the chip test circuit includes: the test chip socket, the master control FPGA and the peripheral interface circuits of various communication protocols;
the test chip socket is used as a carrier of a tested chip to realize communication between the tested chip and a peripheral interface circuit and between the tested chip and the main control FPGA;
the master control FPGA is responsible for generating different test vectors and communication protocols according to the functions and types of the chip to be tested and switching a test interface corresponding to the chip to be tested in the peripheral interface circuit;
the peripheral interface circuit of the multiple communication protocols comprises peripheral test interfaces of the multiple communication protocols and is used for realizing test physical access of different chips to be tested.
Through the test circuit, the test of chips with the same encapsulation and various different functions can be completed on one test board card, the test circuit does not need to be redesigned, the time is saved, and the efficiency is improved.
The universal configurable chip test circuit is a universal configurable chip test circuit board card;
in the chip test circuit board card, a chip is arranged on the chip test circuit board card,
the chip test socket realizes the electrical connection of the chip to be tested with the main control FPGA and the peripheral interface circuit;
the main control FPGA is used for realizing a corresponding communication protocol according to the function of the chip to be tested; the peripheral test interface circuit is used for selecting a peripheral test interface in the peripheral interface circuit according to the function of the chip to be tested and connecting the peripheral test interface with the test physical channel; the test system is also used for automatically generating a test vector according to the function of the chip to be tested; the test device is used for calling a corresponding communication protocol to send a test vector and receive a test result, and checking whether the function of the chip to be tested is correct or not;
the peripheral interface circuit is used for providing a test physical channel of a corresponding communication protocol.
The chip test circuit board card also comprises a peripheral power supply control module which is used for flexibly switching according to the power supply voltage and the power supply pins of different chips to be tested so as to ensure that the power supply of the chips to be tested is correct.
The master control FPGA is internally integrated with various bus controllers including a UART, an SPI, an I2C, an SRIO, a PCI-E, an ISA and the like.
The chip to be tested and the main control FPGA adopt a full connection mode, namely all pins of the chip to be tested are connected into the main control FPGA, the main control FPGA carries out customized configuration according to functions to be tested, and corresponding test physical channels are selectively connected;
the main control FPGA selects a communication protocol according to a function to be tested and automatically generates a test vector, the test vector is converted into a data packet conforming to the corresponding communication protocol and is sent to a chip to be tested, and the chip to be tested sends data through a peripheral test interface;
and the main control FPGA receives the test data returned by the peripheral test interface, decodes the test data through a built-in communication protocol and compares the decoded test data to obtain a test result.
In the chip test socket, the main control FPGA, the peripheral interface circuit and the peripheral power supply control module, the connection relationship among the modules is as follows:
(1) All pins of the chip to be tested need to be respectively connected with the main control FPGA and the peripheral power supply control module;
(2) A control selection pin of the peripheral power supply control module is connected with the main control FPGA;
(3) The data receiving end and the data sending end of the peripheral interface circuit are respectively connected with the master control FPGA, and the receiving and sending physical ends of the peripheral interface circuit with the same communication protocol are connected to form a self-sending and self-receiving loop test mode.
The main control FPGA is used as a core module of a chip test circuit and is used for electric communication between a chip to be tested and a peripheral interface circuit, generation of test vectors, collection of test results, automatic configuration of a communication protocol and power supply control work of the chip to be tested;
the peripheral interface circuit is configured into a self-sending and self-receiving loop test channel, and data sent by the chip to be tested through the main control FPGA is sent back to the main control FPGA;
the peripheral power supply control module connects a power supply with the chip to be tested through a multi-way switch, the gating function of the power supply control module is controlled by the main control FPGA, and the main control FPGA determines which way of switch is switched on, so that the power supply is connected with a certain pin of the chip to be tested.
Wherein, master control FPGA has integrateed a plurality of submodule pieces as circuit core module, includes: the system comprises a time sequence control module, a configurable communication protocol generation module, a clock generation module, a peripheral interface gating module and a power control module; wherein the content of the first and second substances,
the time sequence control module is used for realizing time sequence control of interface communication between the chip to be tested and the main control FPGA and the connection and control functions of all modules in the main control FPGA;
the configurable communication protocol generation module internally comprises: the system comprises a clock synchronization module, a data storage RAM module, a protocol configuration module, a logic control module, a serial-parallel conversion module and a communication protocol generation module, wherein the clock synchronization module is used for converting various serial or parallel communication protocols and receiving and transmitting data and supporting ISA (industry standard architecture) bus, SRIO (serial peripheral input output), PCI-E (peripheral component interconnect express), I2C (inter-integrated circuit), SPI (serial peripheral interface) and UART (universal asynchronous receiver/transmitter) communication protocols;
the clock generation module consists of a plurality of configured PLL circuits in the master control FPGA, and is used for scheduling the internal PLL frequency division circuits to generate different clock outputs as reference clocks of the test circuit according to the clock requirements of different chips to be tested by receiving external crystal oscillator input;
the peripheral interface gating module is used for gating a receiving and transmitting pin of the chip to be tested and a peripheral interface circuit pin of a corresponding communication protocol according to the communication protocol to be configured so as to realize a test access of data;
and the power supply control module is used for controlling the power supply control module on the board according to the voltage required by the chip to be tested and the position of the specific power supply pin, gating the corresponding multi-way switch channel and connecting the correct power supply with the corresponding power supply pin of the chip to be tested.
The power supply control module is used for receiving a control signal transmitted by the main control FPGA, gating a corresponding channel according to the control signal and connecting a power supply with a power supply pin of the chip to be tested; the power supply control module comprises a group of multi-way switches, the input ends of the switches are connected with the outputs (5V, 3.3V, 1.8V, 1.5V, 1.2V and the like) of different power supplies, and the output ends of the switches are connected with all pins of the chip to be tested; the routing control end is connected with the main control FPGA, the main control FPGA decodes the routing control end, and the corresponding gating input end is connected with the output end.
The testing process of the chip testing circuit comprises the following steps:
(1) After the power is on, firstly loading a test program by the main control FPGA, configuring the main control FPGA according to a communication protocol required by the test, and loading the corresponding communication protocol when the main control FPGA is in a corresponding working mode;
(2) The main control FPGA sends a command to the power supply control module according to the power supply requirement of the chip to be tested, and a power supply channel is gated;
(3) The main control FPGA establishes a test physical channel according to the type and the pin position of the chip to be tested;
(4) Performing basic test to test whether a fault exists between system buses, writing configuration data into a configuration register of a chip to be tested by the main control FPGA, and checking whether the configuration of a data bus between the main control FPGA and the chip to be tested is correct;
(5) The chip function test is carried out, the chip to be tested carries out the communication protocol test through the main control FPGA, the main control FPGA writes specific test data into the chip to be tested, the chip to be tested is sent to the peripheral test interface according to the corresponding communication protocol, the main control FPGA decodes the data after receiving the data sent by the peripheral interface, compares the data and tests whether the chip has the communication protocol problem.
Example 1
In this embodiment, the specific conditions are as follows:
(one) component structure
The hardware circuit of the invention consists of a universal configurable chip test circuit board card. The whole board card comprises: the chip testing socket comprises a chip testing socket, a main control FPGA, a peripheral interface circuit, a power supply module and a power supply control module. The overall architecture is shown in fig. 1:
the connection relationship among the modules is as follows:
(1) All pins of the chip to be tested need to be connected with the main control FPGA and the power supply control module respectively.
(2) And a control selection pin of the power supply control module is connected with the main control FPGA.
(3) The data receiving end and the data sending end of the peripheral interface circuit are respectively connected with the master control FPGA, and the receiving and sending physical ends of the peripheral interface circuit with the same communication protocol are connected to form a self-sending and self-receiving loop test mode.
The main control FPGA is used as a core module of a test circuit and is responsible for the electrical communication between a chip to be tested and a peripheral interface circuit, the generation of test vectors, the collection of test results, the automatic configuration of a communication protocol and the power supply control work of the chip to be tested; the peripheral interface circuit is configured into a self-sending and self-receiving loop test channel, and data sent by the chip to be tested through the main control FPGA is sent back to the main control FPGA. The power supply control module connects a power supply with the chip to be tested through the multi-way switch, the gating function of the power supply control module is controlled by the main control FPGA, and the main control FPGA determines which way of switch is switched on, so that the connection between the power supply and a certain pin of the chip to be tested is realized.
The main control FPGA serves as a circuit core module, a plurality of sub modules are integrated inside the main control FPGA, and the main control FPGA is explained in detail below.
(1) Main control FPGA module
The main control FPGA is mainly composed of a time sequence control module, a configurable communication protocol generation module, a clock generation module, a peripheral interface gating module and a power control module. The structure diagram is shown in figure 2.
The following will respectively introduce each module of the main control FPGA:
a. time sequence control module
The time sequence control module is responsible for realizing time sequence control of interface communication between the chip to be tested and the main control FPGA, and connection and control functions of all modules in the main control FPGA.
b. Configurable communication protocol generation module
The specific architecture of the configurable communication protocol generation module is shown in fig. 3, and the configurable communication protocol generation module internally includes the following modules: the clock synchronization module, the data storage RAM module, the protocol configuration module, the logic control module, the serial-parallel conversion module and the communication protocol generation module can perform conversion and data receiving and transmitting of various serial or parallel communication protocols and support ISA bus, SRIO, PCI-E, I2C, SPI and UART communication protocols.
c. Clock generation module
The clock generation module is composed of a plurality of configured PLL circuits in the FPGA, and the clock generation module can schedule an internal PLL frequency division circuit to generate different clock outputs according to the clock requirements of different chips to be tested by receiving external crystal oscillator input and is used as a reference clock of the test circuit.
d. Peripheral interface gating module
And the peripheral interface gating module gates the receiving and transmitting pin of the chip to be tested and the peripheral interface circuit pin of the corresponding communication protocol according to the communication protocol to be configured, so as to realize a test access of data.
e. Power supply control module
The power supply control module controls the power supply control module on the board according to the voltage required by the chip to be tested and the specific power supply pin position, gates the corresponding multi-way switch channel, and connects the correct power supply with the corresponding power supply pin of the chip to be tested.
(2) Power supply control module
The power supply control module is mainly used for receiving a control signal transmitted by the main control FPGA and gating a corresponding channel according to the control signal so as to connect a power supply with a power supply pin of the chip to be tested.
The main components of the device are a group of multi-way switches, the input ends of the switches are connected with the outputs (5V, 3.3V, 1.8V, 1.5V, 1.2V and the like) of each power supply, and the output ends of the switches are connected with all pins of a chip to be tested. The route selection control end is connected with the main control FPGA, the main control FPGA carries out decoding, and the corresponding gating input end is connected with the output end.
(II) test flow
The system test flow is shown in fig. 4, and is described in detail as follows:
a. after the system is powered on, firstly, the main control FPGA loads a test program, and configures the main control FPGA according to a communication protocol required by the test, so that the main control FPGA is in a corresponding working mode and loads a corresponding communication protocol.
b. And the main control FPGA sends a command to the power supply control module according to the power supply requirement of the chip to be tested, and gates a power supply channel.
c. And the main control FPGA establishes a test path according to the type and the pin position of the chip to be tested.
d. And performing basic test to test whether a fault exists between the system buses, writing configuration data into a configuration register of the chip to be tested by the main control FPGA, and checking whether the configuration of the data bus between the main control FPGA and the chip to be tested is correct.
e. The chip function test is carried out, the chip to be tested carries out communication protocol test through the main control FPGA, specific test data are written into the main control FPGA chip to be tested, the chip to be tested is sent to the peripheral test interface according to the corresponding communication protocol, the main control FPGA decodes the data after receiving the data sent by the peripheral interface, then the data are compared, and whether the chip has the communication protocol problem or not is tested.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims (1)

1. A universally configurable chip test circuit, the chip test circuit comprising: the test chip socket, the master control FPGA and the peripheral interface circuits of various communication protocols;
the test chip socket is used as a carrier of a tested chip to realize communication between the tested chip and a peripheral interface circuit and between the tested chip and the main control FPGA;
the master control FPGA is responsible for generating different test vectors and communication protocols according to the functions and types of the chip to be tested and switching test interfaces corresponding to the chip to be tested in the peripheral interface circuit;
the peripheral interface circuits of the multiple communication protocols comprise peripheral test interfaces of the multiple communication protocols and are used for realizing test physical access of different chips to be tested;
the universal configurable chip test circuit is a universal configurable chip test circuit board card;
in the chip test circuit board card,
the chip test socket realizes the electrical connection of a chip to be tested with the main control FPGA and the peripheral interface circuit;
the main control FPGA is used for realizing a corresponding communication protocol according to the function of the chip to be tested; the peripheral test interface circuit is used for selecting a peripheral test interface in the peripheral interface circuit according to the function of the chip to be tested and connecting the peripheral test interface with the test physical channel; the test system is also used for generating a test vector according to the function of the chip to be tested; the test system is used for calling a corresponding communication protocol to send a test vector and receive a test result, and checking whether the function of the tested chip is correct or not;
the peripheral interface circuit is used for providing a test physical access of a corresponding communication protocol;
the chip test circuit board card also comprises a peripheral power supply control module which is used for switching according to the power supply voltage and the power supply pins of different chips to be tested so as to ensure that the chips to be tested are correctly powered;
the master control FPGA is internally integrated with a plurality of bus controllers including a UART, an SPI, an I2C, an SRIO, a PCI-E and an ISA;
the chip to be tested and the main control FPGA adopt a full connection mode, namely all pins of the chip to be tested are connected into the main control FPGA, the main control FPGA carries out customized configuration according to functions to be tested, and a corresponding test physical channel is selectively connected;
the master control FPGA selects a communication protocol according to a function to be tested and generates a test vector, the test vector is converted into a data packet conforming to the corresponding communication protocol and is sent to the chip to be tested, and the chip to be tested sends data through a peripheral test interface;
the main control FPGA receives test data returned by the peripheral test interface, decodes the test data through a built-in communication protocol and then compares the decoded test data to obtain a test result;
in the chip test socket, the main control FPGA, the peripheral interface circuit and the peripheral power supply control module, the connection relationship among the modules is as follows:
(1) All pins of the chip to be tested need to be respectively connected with the main control FPGA and the peripheral power supply control module;
(2) A control selection pin of the peripheral power supply control module is connected with the main control FPGA;
(3) The data receiving end and the data sending end of the peripheral interface circuit are respectively connected with the master control FPGA, and the receiving and sending physical ends of the peripheral interface circuit with the same communication protocol are connected to form a self-sending and self-receiving loop test mode;
the main control FPGA is used as a core module of a chip test circuit and is used for electric communication between a chip to be tested and a peripheral interface circuit, generation of test vectors, collection of test results, configuration of a communication protocol and power supply control work of the chip to be tested;
the peripheral interface circuit is configured into a self-sending and self-receiving loop test channel, and data sent by the chip to be tested through the main control FPGA is sent back to the main control FPGA;
the peripheral power supply control module connects a power supply with the chip to be tested through a multi-way switch, the gating function of the power supply control module is controlled by the main control FPGA, and the main control FPGA determines which way of switch is switched on to realize the connection of the power supply with a certain pin of the chip to be tested;
the main control FPGA is used as a circuit core module, a plurality of sub-modules are integrated inside the main control FPGA, and the circuit comprises: the system comprises a time sequence control module, a configurable communication protocol generation module, a clock generation module, a peripheral interface gating module and a power control module; wherein the content of the first and second substances,
the time sequence control module is used for realizing time sequence control of interface communication between the chip to be tested and the main control FPGA and connection and control functions of all modules in the main control FPGA;
the configurable communication protocol generation module internally comprises: the system comprises a clock synchronization module, a data storage RAM module, a protocol configuration module, a logic control module, a serial-parallel conversion module and a communication protocol generation module, wherein the clock synchronization module is used for converting various serial or parallel communication protocols and receiving and transmitting data and supporting ISA (industry standard architecture) bus, SRIO (serial peripheral input output), PCI-E (peripheral component interconnect express), I2C (inter-integrated circuit), SPI (serial peripheral interface) and UART (universal asynchronous receiver/transmitter) communication protocols;
the clock generation module consists of a plurality of configured PLL circuits in the master control FPGA, and is used for receiving external crystal oscillator input, scheduling the internal PLL frequency division circuits to generate different clock outputs according to the clock requirements of different chips to be tested and using the different clock outputs as the reference clock of the test circuit;
the peripheral interface gating module is used for gating a receiving and transmitting pin of the chip to be tested and a peripheral interface circuit pin of a corresponding communication protocol according to the communication protocol to be configured so as to realize a test access of data;
the power supply control module is used for controlling the power supply control module on the board according to the voltage required by the chip to be tested and the position of the specific power supply pin, gating the corresponding multi-way switch channel and connecting the correct power supply with the corresponding power supply pin of the chip to be tested;
the power supply control module is used for receiving a control signal transmitted by the main control FPGA, and gating a corresponding channel according to the control signal to connect a power supply with a power supply pin of the chip to be tested; the power supply control module comprises a group of multi-way switches, the input ends of the switches are connected with the outputs of different power supplies, and the output ends of the switches are connected with all pins of a chip to be tested; the routing control end is connected with the main control FPGA, the main control FPGA decodes the routing control end, and the corresponding gating input end is connected with the output end;
the testing process of the chip testing circuit comprises the following steps:
(1) After the power is on, firstly, a test program is loaded by the main control FPGA, the main control FPGA is configured according to a communication protocol required by the test, and the corresponding communication protocol is loaded when the main control FPGA is in a corresponding working mode;
(2) The main control FPGA sends a command to the power supply control module according to the power supply requirement of the chip to be tested, and a power supply channel is gated;
(3) The main control FPGA establishes a test physical channel according to the type and the pin position of the chip to be tested;
(4) Performing basic test to test whether a fault exists between system buses, writing configuration data into a configuration register of a chip to be tested by the main control FPGA, and checking whether the configuration of a data bus between the main control FPGA and the chip to be tested is correct;
(5) The chip function test is carried out, the chip to be tested carries out the communication protocol test through the main control FPGA, the main control FPGA writes specific test data into the chip to be tested, the chip to be tested is sent to the peripheral test interface according to the corresponding communication protocol, the main control FPGA decodes the data after receiving the data sent by the peripheral interface, compares the data and tests whether the chip has the communication protocol problem.
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