CN112199320A

CN112199320A - Multi-channel reconfigurable signal processing device

Info

Publication number: CN112199320A
Application number: CN202011043070.7A
Authority: CN
Inventors: 陈能; 吴江; 刘盛利; 邵永杰
Original assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Current assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Priority date: 2020-09-28
Filing date: 2020-09-28
Publication date: 2021-01-08
Anticipated expiration: 2040-09-28
Also published as: CN112199320B

Abstract

The invention discloses a multi-channel reconfigurable signal processing device, aiming at providing a signal processing device with higher integration level and more flexible reconfiguration mode, which is realized by the following technical scheme: the method comprises the steps that a clock shunt circuit is adopted to receive a reference clock, the required clock is distributed to each signal processing channel, each signal processing channel exchanges control parameters between a DSP and an FPGA, different processing programs are loaded to the FPGA and the DSP according to a reconstruction instruction of a system host, the FPGA and the DSP load functional programs from respective external FLASH, baseband signals to be processed are sent to the corresponding signal processing channels through a data exchange matrix, the DSP and the FPGA of each signal processing channel process the baseband signals and then send the processed baseband signals to the data exchange matrix, the processing of intermediate frequency and baseband signals is completed, and the modulation/demodulation, the despreading/debounce, the data error correction coding and decoding, the wave beam envelope processing and the time measurement of various modes are realized.

Description

Multi-channel reconfigurable signal processing device

Technical Field

The invention relates to the fields of communication, navigation, identification and the like, in particular to a multi-channel reconfigurable signal processing device mainly used for aviation communication.

Background

Signal processing devices are currently widely used in the fields of communication, navigation, identification, and the like. General signal processing devices are oriented to specific application scenes, have diversified functional frameworks and signal processing capabilities and poor compatibility, cannot adapt to multi-platform complex application scenes, and greatly increase hardware research and development and software development costs. At present, the functional requirements of the mainstream signal processing device are taken into consideration, and the use requirements of platforms such as an airborne platform, a ship-borne platform, a vehicle-mounted platform and a ground platform are taken into consideration, so that the signal processing device can be flexibly and widely applied to different fields such as software radio, satellite communication and data link, the signal processing device needs to pass through a unified circuit architecture of a large-scale FPGA and a high-speed DSP, and the uniformity of multi-channel design breaks the barrier of multi-platform generalization. The general signal processing module generally adopts 3 independent channels, and each channel is in a DSP + FPGA structure. The excitation receiving modules are generally divided into a plurality of categories by frequency band. There are many disadvantages to conventional signal processing systems, such as: data loss can be caused by FPGA calculation interruption in the platform reconstruction process; the limited platform hardware resources are difficult to accommodate the increasing scale of processing algorithms. With the development of avionics system integration and software radio theory, the requirements on high-speed sampling, signal processing, software reconstruction capability and miniaturization are higher and higher. A general signal processing platform with higher integration level, more flexible reconstruction mode and dynamically configurable sampling rate needs to be designed. Aiming at the requirement of flexible reception of multi-band and multi-standard signals, signals received by a receiver are often in different frequency bands and have different bandwidths, and the simplest and most direct method for realizing the processing of the multi-band signals is a multi-channel digital receiver. The multi-channel receiver is formed by a plurality of different down-conversion modules in parallel, each down-conversion module covers a single frequency band and completes signal receiving of the fixed frequency band, although the function can be realized, the problems of huge volume, serious resource waste and poor expandability can be inevitably caused. To improve the disadvantages of a multi-channel digital receiver. The prior art provides a reconfigurable virtual multi-channel digital receiver based on an FPGA (field programmable gate array), the whole receiver only has one channel, and the receiving of different frequency bands and different bandwidths is realized by reconfiguring the channel. The method comprises the steps of obtaining a baseband digital signal through modes of extraction filtering and the like, obtaining a difference frequency signal and a sum frequency signal after the baseband signal is subjected to frequency mixing by a direct digital frequency synthesizer DDS, dividing the signal into two channels, obtaining a lower frequency through CIC extraction frequency reduction and a half-band filter on one channel, and obtaining a low frequency signal through frequency reduction and half-band filtering on the other channel. Although the system can work normally, the resource consumption is increased, and the system is obviously not applicable to the condition of multi-channel multiple change.

Disclosure of Invention

Aiming at the problems, the invention provides a method which has higher integration level, more flexible reconstruction mode and dynamically configurable sampling rate. The multi-channel reconfigurable signal processing device can reduce hardware resources, and solves the problems that the traditional signal processing device is long in design period, cannot be multiplexed, cannot be expanded, is insufficient in reliability verification and the like.

The above object of the present invention can be achieved by a multi-channel reconfigurable signal processing apparatus comprising: 1-4 independent signal processing channels and signal processing circuit, clock shunt circuit and power switching circuit on each signal processing channel that are connected to the backplane connector consistently, connect in parallel the data switching matrix and system host computer on the backplane connector, characterized by that: the clock shunt circuit receives a reference clock, converts the reference clock into a clock required by signal processing through frequency multiplication and frequency division and distributes the clock to each signal processing channel, each signal processing channel adopts a Field Programmable Gate Array (FPGA) and a Digital Signal Processor (DSP) which respectively store multi-version switching application programs, control parameters are exchanged between the DSP and the FPGA through an EMIF interface, the DSP and the FPGA load functional programs from respective external FLASH to finish large-capacity data processing in real time, and the DSP stores data to be processed in an external synchronous dynamic random access memory (DDR); the baseband signals to be processed are sent to a signal processing channel through a data exchange matrix, the DSP and the FPGA process the baseband signals and then send the baseband signals to the data exchange matrix, the signal processing channel loads different processing programs to the FPGA and the DSP according to a reconstruction instruction of a system host to complete the processing of the intermediate frequency and baseband signals, and the modulation/demodulation, the despreading/debounce, the data error correction coding and decoding, the beam envelope processing and the time measurement of various modes are realized.

Compared with the prior art, the invention has the beneficial effects that:

the integration level is high. The invention adopts the independent signal processing channels which are internally provided with 1-4 consistency and connected to the backplane connector, and the signal processing circuit, the clock shunt circuit and the power conversion circuit on each signal processing channel, each processing channel adopts a circuit architecture of large-scale FPGA + high-speed DSP, the design of the channels has consistency to realize the digital signal processing function, the consistency of the design of 1-4 processing channels can meet the flexible deployment of application software among the channels, the module generalization with higher integration level can be realized, and the programs among the channels have mutual portability. The method is beneficial to realizing software engineering, and can be expanded and adapted to different signal processing applications. The requirement of independent and concurrent operation of multi-channel waveforms is met, and later-stage function expansion is facilitated. At present, under most application scenes, the requirement of providing the maximum available space in a loading cylinder of a cylinder type structure for 6ULRM structure processing channels is met.

The reconstruction mode is more flexible. The clock shunt circuit receives a reference clock, converts the reference clock into a clock required by signal processing through frequency multiplication and frequency division, reserves a crystal oscillator with the same frequency as a system clock on a signal processing device, and can flexibly distribute reserved crystal oscillator clock signals and the system clock to each signal processing channel FPGA and DSP according to application requirements. Each signal processing channel adopts an FPGA and a DSP which respectively store multi-version switching application programs, the reception of different frequency bands and different bandwidths is realized by the reconstruction of the channel, and different configuration files are configured in a reconstruction area to realize a more flexible reconstruction mode of different channel functions. By adopting the FPGA and DSP partition loading technology, the number of the FPGA and the DSP is reduced from three to one, the PCB layout area is reduced, the system power consumption is reduced, the FPGA and DSP reconfigurable technology is adopted to design a multi-channel reconfigurable virtual multi-channel system, the hardware resources are reduced, 16 application program versions can be stored in each processing channel FPGA and DSP respectively, the multi-version switching can be realized, the hardware volume is reduced to a great extent, meanwhile, the received signal processing can be adjusted in real time, the flexibility and the expandability are very strong, and the reliability and the signal processing capability of the device are improved. The sampling rate can be dynamically configured, and hardware resources can be reduced.

The DSP and the FPGA exchange control parameters through the EMIF interface, function programs are loaded from respective plug-in FLASH, the FPGA receives high-speed serial data through the high-speed serial data interface GTX, and the high-speed serial data interface GTX can reliably complete the transmission of large-capacity data at high speed in real time. The high-speed serial interface can process more and larger data while improving the data transmission rate, the processed data with large capacity is transmitted to the DSP in real time, the DSP stores the data to be processed in the external synchronous dynamic random access memory DDR, the final processing result is transmitted to the data exchange matrix through the main/standby SRIO interface, and the reconstruction is carried out through the input/output flow direction, so that the purpose of reconfigurable processing of the multi-channel array signal is achieved, the computing capacity of the multi-channel array signal processing system is effectively improved, and hardware resources are reduced; each signal processing channel is used as a reconfigurable configuration file, virtual reconfiguration is realized by configuring different configuration files, and the resource utilization rate can be improved to a greater extent.

The FPGA and DSP program codes of the invention are supported in the system to be dynamically reconstructed, the number of reconstructed versions is not less than 8 (including default versions), and different functions are configured in real time according to task requirements.

Drawings

The patent is further described below with reference to the drawings and examples.

Fig. 1 is a schematic block diagram of signal processing channels of the multi-channel reconfigurable signal processing device according to the present invention.

Fig. 2 is a clock splitting functional block diagram of the present invention.

Fig. 3 is a schematic block diagram of the power conversion of the present invention.

Fig. 4 is a functional block diagram of the management control unit of the present invention.

Fig. 5 is a flow chart of function reconfiguration of the present invention.

Fig. 6 is a flow chart of the multi-version program storage of the present invention.

The technical scheme of the invention is further described in detail in the following with reference to the attached drawings.

Detailed Description

See fig. 1. In the preferred embodiment described below, a multi-channel reconfigurable signal processing apparatus is mainly composed of four independent processing paths, 1-4 independent signal processing paths uniformly connected to a backplane connector and a signal processing circuit, a clock branching circuit and a power supply conversion circuit on each signal processing path. The clock shunt circuit receives a reference clock, converts the reference clock into a clock required by signal processing through frequency multiplication and frequency division and distributes the clock to each signal processing channel, each signal processing channel adopts an FPGA and a DSP which respectively store a multi-version switching application program, control parameters are exchanged between the DSP and the FPGA through an EMIF interface, a function program is loaded from each external FLASH, the FPGA receives high-speed serial data through a high-speed serial data interface GTX, large-capacity data which are processed in real time are transmitted to the DSP, the DSP stores the data to be processed in an external synchronous dynamic random access memory DDR, and the final processing result is transmitted to a data exchange matrix through a master/backup SRIO interface; the baseband signals to be processed are sent to corresponding processing channels through a data exchange matrix, after being processed by the DSP and the FPGA, the baseband signals are sent to each signal processing channel through a GTX high-speed serial bus, a reconstruction instruction of a system host is received, different processing programs are loaded to the FPGA and the DSP by the processing unit according to the instruction, the processing channel is constructed into another signal waveform processing unit to complete the processing of the intermediate frequency and baseband signals, and the functions of modulation/demodulation, de-spreading/de-hopping, data error correction coding and decoding, beam envelope processing, time measurement and the like of various modes are realized. The FPGA selects XC7K325T-2FFG900 and the DSP selects TMS320C6455 to realize the digital signal processing function, and the design of each processing path keeps consistent. The processing channel performs digital reception or transmission procedures depending on the system configuration. In the digital receiving process, the user FPGA receives the GTX high-speed serial data, and transmits the processed data to the DSP for further processing, and the digital sending process is opposite to the digital receiving process. Each processing channel has the capability of reconstructing a signal processing function, namely, when a reconstruction instruction of a system host is received in the normal operation process of the channel, the processing unit loads different processing programs to the FPGA and the DSP according to the instruction, so that the processing channel is constructed into another processing unit of signal waveforms.

Preferably, as shown in fig. 2. The clock shunt takes a 125MHz differential clock as the reference input of SRIO facing serial backboard, DSP and serial RapidIO interface and high-speed serial data interface GTX clock of related serial data plane connection application, the two clocks are provided by on-board crystal oscillator and distributed to each processing channel through CSCLK 954; high stability system clock input 100MHz and 32.512MHz are divided into four channels and a clock signal transmitting channel through a low voltage differential signaling LVDS transmitting chip, an output digital signal LC9122, a bus type low voltage differential signaling BLVDS chip bus LC92LV010A based on FPGA are converted into TTL level and input to a special clock pin of a complex programmable logic device CPLD, and in addition, a crystal oscillator with the same frequency as the system clock is reserved on a module as a backup and also input to the special clock pin. The system clock enters the CPLD to be distributed, the 100MHz single-ended system clock and the 32.512MHz single-ended system clock which are sent to the multi-channel reconfigurable signal processing channel are connected to the MRCC pin of the FPGA, and the FPGA program processed by the signals of each waveband can use the two clock signals as clock sources. The complex programmable logic device CPLD divides the 100MHz single-ended input clock by 4 and 2, and outputs the divided clock to the DSP external clock input pins CLKIN1(25M), CLKIN2(50MHz) and JDSPF28335 reference clock pin DSP _25M (25M).

Preferably, the power conversion circuit provides voltages required by other chips, and the device uses a platform to provide a set of 28V power supplies for the multi-channel reconfigurable signal processing device, as shown in FIG. 3. Considering that the voltage difference between the 28V voltage and the internal voltage of the module is large, a distributed power supply framework is adopted, and a three-level voltage conversion scheme is adopted for reducing the heat consumption of the power supply: the first stage converts 28V into 5V to obtain a 5V power supply used in the module; the second stage is converted from internal 5V to power sources such as 3.3V, 1.2V, 1.8V and 1.0V used inside the signal processing channel, and the third stage is converted from internal 3.3V and 1.8V to power sources such as 1.8V, 1.2V and 1.0V used inside the GTX channel. In addition, the MCU is adopted to control the power-on sequence of each power supply on the second and third-stage power supply conversion circuits on the signal processing device. The first-stage power supply adopts an isolated DC/DC power converter EA24M050P025R22, the input voltage range of the first-stage power supply is 18V to 36V, the maximum output power is 125W when the voltage is 5V at normal temperature, and the efficiency can reach 92.5%. The second stage switching power supply outputs are as follows: the MCU cell 5V voltage input, internally converted to the required 1.9V, 1.2V, 2.5V and 3.3V. The 1.9V power supply supplies power to the MCU kernel; the 3.3V power supply supplies power to IO (input/output) devices of the MCU; the 1.2V power supply supplies power to the CPLD inner core; the 2.5V power supply is the auxiliary voltage of the programmable logic CPLD. The 4 voltages are all provided by 2 pieces of LYM4622 double-output DC-DC power supply. The 1.0V power supply supplies power for the FPGA core, an LYM4630 type double-output DC-DC power supply module is selected for supplying power, one path of power is supplied to the

FPGAs

1 and 2, and the other path of power is supplied to the FPGAs 3 and 4; a 1.25V power supply supplies power for all DSP cores, an LYM4620 type double-output DC-DC power supply module is selected for supplying power, one path of power is supplied to the

DSPs

1 and 2, and the other path of power is supplied to the DSPs 3 and 4; the 3.3V power supply supplies power for almost all I/O devices, supplies power for SM74401 to generate GTXIO power supply of 1.8V, selects LYM4616 type power supply module to supply power, the other path of power supply of the LYM4616 outputs 1.8V, supplies power for DSP and DDR2SDRAM interface, and supplies power for SM74401 to generate SRIO _1.25V power supply. SRIO _1.25V supplies power for SRIO of all DSPs, and SM74401 power supply is adopted for supplying power. FPGAGTX has three power sources GTX1.0V, GTX1.2V and GTX1.8V, wherein GTX1.0V and GTX1.2V are provided by LYM4616 power source, and GTX1.8V is provided by SM74401 power source. The first stage power supply is controllable through an APP signal, the APP is suspended and output is enabled, and the APP pull-down and output are closed. The power-on timing of the second stage power supply is controllable through the EN signal, and the reference power supply 3.3V is generated by the GED1963 through a 5V input. The 1.25V kernel power supply, the 1.8V power supply and the 3.3VIO power supply used by the DSP have the store time sequence requirement, the power-on sequence is firstly 3.3V, and then other power supplies are powered on together

Preferably, as shown in fig. 4. The management control unit connected with the signal processing channel through the high-density FMC connector, the discrete control line and the channel EMIF bus comprises: the CAN bus protocol processing is realized and the module power-on management and the module MARK link address acquisition are completed through the constitution of a JDSPF28335+1 sheet type field programmable gate array circuit JXCLX25-668 and related peripherals connected by a discrete control line and an XINTF interface, 100MHz and 32.512MHz system clock distribution, processing channel dog feeding, module temperature monitoring, module voltage detection, self-checking and version information reporting of clock interface chips LC92LV010 and LC9122 are adopted, a GH063X is adopted as an optical coupler in the CAN link, and ER65HVD230 is adopted as an interface chip.

Preferably, as shown in fig. 5. The signal processing device sends a function reconfiguration instruction to a DSP when a platform system host connected with a backplane connector is used for carrying out function reconfiguration on a certain processing channel, after a DSP normal operation processing program receives a system host FPGA dynamic loading instruction, a Flash high-order address of the FPGA is switched through a CPLD, a corresponding version is selected to be loaded into the FPGA, whether the program is the reconfiguration instruction is judged, if not, a currently operated user program is immediately stopped, a normal operation processing program is returned, if yes, the program jumps to a bottom layer management program and starts to be executed, the bottom layer management program analyzes the reconfiguration instruction transmitted by the user program, a FLASH address needing to be operated is obtained, an FPGA program clearing control register is set, corresponding FPGA and DSP programs are searched from the FLASH to be respectively loaded, whether a monitoring initialization INIT signal is 1 is judged, if yes, the FPGA program is read, and then whether an FPGA loading completion flag register is 1 is judged, if so, reading the DSP program, otherwise, returning to read the FPGA program, after reading the DSP program, judging whether the loading completion flag register is 1, if so, jumping to the DSP program entry address to start execution, covering the original user program in the chip program storage area by the DSP program newly loaded, and after finishing loading, jumping to the user program entry address again by the DSP to start executing the newly loaded user program. After receiving an FPGA (field programmable gate array) online updating instruction of a system host, the DSP switches the Flash high-order address of the DSP through the CPLD, selects a corresponding version to load into the RAM of the DSP, and then resets the running program of the DSP. And controlling the FPGA to load the basic version through the CPLD, receiving the updated program file and writing the updated program file into the corresponding address of the DSP Flash by the DSP basic version, receiving the updated program file and writing the updated program file into the corresponding address of the FPGA Flash, finishing an online updating process if verification is successful after the writing is finished, and otherwise reporting an online updating abnormal state.

Preferably, as shown in fig. 6. In the process of normally operating the processing program, after receiving a system host instruction, the DSP judges whether the instruction is a program curing instruction, if so, the DSP analyzes the instruction to obtain a FLASH address required to be operated and receives a new program transmitted by the system host, the system host sends a FLASH programming instruction to the DSP through the SRIO bus, a FLASH programming function module is started and transmits the new program to the DSP, after receiving the FLASH programming instruction, the DSP immediately stops the currently operated program and then executes a bottom management program, the bottom management program receives the new program transmitted by the system host and confirms whether the transmission is finished, if so, the FLASH programming function module is started, the DSP responds to the system host, analyzes the FLASH programming instruction, and then the new program is programmed to a corresponding address in the DSP and the FPGA plug-in FLASH to cover the original program.

The foregoing is only a preferred embodiment for implementing a multi-channel reconfigurable signal processing apparatus, and it is to be understood that the invention is not limited to the form disclosed herein, but is not to be construed as excluding other embodiments and may be used in various other combinations, modifications, and environments and may be modified within the scope of the concept described herein by the above teachings or by the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A multi-channel reconfigurable signal processing apparatus comprising: 1-4 independent signal processing channels uniformly connected to the backplane connector, and a signal processing circuit, a clock shunting circuit and a power conversion circuit on each signal processing channel, a data switching matrix and a system host computer connected in parallel on the backplane connector, wherein: the clock shunt circuit receives a reference clock, converts the reference clock into a clock required by signal processing through frequency multiplication and frequency division and distributes the clock to each signal processing channel, each signal processing channel adopts a Field Programmable Gate Array (FPGA) and a Digital Signal Processor (DSP) which respectively store multi-version switching application programs, control parameters are exchanged between the DSP and the FPGA through an EMIF interface, the DSP and the FPGA load functional programs from respective external FLASH to finish large-capacity data processing in real time, and the DSP stores data to be processed in an external synchronous dynamic random access memory (DDR); the baseband signals to be processed are sent to a signal processing channel through a data exchange matrix, the DSP and the FPGA process the baseband signals and then send the baseband signals to the data exchange matrix, the signal processing channel loads different processing programs to the FPGA and the DSP according to a reconstruction instruction of a system host to complete the processing of the intermediate frequency and baseband signals, and the modulation/demodulation, the despreading/debounce, the data error correction coding and decoding, the beam envelope processing and the time measurement of various modes are realized.

2. The multi-channel reconfigurable signal processing apparatus according to claim 1, wherein: the clock division inputs the differential clock as the clock reference of a high-speed serial data RapidIO interface and a high-speed serial data GTX interface which are applied to the connection of related serial data planes, the two clocks are provided by an on-board crystal oscillator and are distributed to each processing channel through a clock distribution chip CSCLK 954.

3. The multi-channel reconfigurable signal processing apparatus according to claim 1, wherein: a 100MHz system clock from the backplane connector is converted into a TTL level clock through a four-channel low-voltage differential signal LVDS sending chip LC 9122; 32.512MHzBLVDS level system clock is converted into TTL level clock through BLVDS bus chip LC92LV010A, then the two clocks are input to CPLD clock pin of complex programmable logic device, crystal oscillator with same frequency as system clock is reserved on the module as backup, and is also input to CPLD clock pin.

4. A multi-channel reconfigurable signal processing apparatus according to claim 3, characterized in that: and the 100MHz and 32.512MHz system clocks enter the CPLD to be distributed, the 100MHz and 32.512MHz single-ended system clocks sent to the signal processing channel are connected to the MRCC pin of the FPGA, and the two clock signals are used as clock sources by the FPGA program for processing the signals of each waveband.

5. The multi-channel reconfigurable signal processing apparatus according to claim 4, wherein: the complex programmable logic device CPLD divides the 100MHz single-ended input clock by 4 and 2, and outputs the divided clock to the DSP external clock input pins CLKIN1(25M), CLKIN2(50MHz) and JDSPF28335 reference clock pin DSP _25M (25M).

6. The multi-channel reconfigurable signal processing apparatus according to claim 1, wherein: the MCU unit connected with the system host through the CAN bus controls the power-on time sequence of each power supply on the second-level power supply conversion circuit and the third-level power supply conversion circuit on the signal processing device, the first-level power supply adopts an isolated DC/DC power supply converter, and a 1.9V power supply supplies power for an MCU core; the 3.3V power supply supplies power to IO (input/output) devices of the MCU; the 1.2V power supply supplies power to the CPLD inner core; the 2.5V power supply is an auxiliary voltage of the programmable logic CPLD, and the 4 voltages are all provided by 2 LYM4622 double-output DC-DC power supplies; the first stage power supply is controllable through an APP signal, the APP is suspended, namely output is enabled, and the APP is pulled down, namely output is closed; the power-on timing of the second stage power supply is controllable through the EN signal, and the reference power supply 3.3V is generated by the GED1963 through a 5V input.

7. The multi-channel reconfigurable signal processing apparatus according to claim 1, wherein: the management control unit MCU is connected with the backplane connector through a 2-way CAN field bus, the MCU comprises 1 JDSPF28335+1 field programmable gate array circuit JXCLX25-668 connected through a discrete control line and a XINTF interface and related peripherals, realizes CAN bus protocol processing, completes module power-on management and module MARK link address acquisition, and performs 100MHz and 32.512MHz system clock distribution, processing channel dog feeding, module temperature monitoring, module voltage detection, self-checking and version information reporting through clock interface chips LC92LV010 and LC 9122.

8. The multi-channel reconfigurable signal processing apparatus according to claim 1, wherein: when a system host interconnected with a device through a backplane connector performs function reconstruction on a certain processing channel, a function reconstruction instruction is sent to a DSP, after a DSP normal operation processing program receives a system host FPGA dynamic loading instruction, a Flash high-order address of the FPGA is switched through a CPLD, a corresponding version is selected to be loaded into the FPGA, whether the program is the reconstruction instruction is judged, if not, a currently operated user program is stopped immediately, a normal operation processing program is returned, if yes, the program jumps to a bottom layer management program and starts to be executed, the bottom layer management program analyzes the reconstruction instruction transmitted by the user program, a FLASH address needing to be operated is obtained, an FPGA program clearing control register is set, a corresponding FPGA and a corresponding DSP program are searched from the FLASH to be respectively loaded, whether a monitoring initialization INIT signal is 1 is judged, if yes, the FPGA program is read, and then whether an FPGA loading completion flag register is 1 is judged, if so, reading the DSP program, otherwise, continuing to wait, after reading the DSP program, judging whether the loading completion flag register is 1, if so, jumping to the DSP program entry address to start execution.

9. The multi-channel reconfigurable signal processing apparatus according to claim 1, wherein: the FPGA and the DSP which are newly loaded cover the original user program in the chip program storage area, and after the loading is finished, the FPGA and the DSP jump to the entry address of the user program again to start to execute the newly loaded user program; after receiving the FPGA and DSP online updating instruction, the DSP switches the Flash high-order addresses of the FPGA and the DSP through the CPLD, selects the corresponding versions to load into the RAMs of the FPGA and the DSP, and then resets the running programs of the FPGA and the DSP; and controlling the FPGA and the DSP to load the basic version through the CPLD, receiving the updated program file and writing the updated program file into the Flash corresponding address of the DSP by the DSP basic version, receiving the updated program file and writing the updated program file into the Flash corresponding address of the FPGA, finishing an online updating process if verification is successful after the writing is finished, and otherwise reporting an online updating abnormal state.

10. The channel reconfigurable signal processing apparatus according to claim 1, wherein: after receiving the instruction of the system host, the DSP judges whether the instruction is a program curing instruction, if so, the DSP analyzes the instruction to obtain a FLASH address needing to be operated, receives a new program transmitted by the system host, and after receiving the FLASH programming instruction, the DSP immediately stops the currently operated program and then executes a bottom management program, wherein the bottom management program receives the new program transmitted by the system host, confirms whether the transmission is finished, if so, the DSP starts a FLASH programming function module, responds to the system host, analyzes the FLASH programming instruction, and then writes the new program to a corresponding address in the DSP and the FPGA plug-in FLASH to cover the original program.