CN111190855A - FPGA multiple remote configuration system and method - Google Patents

Abstract

The invention discloses a FPGA multiple remote configuration system and a method, comprising a remote configuration module, a FPGA master control module and a control module, wherein the remote configuration module is used for receiving a bit stream file sent by an upper computer and sending the bit stream file to the FPGA master control module; the FPGA main control module is used for writing the bit stream file into the memory module; the storage module is used for storing a plurality of bit stream files and writing the bit stream files into different addresses, and the FPGA main control module reads out the corresponding bit stream files from the specified addresses to realize configuration during reconfiguration; the power supply module is used for supplying power to the system; the clock module is used for providing corresponding working clocks for the FPGA main control module and the memory module; and the interface module is used for configuring the FPGA main control module on line and realizing the control of reading and writing of the memory module. The method realizes FPGA multiple remote configuration based on the system. The invention solves the problem of low FLASH configuration speed of the traditional SPI interface, meets the requirements of different working modes in a multi-configuration mode, greatly reduces the time for system configuration and has strong practicability, universality and transportability.

Description

FPGA multiple remote configuration system and method

Technical Field

The invention belongs to the field of communication, particularly relates to the field of FPGA remote configuration, and particularly relates to a FPGA multiple remote configuration system and a method.

Background

Modern hardware program design scale is getting bigger and bigger, and functions are getting more and more complex, when a plurality of application programs are simultaneously realized on one hardware platform, resource usage and data paths of all the programs may conflict, which increases complexity of control circuit design and increases workload and development difficulty for developers.

In recent years, the FPGA technology has been rapidly developed, and is widely applied to design of large complex systems as a programmable resource. Although FPGAs have achieved considerable success in terms of resource integration, in large-scale system design in multiple modes, single-chip FPGA resources are far from meeting design requirements, and sometimes multiple chips may be required. However, the price of the FPGA is relatively high, which greatly increases the design cost, and the product is not easy to maintain and upgrade, so that the FPGA loading technology appears, but the traditional loading configuration adopts SPI interface, FLASH and the like, the configuration speed is slow, and the requirements of various working modes cannot be met.

Disclosure of Invention

The invention aims to provide an FPGA multiple remote configuration system and method with the characteristics of low cost, high configuration speed, high reliability and the like.

The technical solution for realizing the purpose of the invention is as follows: an FPGA multiple remote configuration system comprises a remote configuration module, an FPGA main control module, a memory module, a power supply module, a clock module and an interface module;

the remote configuration module is used for receiving the bit stream file sent by the upper computer and sending the bit stream file to the FPGA main control module;

the FPGA main control module is used for receiving the bit stream file, writing the bit stream file into the memory module, and appointing to receive a certain bit stream file from the memory module to realize reconfiguration after receiving the FPGA reconfiguration instruction;

the memory module is used for storing a plurality of bit stream files from the FPGA main control module and writing the bit stream files into different addresses, and the FPGA main control module reads out the corresponding bit stream files from the specified addresses to configure the FPGA main control module during reconfiguration;

the power supply module is used for supplying power to the whole system;

the clock module is used for providing corresponding working clocks for the FPGA main control module and the memory module;

the interface module is used for configuring the FPGA main control module on line and realizing the control of reading and writing of the memory module.

The configuration method based on the FPGA multiple remote configuration system comprises the following steps:

step 1, an interface module configures an FPGA main control module on line to realize the control of reading and writing of a memory module;

step 2, the remote configuration module receives a bit stream file sent by an upper computer and sends the bit stream file to the FPGA main control module;

step 3, the FPGA main control module receives the bit stream file and writes the bit stream file into the memory module, and the memory module writes the bit stream file into different addresses;

and 4, when the FPGA main control module receives the FPGA reconfiguration instruction, reading the bit stream file from the corresponding address in the memory module according to the specified bit stream file to configure the FPGA main control module.

Compared with the prior art, the invention has the following remarkable advantages: 1) through multiple configuration, a plurality of programs can be loaded into the FPGA in a time-sharing manner according to needs, and the problem of insufficient programmable resources can be solved, so that the development cost is greatly reduced, the utilization rate of the programmable resources is improved, the complexity of system design is reduced, the flexibility of the system design is increased, and the system is convenient to maintain and upgrade; 2) through the multiple loading technology, a user can select to load different bit stream files according to the requirement, so that the multi-mode function is realized; 3) compared with a common memory using an SPI FLASH as a bit stream file, QSPI FLASH has larger storage space and higher reading and writing speed, a plurality of bit stream files of Virtex-7 series FPGA can be stored in one piece of QSPI FLASH, the reading and writing speed is increased by times, and the time for configuring the FPGA system is greatly saved; 4) the ICAPE2 is called to verify that the multi-reconfiguration can be realized by the FPGA under the condition of no power failure, and when the reloaded bit stream file has a problem, the FPGA can select to load the original bit stream file, so that the system can be ensured to be in a working state forever, and the system can not be halted due to the problem of updating the program.

The present invention is described in further detail below with reference to the attached drawing figures.

Drawings

Fig. 1 is a block diagram of the FPGA multiple remote configuration system according to the present invention.

FIG. 2 is a circuit diagram of a multi-configuration hardware implementation QSPI FLASH according to an embodiment of the invention.

FIG. 3 is a flow chart illustrating the implementation of QSPI FLASH in a multi-configuration embodiment of the present invention.

FIG. 4 is a flow chart of QSPI FLASH state machine instructions in one embodiment of the invention.

FIG. 5 is a flow diagram of an ICAP core state machine instruction in accordance with an embodiment of the present invention.

Detailed Description

With reference to fig. 1, the present invention provides an FPGA multiple remote configuration system, which includes a remote configuration module, an FPGA master control module, a memory module, a power module, a clock module, and an interface module;

the remote configuration module is used for receiving the bit stream file sent by the upper computer and sending the bit stream file to the FPGA main control module;

the FPGA main control module is used for receiving the bit stream file, writing the bit stream file into the memory module, and appointing to receive a certain bit stream file from the memory module to realize reconfiguration after receiving the FPGA reconfiguration instruction;

the memory module is used for storing a plurality of bit stream files from the FPGA main control module and writing the bit stream files into different addresses, and the FPGA main control module reads out the corresponding bit stream files from the specified addresses to configure the FPGA main control module during reconfiguration;

the power supply module is used for supplying power to the whole system;

the clock module is used for providing corresponding working clocks for the FPGA main control module and the memory module;

and the interface module is used for configuring the FPGA main control module on line and realizing the control of reading and writing of the memory module.

Further, in one embodiment, in conjunction with fig. 3, the remote configuration module communicates with the host computer via a gigabit ethernet.

Further, in one embodiment, in conjunction with FIG. 3, the remote configuration module employs a DSP.

Further, in one embodiment, with reference to fig. 3, the remote configuration module specifically sends the bit stream file to the FPGA main control module through an EMIF interface of the DSP.

Further, in one embodiment, the memory module employs FLASH memory.

Further, in one embodiment, in conjunction with FIG. 3, the FLASH memory employs a QSPI interface.

Further, in one embodiment, the FLASH memory is implemented using QSPI FLASH chips.

Further, in one embodiment, the interface module employs a JTAG interface.

As a specific example, the technical scheme of the invention is as follows:

hardware design:

the multi-configuration hardware mainly comprises an FPGA board card and a FLASH chip for storing and configuring the bit stream file. The FPGA chip selects XC7VX485T-2FFG1761 in Virtex-7 series of XILINX company, and the chip has special internal loading logic to realize multiple configurations. Since the bit file size of the FPGA chip is about 100Mb, the FLASH chip selects QSPI FLASH chip N25Q256A of MICRON company, the storage space of the FLASH chip is 256Mb, and the FLASH chip is enough to store 2 bit stream files. The hardware connections of the particular FPGA and QSPI FLASH are shown in figure 2.

Designing software:

the software design is divided into two parts, wherein the first part is to write QSPI FLASH state machine programs for reading, writing and erasing, and store bit stream files received by the FPGA into QSPI FLASH. The second part is writing an FPGA heavy-load configuration module.

Unlike SPI FLASH, QSPI FLASH four-wire mode has four signal lines in total, all of which can be used as input and output to transmit data, so QSPI four-wire mode is approximately four times faster than SPI mode (see table 1 below) when transmitting the same size data module, but QSPI four-wire mode is more complicated to use. Except for commands of reading, writing, erasing and the like of the SPI, the QSPI needs to write a command of entering a 4-byte address mode before entering the four-wire mode, and needs to write a command of exiting the 4-byte address mode after finishing all the commands. In this case, the address accessed by the read and write instructions must be 4 bytes. QSPI FLASH the state machine instruction flow is shown in figure 4.

TABLE 1 QSPI FLASH comparison of time required for commands to read, write, erase, etc. from SPI FLASH

The multiple configuration of the FPGA requires calling an ICAPE2 core, and when a trigger condition is satisfied, the ICAPE2 core is assigned and configured in a state machine coding manner as shown in fig. 5.

The Virtex-7 series FPGA calls ICAPE2 kernel primitives as follows:

after the ICAPE2 core is called, Verilog code implements a state machine. The IPROG instruction is sent to the ICAPE2 core through the state machine, and the ICAPE2 core can automatically load the bit stream file needing configuration according to the specified address after receiving the instruction. The first clock cycle of the state machine asserts the RDWRB and CSIB signals of the ICAPE2 core high, the second cycle asserts the RDWRB and CE signals low, and the third cycle asserts both the RDWRB and CSIB signals low. The control commands in the instruction queue are then issued sequentially for the next 8 clock cycles.

Where the fifth control command wave Boot Start Address Register (WBSTAR) specifies the Start Address in QSPI FLASH of the bit stream file that satisfies the trigger condition, note that the WBSTAR is assigned the same Address as the physical Address in QSPI of the bit stream file to be configured.

After all the control commands are sent, the special configuration logic of the FPGA starts to execute internal reset operation (the JTAG pin and the reload control part do not reset), the original program on the system is erased, the bit stream file is read from the start address pointed by the WBSTAR in QSPI FLASH, and the reconfiguration of the FPGA is completed.

The configuration method based on the FPGA multiple remote configuration system comprises the following steps:

step 1, an interface module configures an FPGA main control module on line to realize the control of reading and writing of a memory module;

step 2, the remote configuration module receives a bit stream file sent by an upper computer and sends the bit stream file to the FPGA main control module;

step 3, the FPGA main control module receives the bit stream file and writes the bit stream file into the memory module, and the memory module writes the bit stream file into different addresses;

and 4, when the FPGA main control module receives the FPGA reconfiguration instruction, reading the bit stream file from the corresponding address in the memory module according to the specified bit stream file to configure the FPGA main control module.

In conclusion, the invention solves the problem of low FLASH configuration speed of the traditional SPI interface, meets the requirements of different working modes in a multi-configuration mode, greatly reduces the time for system configuration and has strong practicability, universality and transportability.

Claims (9)

1. The FPGA multiple remote configuration system is characterized by comprising a remote configuration module, an FPGA main control module, a memory module, a power supply module, a clock module and an interface module;

the remote configuration module is used for receiving the bit stream file sent by the upper computer and sending the bit stream file to the FPGA main control module;

the FPGA main control module is used for receiving the bit stream file, writing the bit stream file into the memory module, and appointing to receive a certain bit stream file from the memory module to realize reconfiguration after receiving the FPGA reconfiguration instruction;

the memory module is used for storing a plurality of bit stream files from the FPGA main control module and writing the bit stream files into different addresses, and the FPGA main control module reads out the corresponding bit stream files from the specified addresses to configure the FPGA main control module during reconfiguration;

the power supply module is used for supplying power to the whole system;

the clock module is used for providing corresponding working clocks for the FPGA main control module and the memory module;

the interface module is used for configuring the FPGA main control module on line and realizing the control of reading and writing of the memory module.

2. The FPGA multiple remote configuration system of claim 1, wherein the remote configuration module communicates with the host computer via a gigabit ethernet.

3. The FPGA multiple remote configuration system of claim 1, wherein said remote configuration module employs a DSP.

4. The FPGA multi-remote-configuration system according to claim 1 or 2, wherein the remote configuration module sends the bit stream file to the FPGA main control module through an EMIF interface of the DSP.

5. The FPGA multiple remote configuration system of claim 1, wherein said memory module employs FLASH memory.

6. The FPGA multiple remote configuration system of claim 4, wherein the FLASH memory employs a QSPI interface.

7. The FPGA multi-remote configuration system of claim 4, wherein the FLASH memory is an QSPI FLASH chip.

8. The FPGA multiple remote configuration system of claim 1 wherein said interface module employs a JTAG interface.

9. The configuration method of the FPGA multiple remote configuration system based on any one of claims 1 to 8, characterized by comprising the following steps:

step 1, an interface module configures an FPGA main control module on line to realize the control of reading and writing of a memory module;

step 2, the remote configuration module receives a bit stream file sent by an upper computer and sends the bit stream file to the FPGA main control module;

step 3, the FPGA main control module receives the bit stream file and writes the bit stream file into the memory module, and the memory module writes the bit stream file into different addresses;

and 4, when the FPGA main control module receives the FPGA reconfiguration instruction, reading the bit stream file from the corresponding address in the memory module according to the specified bit stream file to configure the FPGA main control module.

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