CN112463651A - QSPI controller, image processor and flash memory access method - Google Patents

QSPI controller, image processor and flash memory access method Download PDF

Info

Publication number
CN112463651A
CN112463651A CN202011417962.9A CN202011417962A CN112463651A CN 112463651 A CN112463651 A CN 112463651A CN 202011417962 A CN202011417962 A CN 202011417962A CN 112463651 A CN112463651 A CN 112463651A
Authority
CN
China
Prior art keywords
state machine
stage
phase
qspi
assignment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011417962.9A
Other languages
Chinese (zh)
Inventor
刘刚强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changsha Jingmei Integrated Circuit Design Co ltd
Changsha Jingjia Microelectronics Co ltd
Original Assignee
Changsha Jingmei Integrated Circuit Design Co ltd
Changsha Jingjia Microelectronics Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changsha Jingmei Integrated Circuit Design Co ltd, Changsha Jingjia Microelectronics Co ltd filed Critical Changsha Jingmei Integrated Circuit Design Co ltd
Priority to CN202011417962.9A priority Critical patent/CN112463651A/en
Publication of CN112463651A publication Critical patent/CN112463651A/en
Priority to PCT/CN2021/087349 priority patent/WO2022121199A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
    • G06F9/4451—User profiles; Roaming
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The embodiment of the application provides a QSPI controller and a flash memory access method in an image processor, wherein the QSPI controller comprises an on-chip bus interface, a sending first-in first-out memory, a receiving first-in first-out memory and a receiving and sending control module; the on-chip bus interface is used for being connected with an AHB bus to acquire a configuration command; the transmission first-in first-out storage is used for storing transmission data; the receiving first-in first-out memory is used for storing receiving data; and the transceiving control module is used for controlling the state machine to jump at each stage according to the configuration command and outputting a communication signal to the flash memory through the QSPI bus. A QSPI controller is designed, a state machine in the QSPI controller is controlled to jump at each stage through a configuration command, communication signals are output to achieve access to a flash memory, double-line or four-line access can be achieved based on a QSPI protocol, and data transmission speed in flash memory access is improved.

Description

QSPI controller, image processor and flash memory access method
Technical Field
The application relates to the technical field of computers, in particular to a QSPI controller, an image processor and a flash memory access method.
Background
In computer technology, communication with flash memory is often required. In accessing the flash memory, a Serial Peripheral Interface (SPI) is generally used to communicate with the flash memory. However, since the SPI is a single line, the transmission speed of data is slow when flash memory access is performed through the SPI.
Disclosure of Invention
The embodiment of the application provides a QSPI controller and a flash memory access method, and solves the problem that data transmission speed is low in flash memory access.
According to a first aspect of embodiments of the present application, there is provided a QSPI controller, the QSPI controller including: the on-chip bus interface is used for sending the first-in first-out memory, receiving the first-in first-out memory and receiving and sending the control module; the on-chip bus interface is used for being connected with an AHB bus to acquire a configuration command; the transmission first-in first-out storage is used for storing transmission data; the receiving first-in first-out memory is used for storing receiving data; and the transceiving control module is used for controlling the state machine to jump at each stage according to the configuration command and outputting a communication signal to the flash memory through the QSPI bus.
According to a second aspect of embodiments of the present application, there is provided an image processor, including the QSPI controller provided in the first aspect, a bus interconnect system, and a central processor; the bus interconnection system is respectively connected with the central processing unit and a PCIe bus through an AXI bus; the bus interconnection system is connected with the QSPI controller through an AHB bus; the QSPI controller is connected with the flash memory through a QSPI bus.
According to a third aspect of embodiments of the present application, there is provided a flash memory access method, including: acquiring a configuration command, wherein the configuration command is used for configuring a state machine in the QSPI controller according to a QSPI protocol; and controlling the state machine to jump at each stage according to the configuration command, and outputting a communication signal to the flash memory.
According to a fourth aspect of embodiments of the present application, there is provided a flash memory access device, including: the obtaining module is used for obtaining a configuration command, and the configuration command is used for configuring a state machine in the QSPI controller according to a QSPI protocol; and the access module is used for controlling the state machine to jump at each stage according to the configuration command and outputting a communication signal to the flash memory.
According to a fifth aspect of embodiments herein, there is provided an electronic device comprising one or more processors; a memory; one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the method as applied to an electronic device, as described above.
According to a sixth aspect of embodiments of the present application, there is provided a computer-readable storage medium having program code stored therein, wherein the method described above is performed when the program code is run.
By adopting the QSPI controller, the image processor and the flash memory access method provided by the embodiment of the application, a configuration command is obtained, and the configuration command is used for configuring a state machine in the QSPI controller according to a QSPI protocol; and controlling the state machine to jump at each stage according to the configuration command, and outputting a communication signal to the flash memory. A QSPI controller is designed, a state machine in the QSPI controller is controlled to jump at each stage through a configuration command, communication signals are output to achieve access to a flash memory, double-line or four-line access can be achieved based on a QSPI protocol, and data transmission speed in flash memory access is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a structural diagram of a QSPI controller according to an embodiment of the present application;
FIG. 2 is a schematic diagram of the QSPI controller connection in an image processor according to one embodiment of the present application;
FIG. 3 is a flow chart of a method for accessing a flash memory according to an embodiment of the present application;
FIG. 4 is a diagram illustrating a jump of a state machine in an idle stage according to an embodiment of the present application;
FIG. 5 is a diagram illustrating a jump of a state machine at an instruction phase according to an embodiment of the present application;
FIG. 6 is a diagram illustrating a jump of a state machine in an address phase according to an embodiment of the present application;
FIG. 7 is a diagram illustrating jumping of a state machine in a byte alternation phase according to an embodiment of the present application;
FIG. 8 is a functional block diagram of a flash memory access device according to one embodiment of the present application;
fig. 9 is a block diagram of an electronic device for executing a flash memory access method according to an embodiment of the present application.
Detailed Description
In computer technology, communication with flash memory is often required. In accessing the flash memory, a Serial Peripheral Interface (SPI) is generally used to communicate with the flash memory. However, since the SPI is a single line, the transmission speed of data is slow when flash memory access is performed through the SPI.
The inventor finds that QSPI is the extension of an SPI interface and is wider than the SPI application, the function of the QSPI is enhanced on the basis of the SPI protocol, a queue transmission mechanism is added, and a queue serial peripheral interface protocol is provided. With the QSPI interface, the speed at which a user transmits data is 4 times faster than the SPI interface. And once the QSPI starts transmission, the transmission process does not need the intervention of a CPU until the transmission is finished, thereby greatly improving the transmission efficiency.
In view of the above problems, an embodiment of the present application provides a QSPI controller and a flash memory access method, where the QSPI controller includes an on-chip bus interface, a transmit fifo, a receive fifo, and a transmit/receive control module; the on-chip bus interface is used for being connected with an AHB bus to acquire a configuration command; the transmission first-in first-out storage is used for storing transmission data; the receiving first-in first-out memory is used for storing receiving data; and the transceiving control module is used for controlling the state machine to jump at each stage according to the configuration command and outputting a communication signal to the flash memory through the QSPI bus. A QSPI controller is designed, a state machine in the QSPI controller is controlled to jump at each stage through a configuration command, communication signals are output to achieve access to a flash memory, double-line or four-line access can be achieved based on a QSPI protocol, and data transmission speed in flash memory access is improved.
The solution in the embodiment of the present application may be implemented by using a computer hardware description language, for example, Verilog language.
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following further detailed description of the exemplary embodiments of the present application with reference to the accompanying drawings makes it clear that the described embodiments are only a part of the embodiments of the present application, and are not exhaustive of all embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Referring to fig. 1, a block diagram of a QSPI controller according to an embodiment of the present application is shown.
The QSPI controller 10 includes an on-chip bus interface 11, a First Input First Output (FIFO) memory 12, a First Input First Output (FIFO) memory 13, and a transceiving control module 14. The on-chip bus interface 11 is configured to be connected to an AHB bus to obtain a configuration command, the transmit FIFO memory 12 is configured to store transmit data, the receive FIFO memory 13 is configured to store receive data, the transmit data may be read data, and the receive data may be write data, and the transmit/receive control module 14 is configured to control the state machine to jump at each stage according to the configuration command and output a communication signal to the flash memory through a QSPI bus. That is, according to the QSPI protocol, the state machine in the transceiving control module 14 is controlled through an AHB bus configuration register, which may be in the form of a configuration command in which values may be assigned to various stages of the state machine, so that the transceiving control module 14 may access the flash memory according to the values assigned to various stages of the state machine in the configuration command.
The transceiver control module 14 includes a state machine, and the state machine can jump to various stages, such as an idle stage, an instruction stage, an address stage, an alternate byte stage, a null cycle stage, and a data stage. Typically, the QSPI controller may communicate with the flash memory via commands, each command including five phases, an instruction phase, an address phase, an alternate byte phase, a null cycle phase, and a data phase, any of which may be skipped but including at least one of the instruction phase, the address phase, the alternate byte phase, or the data phase.
In the instruction phase, commands (8-bit instructions) may be sent to the flash memory, allowing any value to be sent, specifying the type of operation to be performed, which may be sent in a 1-wire, 2-wire, or 4-wire fashion by configuration. In the address phase, addresses are sent to the flash memory, data is read or written from the specified addresses, 1-4 byte addresses are allowed to be sent, and the addresses can be sent in a 1-line, 2-line or 4-line mode through configuration. During the byte alternation phase, 1-4 bytes are sent to the flash memory, typically for controlling the mode of operation. During the empty cycle phase, no data is sent or received for a given 1-31 cycles, in order to allow time for the flash memory to prepare for the data phase when a higher clock frequency is used. Any number of bytes may be received from or sent to the flash memory during the data phase.
The on-chip Bus interface 11 is connected to an AHB Bus, and is capable of acquiring a configuration command, where the AHB is an abbreviation of an Advanced High Performance Bus (AHB), and is a Bus interface. The transceiver control module 14 is connected to the flash memory through the QSPI bus, and is configured to control the state machine to jump at each stage according to the configuration command, and output a communication signal through the QSPI bus to implement access to the flash memory.
Flash memory is a non-volatile memory that can still hold written data when power is off, in fixed block units, rather than in individual bytes. Common flash memories include a U disk, a flash memory card, and the like.
In the QSPI controller, the on-chip bus interface 11, the transmission FIFO memory 12, the reception FIFO memory 13, and the transmission/reception control module 14 form a soft channel by control signals, and can access the flash memory through an AHB bus configuration register. And data stream can be directly transmitted between the on-chip bus interface 11 and the transceiving control module 14 to form a hard channel, thereby realizing direct access to the flash memory. Therefore, the QSPI controller accesses the flash memory in two modes, and can be compatible with all flash memories with SPI or QSPI interfaces, wherein the software configuration mode is flexible and supports two-wire access.
The QSPI controller provided in the embodiment of the present application may be designed to be used in a chip, and please refer to fig. 2, which shows a connection diagram of the QSPI controller provided in the embodiment of the present application in an image processor (GPU) 20.
The GPU 20 includes a Central Processing Unit (CPU) 21, a bus interconnection system 22, and the QSPI controller 10, where the QSPI controller is connected to the bus interconnection system 22 through an AHB bus, and the bus interconnection system 22 is connected to the CPU 21 through an AXI bus and connected to a PCIe bus through an AXI bus. The QSPI controller 10 is connected to the flash memory 23 through a QSPI bus, and outputs a communication signal through the QSPI bus to realize access to the flash memory 23. Thus, communication between GPU 20 and flash memory 23 may be achieved.
The QSPI controller provided by the embodiment of the application comprises an on-chip bus interface, a transmission FIFO memory, a reception FIFO memory and a receiving and transmitting control module; the on-chip bus interface is used for being connected with an AHB bus to acquire a configuration command; the transmission FIFO memory is used for storing transmission data; the receiving FIFO memory is used for storing received data; and the transceiving control module is used for controlling the state machine to jump at each stage according to the configuration command and outputting a communication signal to the flash memory through the QSPI bus. A QSPI controller is designed, a state machine in the QSPI controller is controlled to jump at each stage through a configuration command, communication signals are output to achieve access to a flash memory, double-line or four-line access can be achieved based on a QSPI protocol, and data transmission speed in flash memory access is improved.
Referring to fig. 3, an embodiment of the present invention provides a flash memory access method, which can be applied to the QSPI controller provided in the foregoing embodiment.
Step 110, obtaining a configuration command, where the configuration command is used to configure a state machine in the QSPI controller according to a QSPI protocol.
The QSPI controller can obtain a configuration command through an AHB bus, and the configuration command is used for configuring a state machine in the QSPI controller according to a QSPI protocol. Wherein the state machine is in the transmit-receive control module in the QSPI controller. The state machine may be controlled by an AHB bus configuration register according to the QSPI protocol. The configuration command may include communication commands for communicating with the flash memory, each command including five phases, namely an instruction phase, an address phase, an alternate byte phase, a null cycle phase and a data phase, and any of the five phases may be skipped, but at least any of the instruction phase, the address phase, the alternate byte phase or the data phase may be included, and the communication commands may assign values to the respective phases to form the communication command.
The state machine includes an idle phase and five phases corresponding to the communication commands, and thus the state machine can be configured by a configuration command.
And step 120, controlling the state machine to jump at each stage according to the configuration command, and outputting a communication signal to the flash memory.
Communication commands for communicating with the flash memory may be included in the configuration commands, and the communication commands may configure five phases of a state machine. Therefore, the state machine can jump at each stage according to the configuration command and output a communication signal to the flash memory to realize the access to the flash memory, namely, the communication with the flash memory is carried out. Specifically, the current stage of the state machine may be obtained; obtaining the assignment of each stage of the state machine in the configuration command; determining another stage of the state machine jump according to the value assignment of each stage; outputting a communication signal to the flash memory when the state machine jumps to another phase.
Since the state machine has a plurality of stages, the jump of the state machine in each stage can be controlled by the configuration command, and the detailed description of the jump of the state machine in each stage will be provided below.
If the state machine is currently in the idle stage, the state machine may jump to an instruction stage, an address stage, and a data stage. If the assignment of the instruction phase is not 0, the state machine jumps to the instruction phase; if the assignment of the instruction phase is 0, the state machine jumps to the address phase; and if the assignment of the data phase is not 0, the state machine jumps to the data phase.
Referring to fig. 4, a diagram illustrating the state machine jumping during the idle phase is shown. When the state machine is currently in an idle stage, the state machine can jump from the idle stage to an instruction stage when the condition 1 is met, jump from the idle stage to an address stage when the condition 2 is met, and jump from the idle stage to a data stage when the condition 3 is met.
Wherein the condition 1 is that the instruction phase assignment is not 0. Condition 2 is that the instruction phase has a value of 0. Condition 3 is that the data-only phase assignment is not 0.
If the state machine is currently in the instruction phase and the state enable is valid, the state machine can jump to an idle phase, an address phase, an alternate byte phase, an empty cycle phase and a data phase. If the assignment values of other stages are all 0, the state machine jumps to the idle stage; if the assignment of the address phase is not 0, the state machine jumps to the address phase; if the assignment of the address stage is 0, the state machine jumps to the alternate byte stage; if the assignment of the address stage and the alternate byte stage is 0, the state machine jumps to the empty cycle stage; and if the assignment of the data phase is not 0, the state machine jumps to the data phase.
It will be appreciated by those skilled in the art that the state machine enables the state to be active when jumping at each stage, so that jumping at each stage is possible.
Referring to FIG. 5, a diagram illustrating jump of a state machine at the instruction phase is shown. When the state machine is currently in an instruction phase, the state enable is effective, the condition 4 is met, and the state machine can jump to an idle phase from the instruction phase; a jump from the instruction phase to the address phase can be made if condition 5 is satisfied; satisfying condition 6 may jump from the instruction phase to the alternate byte phase; satisfying condition 7 may jump from the instruction phase to the empty cycle phase; satisfying condition 8 may jump from the instruction phase to the data phase.
The condition 4 is that the assignments of other phases are all 0, that is, the assignments of the address phase, the alternate byte phase, the null cycle phase and the data phase are all 0. Condition 5 is that the address phase assignment is not 0. Condition 6 is that the address phase has a value of 0. Condition 7 is that the assignments for the address phase and the alternate byte phase are both 0. The condition 8 is that the assignment of the data-only phase is not 0, i.e., the assignment of the address phase, the alternate byte phase, and the null cycle phase is 0.
If the state machine is currently in the address phase and the state enable is valid, the state machine may jump to the alternate byte phase, the null cycle phase, and the data phase. If the assignment of the alternate byte stage is not 0, the state machine jumps to the alternate byte stage; if the assignment of the alternate byte stage is 0, the state machine jumps to the empty cycle stage; and if the assignment of the data phase is not 0, the state machine jumps to the data phase.
Referring to fig. 6, a diagram illustrating the state machine jumping at the address phase is shown. When the state machine is currently in an address stage, the state enable is effective, the condition 9 is met, and the state machine can jump from the address stage to an alternate byte stage; satisfying condition 10 may jump from the address phase to the empty cycle phase; satisfying condition 11 may jump from the address phase to the data phase.
Wherein the condition 9 is that the assignment of the alternate byte stage is not 0. The condition 10 is that the alternate byte phase is assigned a value of 0. The condition 11 is that only the assignment of the data phase is not 0, that is, the assignments of the alternate byte phase and the null cycle phase are both 0.
If the state machine is currently in the alternate byte phase and state enable is active, the state machine may jump to a null cycle phase and a data phase. If the assignment of the empty cycle stage is not 0, the state machine jumps to the empty cycle stage; and if the assignment of the empty cycle stage is 0, the state machine jumps to the data stage.
Referring to fig. 7, a diagram of the state machine jumping during the byte alternation phase is shown. When the state machine is currently in a byte alternating stage, the state enable is effective, the condition 12 is met, and the state machine can jump to a null cycle stage from the byte alternating stage; satisfaction of condition 13 may jump from the byte alternation phase to the data phase. Wherein the condition 12 is that the value assigned to the empty cycle phase is not 0. The condition 13 is that the value of the empty cycle phase is 0.
And if the state machine is currently in the empty cycle stage and the state enable is valid, when the data stage is not 0, the state machine jumps to the data stage. That is, the state machine may jump from the null cycle phase to the data phase when the data phase has a value of 0.
When the state machine is currently in the data phase, data can be received and transmitted in the data phase, so that the count value of the byte receiving counter can be acquired, and when the count value is equal to the configuration value in the configuration command, the state machine indicates that data receiving and transmitting are finished, and can jump from the data phase to the idle phase. Of course, the conversion is performed based on 1 byte and 8 bits, and the count value in the data phase may be a number of bits.
It is understood that the access modes in the QSPI protocol may be single line access, two line access, and four line access, and that the register configuration access modes may be used in the instruction phase, address phase, alternate byte phase, and data phase of the state machine. Therefore, the flash memory can be accessed in a single-wire, double-wire and four-wire mode. That is, the access mode of the state machine at each stage can be obtained by the configuration command.
In some embodiments, the data tasks of a phase need to be completed before the state machine jumps to that phase. Before the state machine jumps to a certain stage, determining an access mode corresponding to the current stage of the state machine according to a configuration command; determining a preset count value corresponding to the current stage according to the access mode; acquiring an actual count value corresponding to a current stage; and when the actual count value is equal to a preset count value, determining another stage of the state machine jump according to the assignment of each stage.
In the instruction stage, the address stage and the byte alternation stage, data is sent to the flash memory, so that the access mode corresponding to the stage can be obtained first, the corresponding preset count value is determined, and when the actual count value is equal to the preset count value, the next stage is skipped according to the above conditions. For example, in the address phase, it is determined that the access mode is a two-line access, the two address bits of the flash memory capacity may be 24 bits and 32 bits, and assuming that the address bits are 24 bits, the preset count value corresponding to the two-line access is 12, and if it is determined that the access mode is a one-line access, the preset count value corresponding to the one-line access is 24, when the actual count value is equal to the preset count value, the other phase may be skipped according to the above conditions.
In the idle period stage, no data is sent or received within 1-31 periods, and the time for preparing the data stage is set for the flash memory, so that the preset count value is the configured period number in the idle period stage, and the actual count value is the actual period number. In the configuration command, the number of cycles may be configured in advance, the configured number of cycles is a preset count value, and when the actual number of cycles is equal to the configured number of cycles, the method jumps to another stage according to the above condition.
In some embodiments, the direction of the lines at each stage may be controlled by a configuration command, and at different stages, whether to read or write may be determined by the configuration command, and after determining whether to read or write, the direction of the lines may be controlled.
When the state machine jumps to any stage, the state machine can output a communication signal to the flash memory through the QSPI bus to realize the communication with the flash memory.
According to the flash memory access method provided by the embodiment of the application, a configuration command is obtained, and the configuration command is used for configuring a state machine in a QSPI controller according to a QSPI protocol; and controlling the state machine to jump at each stage according to the configuration command, and outputting a communication signal to the flash memory. A QSPI controller is designed, a state machine in the QSPI controller is controlled to jump at each stage through a configuration command, and a communication signal is output to realize the access to a flash memory.
Referring to fig. 8, an embodiment of the present application provides a flash memory access apparatus 200, where the flash memory access apparatus 200 includes an obtaining module 210 and an accessing module 220. The obtaining module 210 is configured to obtain a configuration command, where the configuration command is used to configure a state machine in the QSPI controller according to a QSPI protocol; the access module 220 is configured to control the state machine to jump at each stage according to the configuration command, and output a communication signal to the flash memory.
Further, the state machine includes an idle stage, an instruction stage, an address stage, an alternate byte stage, an empty cycle stage and a data stage, and the access module 220 is further configured to obtain a stage in which the state machine is currently located; obtaining the assignment of each stage of the state machine in the configuration command; and determining the other stage of the state machine jump according to the value assignment of each stage.
Further, if the state machine is currently in the idle stage, the access module 220 is further configured to jump to the instruction stage if the assignment of the instruction stage is not 0; if the assignment of the instruction phase is 0, the state machine jumps to the address phase; and if the assignment of the data phase is not 0, the state machine jumps to the data phase.
Further, if the state machine is currently in the instruction stage and the state enable is valid, the access module 220 is further configured to jump to the idle stage if the assignments of other stages are all 0; if the assignment of the address phase is not 0, the state machine jumps to the address phase; if the assignment of the address stage is 0, the state machine jumps to the alternate byte stage; if the assignment of the address stage and the alternate byte stage is 0, the state machine jumps to the empty cycle stage; and if the assignment of the data phase is not 0, the state machine jumps to the data phase.
Further, if the state machine is currently in the address phase and the state enable is valid, the access module 220 is further configured to jump to the alternate byte phase if the assignment of the alternate byte phase is not 0; if the assignment of the alternate byte stage is 0, the state machine jumps to the empty cycle stage; and if the assignment of the data phase is not 0, the state machine jumps to the data phase.
Further, if the state machine is currently in the alternate byte stage and the state enable is valid, the access module 220 is further configured to jump to the empty cycle stage if the assignment of the empty cycle stage is not 0; and if the assignment of the empty cycle phase is 0, the state machine jumps to the data phase.
Further, if the state machine is currently in the empty cycle stage and the state enable is valid, the access module 220 is further configured to jump to the data stage if the assignment of the data stage is not 0.
Further, if the state machine is currently in the data phase, the access module 220 is further configured to obtain a count value of a byte reception counter; and if the count value is equal to the configuration value in the configuration command, the state machine jumps to the idle stage.
Further, before determining that the state machine jumps to another stage according to the assignment of each stage, the access module 220 is further configured to determine, according to a configuration command, an access manner corresponding to the current stage of the state machine, where the access manner includes a single line, a double line, and a four line; determining a preset count value corresponding to the current stage according to the access mode; acquiring an actual count value corresponding to a current stage; and when the actual count value is equal to the preset count value, determining another stage of the state machine jump according to the assignment of each stage.
The flash memory access device provided by the embodiment of the application acquires a configuration command, wherein the configuration command is used for configuring a state machine in a QSPI controller according to a QSPI protocol; and controlling the state machine to jump at each stage according to the configuration command, and outputting a communication signal to the flash memory. A QSPI controller is designed, a state machine in the QSPI controller is controlled to jump at each stage through a configuration command, communication signals are output to achieve access to a flash memory, double-line or four-line access can be achieved based on a QSPI protocol, and data transmission speed in flash memory access is improved.
It should be noted that, as will be clear to those skilled in the art, for convenience and brevity of description, the specific working process of the above-described apparatus may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
Referring to fig. 9, an embodiment of the present application provides a block diagram of an electronic device, where the electronic device 300 includes a processor 310, a memory 320, and one or more application programs, where the one or more application programs are stored in the memory 320 and configured to be executed by the one or more processors 310, and the one or more programs are configured to perform the above-mentioned method for accessing a flash memory.
The electronic device 300 may be a terminal device capable of running an application, such as a smart phone, a tablet computer, an electronic book, or may be a server. The electronic device 300 in the present application may include one or more of the following components: a processor 310, a memory 320, and one or more applications, wherein the one or more applications may be stored in the memory 320 and configured to be executed by the one or more processors 310, the one or more programs configured to perform a method as described in the aforementioned method embodiments.
Processor 310 may include one or more processing cores. The processor 310 connects various parts throughout the electronic device 300 using various interfaces and lines, and performs various functions of the electronic device 300 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 320 and calling data stored in the memory 320. Alternatively, the processor 310 may be implemented in hardware using at least one of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 310 may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing display content; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the processor 310, but may be implemented by a communication chip.
The Memory 320 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). The memory 320 may be used to store instructions, programs, code sets, or instruction sets. The memory 320 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing various method embodiments described below, and the like. The data storage area may also store data created by the electronic device 300 during use (e.g., phone book, audio-video data, chat log data), etc.
The electronic device provided by the embodiment of the application acquires a configuration command, wherein the configuration command is used for configuring a state machine in a QSPI controller according to a QSPI protocol; and controlling the state machine to jump at each stage according to the configuration command, and outputting a communication signal to the flash memory. A QSPI controller is designed, a state machine in the QSPI controller is controlled to jump at each stage through a configuration command, communication signals are output to achieve access to a flash memory, double-line or four-line access can be achieved based on a QSPI protocol, and data transmission speed in flash memory access is improved.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims (16)

1. A QSPI controller comprises an on-chip bus interface, a transmission first-in first-out memory, a reception first-in first-out memory and a receiving and transmitting control module;
the on-chip bus interface is used for being connected with an AHB bus to acquire a configuration command;
the transmission first-in first-out storage is used for storing transmission data;
the receiving first-in first-out memory is used for storing receiving data;
and the transceiving control module is used for controlling the state machine to jump at each stage according to the configuration command and outputting a communication signal to the flash memory through the QSPI bus.
2. The QSPI controller according to claim 1, the transceiver control module coupled to a flash memory via a QSPI bus.
3. The QSPI controller of claim 1, wherein the transceiver control module comprises a state machine, and wherein the various stages of the state machine comprise an idle stage, an instruction stage, an address stage, an alternate byte stage, a null cycle stage, and a data stage.
4. An image processor comprising the QSPI controller of any one of claims 1 to 3, a bus interconnect system, and a central processor;
the bus interconnection system is respectively connected with the central processing unit and a PCIe bus through an AXI bus;
the bus interconnection system is connected with the QSPI controller through an AHB bus;
the QSPI controller is connected with the flash memory through a QSPI bus.
5. A flash memory access method applied to the QSPI controller of any one of claims 1 to 3, the method comprising:
acquiring a configuration command, wherein the configuration command is used for configuring a state machine in the QSPI controller according to a QSPI protocol;
and controlling the state machine to jump at each stage according to the configuration command, and outputting a communication signal to the flash memory.
6. The method of claim 5, wherein the state machine comprises an idle stage, an instruction stage, an address stage, an alternate byte stage, a null cycle stage, and a data stage, and wherein controlling the state machine to jump at each stage and output a communication signal to the flash memory according to the configuration command comprises:
acquiring the current stage of the state machine;
obtaining the assignment of each stage of the state machine in the configuration command;
determining another stage of the state machine jump according to the value assignment of each stage;
outputting a communication signal to the flash memory when the state machine jumps to another phase.
7. The method of claim 6, wherein said determining another phase of said state machine jump based on said assignments of said respective phase if said state machine is currently in said idle phase comprises:
if the assignment of the instruction phase is not 0, the state machine jumps to the instruction phase;
if the assignment of the instruction phase is 0, the state machine jumps to the address phase;
and if the assignment of the data phase is not 0, the state machine jumps to the data phase.
8. The method of claim 6, wherein if the state machine is currently in the instruction phase and state enable is active, said determining another phase of the state machine jump based on the assignments of the respective phases comprises:
if the assignment values of other stages are all 0, the state machine jumps to the idle stage;
if the assignment of the address phase is not 0, the state machine jumps to the address phase;
if the assignment of the address stage is 0, the state machine jumps to the alternate byte stage;
if the assignment of the address stage and the alternate byte stage is 0, the state machine jumps to the empty cycle stage;
and if the assignment of the data phase is not 0, the state machine jumps to the data phase.
9. The method of claim 6, wherein if the state machine is currently in the address phase and state enable is active, said determining another phase of the state machine jump based on the assignments of the respective phases comprises:
if the assignment of the alternate byte stage is not 0, the state machine jumps to the alternate byte stage;
if the assignment of the alternate byte stage is 0, the state machine jumps to the empty cycle stage;
and if the assignment of the data phase is not 0, the state machine jumps to the data phase.
10. The method of claim 6, wherein if the state machine is currently in the alternate byte phase and state enabled is valid, said determining another phase of the state machine jump based on the assignments of the phases comprises:
if the assignment of the empty cycle stage is not 0, the state machine jumps to the empty cycle stage;
and if the assignment of the empty cycle phase is 0, the state machine jumps to the data phase.
11. The method of claim 6, wherein if the state machine is currently in the empty cycle phase and state enable is active, said determining another phase of the state machine jump based on the assignments of the respective phases comprises:
and if the assignment of the data phase is not 0, the state machine jumps to the data phase.
12. The method of claim 6, wherein said determining another phase of said state machine jump based on said respective phase assignments if said state machine is currently in said data phase comprises:
acquiring a count value of a byte receiving counter;
and if the count value is equal to the configuration value in the configuration command, the state machine jumps to the idle stage.
13. The method according to any of claims 6-12, wherein said determining that another phase of said state machine jump precedes said assigning of said respective phase further comprises:
determining an access mode corresponding to a current stage of the state machine according to a configuration command, wherein the access mode comprises a single line, a double line and a four line;
determining a preset count value corresponding to the current stage according to the access mode;
acquiring an actual count value corresponding to a current stage;
and when the actual count value is equal to the preset count value, determining another stage of the state machine jump according to the assignment of each stage.
14. A flash memory access apparatus applied to the QSPI controller of any one of claims 1 to 3, the apparatus comprising:
the obtaining module is used for obtaining a configuration command, and the configuration command is used for configuring a state machine in the QSPI controller according to a QSPI protocol;
and the access module is used for controlling the state machine to jump at each stage according to the configuration command and outputting a communication signal to the flash memory.
15. An electronic device, characterized in that the electronic device comprises:
one or more processors;
a memory electrically connected with the one or more processors;
one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more applications configured to perform the method of any of claims 5 to 13.
16. A computer-readable storage medium, having stored thereon program code that can be invoked by a processor to perform the method according to any one of claims 5 to 13.
CN202011417962.9A 2020-12-07 2020-12-07 QSPI controller, image processor and flash memory access method Pending CN112463651A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202011417962.9A CN112463651A (en) 2020-12-07 2020-12-07 QSPI controller, image processor and flash memory access method
PCT/CN2021/087349 WO2022121199A1 (en) 2020-12-07 2021-04-15 Qspi controller, image processor and flash memory access method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011417962.9A CN112463651A (en) 2020-12-07 2020-12-07 QSPI controller, image processor and flash memory access method

Publications (1)

Publication Number Publication Date
CN112463651A true CN112463651A (en) 2021-03-09

Family

ID=74801544

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011417962.9A Pending CN112463651A (en) 2020-12-07 2020-12-07 QSPI controller, image processor and flash memory access method

Country Status (2)

Country Link
CN (1) CN112463651A (en)
WO (1) WO2022121199A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113032300A (en) * 2021-03-23 2021-06-25 安谋科技（中国）有限公司 Data transmission control method
CN113032301A (en) * 2021-03-23 2021-06-25 安谋科技（中国）有限公司 Memory controller, system on chip thereof and electronic device
CN114490460A (en) * 2022-03-31 2022-05-13 成都启英泰伦科技有限公司 FLASH controller for ASIC and control method thereof
WO2022121199A1 (en) * 2020-12-07 2022-06-16 长沙景嘉微电子股份有限公司 Qspi controller, image processor and flash memory access method
CN114925010A (en) * 2022-05-23 2022-08-19 中国电子科技集团公司第五十八研究所 Method for converting Quad SPI (Serial peripheral interface) into AXI (advanced extensible interface)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115576499A (en) * 2022-11-10 2023-01-06 广州翼辉信息技术有限公司 Flash security enhancing method for real-time system access and access thereof

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101819560A (en) * 2009-02-27 2010-09-01 杭州晟元芯片技术有限公司 Method and device for executing program of SPI interface memory
CN102103566A (en) * 2009-12-18 2011-06-22 Nxp股份有限公司 Flash memory-interface
US20130282945A1 (en) * 2012-04-19 2013-10-24 Lockheed Martin Corporation Apparatus and method emulating a parallel interface to effect parallel data transfer from serial flash memory
CN106201934A (en) * 2015-05-29 2016-12-07 亚德诺半导体集团 Serial peripheral interface host port
CN107347158A (en) * 2017-06-01 2017-11-14 西南电子技术研究所（中国电子科技集团公司第十研究所） Aircraft load terminal image compression method
CN108566357A (en) * 2017-12-21 2018-09-21 中国科学院西安光学精密机械研究所 Image transmitting based on ZYNQ-7000 and FreeRTOS and control system and method
CN111008171A (en) * 2019-11-25 2020-04-14 中国兵器工业集团第二一四研究所苏州研发中心 Communication IP circuit with serial FLASH interface control
CN111143259A (en) * 2019-12-31 2020-05-12 大唐半导体科技有限公司 Multi-line SPI flash controller
CN111190855A (en) * 2019-12-13 2020-05-22 南京理工大学 FPGA multiple remote configuration system and method
CN111338991A (en) * 2020-02-20 2020-06-26 中国科学院自动化研究所 Multi-mode storage system based on eMMC array
CN111566987A (en) * 2018-12-12 2020-08-21 深圳市汇顶科技股份有限公司 Data processing method, circuit, terminal device and storage medium
CN111597137A (en) * 2020-04-07 2020-08-28 安凯(广州)微电子技术有限公司 Dynamic debugging method, device and system based on SPI protocol
CN111897749A (en) * 2020-06-23 2020-11-06 中国船舶重工集团公司第七0七研究所 Quad-SPI (Serial peripheral interface) controller and externally-extended FLASH communication control system and method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102567253A (en) * 2010-12-13 2012-07-11 深圳市硅格半导体有限公司 DMA (direct memory access)-based SPI (serial peripheral interface) data transmission method and DMA-based SPI data transmission device
US10042808B1 (en) * 2015-09-16 2018-08-07 Xilinx, Inc. Modeling SPI flash memory commands in hardware
US11061670B2 (en) * 2019-03-05 2021-07-13 Marvell Asia Pte, Ltd. Dual-interface flash memory controller with execute-in-place cache control
CN112463651A (en) * 2020-12-07 2021-03-09 长沙景嘉微电子股份有限公司 QSPI controller, image processor and flash memory access method

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101819560A (en) * 2009-02-27 2010-09-01 杭州晟元芯片技术有限公司 Method and device for executing program of SPI interface memory
CN102103566A (en) * 2009-12-18 2011-06-22 Nxp股份有限公司 Flash memory-interface
US20110153910A1 (en) * 2009-12-18 2011-06-23 Mackenna Craig Flash Memory-Interface
US20130282945A1 (en) * 2012-04-19 2013-10-24 Lockheed Martin Corporation Apparatus and method emulating a parallel interface to effect parallel data transfer from serial flash memory
CN106201934A (en) * 2015-05-29 2016-12-07 亚德诺半导体集团 Serial peripheral interface host port
CN107347158A (en) * 2017-06-01 2017-11-14 西南电子技术研究所（中国电子科技集团公司第十研究所） Aircraft load terminal image compression method
CN108566357A (en) * 2017-12-21 2018-09-21 中国科学院西安光学精密机械研究所 Image transmitting based on ZYNQ-7000 and FreeRTOS and control system and method
CN111566987A (en) * 2018-12-12 2020-08-21 深圳市汇顶科技股份有限公司 Data processing method, circuit, terminal device and storage medium
CN111008171A (en) * 2019-11-25 2020-04-14 中国兵器工业集团第二一四研究所苏州研发中心 Communication IP circuit with serial FLASH interface control
CN111190855A (en) * 2019-12-13 2020-05-22 南京理工大学 FPGA multiple remote configuration system and method
CN111143259A (en) * 2019-12-31 2020-05-12 大唐半导体科技有限公司 Multi-line SPI flash controller
CN111338991A (en) * 2020-02-20 2020-06-26 中国科学院自动化研究所 Multi-mode storage system based on eMMC array
CN111597137A (en) * 2020-04-07 2020-08-28 安凯(广州)微电子技术有限公司 Dynamic debugging method, device and system based on SPI protocol
CN111897749A (en) * 2020-06-23 2020-11-06 中国船舶重工集团公司第七0七研究所 Quad-SPI (Serial peripheral interface) controller and externally-extended FLASH communication control system and method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022121199A1 (en) * 2020-12-07 2022-06-16 长沙景嘉微电子股份有限公司 Qspi controller, image processor and flash memory access method
CN113032300A (en) * 2021-03-23 2021-06-25 安谋科技（中国）有限公司 Data transmission control method
CN113032301A (en) * 2021-03-23 2021-06-25 安谋科技（中国）有限公司 Memory controller, system on chip thereof and electronic device
CN113032301B (en) * 2021-03-23 2023-12-29 安谋科技（中国）有限公司 Memory controller, system on chip and electronic device
CN114490460A (en) * 2022-03-31 2022-05-13 成都启英泰伦科技有限公司 FLASH controller for ASIC and control method thereof
CN114490460B (en) * 2022-03-31 2022-06-28 成都启英泰伦科技有限公司 FLASH controller for ASIC and control method thereof
CN114925010A (en) * 2022-05-23 2022-08-19 中国电子科技集团公司第五十八研究所 Method for converting Quad SPI (Serial peripheral interface) into AXI (advanced extensible interface)

Also Published As

Publication number Publication date
WO2022121199A1 (en) 2022-06-16

Similar Documents

Publication Publication Date Title
CN112463651A (en) QSPI controller, image processor and flash memory access method
CN106951388B (en) PCIe-based DMA data transmission method and system
CN106874224B (en) Multi-line SPI-Flash controller capable of automatically carrying and adapting to device
US10241955B2 (en) Dynamically adjustable multi-line bus shared by multi-protocol devices
JP2019508915A (en) Optimal latency packetizer finite state machine for messaging and I / O transfer interfaces
CN110309088B (en) ZYNQ FPGA chip, data processing method thereof and storage medium
US10572410B2 (en) Function-specific communication on a multi-drop bus for coexistence management
US20190227971A1 (en) Architecture for consolidating multiple sources of low-bandwidth data over a serial bus
US20200201804A1 (en) I3c device timing adjustment to accelerate in-band interrupts
CN112749113A (en) Data interaction method, system, device and medium
KR101630599B1 (en) Serial peripheral interface with control logic for system performance improvement, and method therefor
CN108959136A (en) Data delivery acceleration device, system and data transmission method based on SPI
CN111026697A (en) Inter-core communication method, inter-core communication system, electronic device and electronic equipment
CN112328523A (en) Method, device and system for transmitting double-rate signal
US6378011B1 (en) Parallel to serial asynchronous hardware assisted DSP interface
CN111143068B (en) File operation method and device and embedded controller
CN115470163A (en) Control method, control device, control equipment and storage medium for DMA transmission
US20020010817A1 (en) Host signal processing modem with a signal processing accelerator
US8909823B2 (en) Data processing device, chain and method, and corresponding recording medium for dividing a main buffer memory into used space and free space
CN115237349A (en) Data read-write control method, control device, computer storage medium and electronic equipment
EP3029579A2 (en) Controller with indirect accessible memory
EP3819778A1 (en) Bus system and method for operating a bus system
JPH09259068A (en) Extended input and output interface
CN108804362A (en) Serial ports bulk data transmission method, device and storage medium
CN111124987B (en) PCIE-based data transmission control system and method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20210309