CN107347158A - Aircraft load terminal image compression method - Google Patents
Aircraft load terminal image compression method Download PDFInfo
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- CN107347158A CN107347158A CN201710405688.5A CN201710405688A CN107347158A CN 107347158 A CN107347158 A CN 107347158A CN 201710405688 A CN201710405688 A CN 201710405688A CN 107347158 A CN107347158 A CN 107347158A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
- H04N19/426—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements using memory downsizing methods
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/85—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
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Abstract
A kind of aircraft load terminal image compression method disclosed by the invention, it is desirable to provide one kind supports that a variety of image resolution ratios, compression of images multiplying power are controllable, compression signal to noise ratio is adjustable, the high method for compressing image of compression efficiency.The technical scheme is that：In using fpga chip as the image compression system that core forms；FPGA loading procedure and ADV212 firmware file are stored in a piece of flash storage jointly；Then the ARM kernels embedded in FPGA are used to carry out parameter configuration to image compression chip ADV212 by bus AXI_EMC, with Hardware Description Language VHDL to being resequenced from image input interface LVDS view data, framing, verification and segmentation, give the data after segmentation to image compression chip ADV212 and carry out view data interaction in fpga logic part, by the data output after compression to programming logic gate array FPGA, FPGA logic cell module is according to after the interruption for detecting ADV212 processing completions, reception original image information is circulated from LVDS interface and be compressed processing again.
Description
Technical field
The present invention relates to a kind of Image Compression that can be widely applied in a variety of data transmission systems, especially scheme
As in the fields such as communication, being mainly used in the terminal image compression method of the aircraft load such as remote sensing, remote measurement.
Background technology
Image is the important sources that people obtain information, and particularly after the digitlization of image, digital picture is being transmitted and deposited
During the extensive use of storage, frequently encounter that digital image data amount is huge, and transmission bandwidth and the limited contradiction of memory capacity.
The storage of image and transmission problem become more and more prominent, it is desirable to store, transmit it is as far as possible low to the expense of Internet resources, while again
The quality of image in storage and transmitting procedure can not be reduced.In recent years, the appearance of high speed high frame-frequency camera, view data is significantly
Increase, and transmission bandwidth substantially turns into bottleneck, therefore Image Compression turns into the focus of research in recent years.Image Compression is wide
General to be applied in a variety of data transmission systems, such as video player generally use MPEG4 or H.264 compress mode, number shine
The compress modes such as camera generally use JPEG.JPEG2000 compression algorithms have good compression efficiency, but algorithm is complicated, always
Annoying engineer applied.Because existing spaceborne, airborne communication terminal restricted is in the limitation of the space of platform, image pressure is not supported generally
Contracting function, under particular circumstances, influenceed by transmission time, memory space and channel width, carry the image of mass data
Information is difficult quickly to be transmitted or stored, and this turns into one of main bottleneck of Image Information Processing development.
In the prior art usually using digital signal processor DSP, the compression function of raw image data is realized.Image pressure
The usual operand of core algorithm of contracting is intensive, runs these algorithms and usually requires to use powerful DSP, due to dsp chip
Other general utility functions it is relatively weak, generally required a general purpose microprocessor to realize some network data transmissions etc.
Function, and the collection of such as view data, preprocessing function also need to extra programming logic gate array FPGA and realized.Mesh
Preceding satellite remote sensing images compressibility hardware plan is mostly based on high performance programmable logical device FPGA.But this scheme is whole
System cost remains high, and FPGA has Single event upset effecf.In order to reduce cost of hardware design, prior art also proposes
A kind of hardware design structure for the FPGA+DSP for being managed and controlling using FPGA.This frame using FPGA+DSP
Structure is disadvantageous in that the area of pcb board is larger, and the load terminal such as aircraft for being not suitable for being limited in volume uses.
Another typical implementation is to use special ASIC image compression chips, special ASIC image compression chips
Corresponding terminal asic chip usually is released with regard to certain specific coding protocol, required software programming amount is small, and compression speed is fast,
Shortcoming is that special asic chip usually requires special program storage, to store ASIC firmware file, and a processing
Device goes to configure and managed, and introduces extra PCB surface product again and opens slightly.
To meet the application demand of the load terminal such as aircraft, in addition to keeping normal communication function, it is necessary to carry out figure
As the Miniaturization Design of compression function.
The content of the invention
The task of the present invention is not support compression of images function not for existing spaceborne, onboard flight device communication terminal
Foot, there is provided one kind supports that a variety of image resolution ratios, compression of images multiplying power are controllable, compression signal to noise ratio is adjustable, miniaturization, low-power consumption,
Compression efficiency is high, is easy to hard-wired aircraft mounted terminal method for compressing image.
The above-mentioned purpose of the present invention can be reached by following measures, a kind of aircraft load terminal image compression side
Method, there is following technical characteristic：With with image input interface LVDS, serial ports, internal memory DDR programming logic gate array FPGA
Chip is core, electrical connection biplate program load store device QSPI Flash, Ethernet chip PHY, A/D converter
ADC, D/A converter DAC and image compression chip ADV212 composition image compression systems；FPGA loading procedure and
ADV212 firmware file is stored in a piece of flash storage jointly；Then the ARM kernels embedded in FPGA are used to pass through total
Line AXI_EMC carries out parameter configuration to image compression chip ADV212, is retouched by programming logic gate array FPGA with hardware
Predicate say VHDL to being resequenced from image input interface LVDS view data, framing, verification and segmentation, with complete
Into the collection of view data, reception, compression pretreatment input, and by view data storage into Large Copacity internal memory DDR, FPGA is patrolled
Collect part and give the data after segmentation to image compression chip ADV212 progress view data interactions, by the data output after compression
To programming logic gate array FPGA, after FPGA logic cell module is according to detecting that ADV212 handles the interruption completed, then from
LVDS interface circulation receives original image information and is compressed processing.
The present invention has the advantages that compared to prior art：
Support that a variety of image resolution ratios, compression of images multiplying power are controllable.The present invention is real using programming logic gate array FPGA chip
Collection, reception, the pretreatment of existing input image data, rearrangement, the segmentation of view data are realized using VHDL language, and will
Data after segmentation give image compression chip ADV212, and 4096*4096 image resolutions can only be supported by solving ADV212 maximums
The limitation of rate.ADV212 is exported after data compression to programming logic gate array FPGA, in FPGA complete framing, verification,
Radio-frequency channel is sent to transmit to other nodes after encryption.In programming logic gate array FPGA, using being checked in embedded ARM
ADV212 carries out parameter configuration, using VHDL language, and logical gate is realized and interacted with ADV212 view data in FPGA, is adopted
Image preprocessing is realized with FPGA, rearrangement, module segmentation comprising image, the resolution ratio for being divided into ADV212 to support.
Avoid the deficiency of the limited resolution of the image of prior art image compression chip ADV212 supports.
Compression of images multiplying power is controllable, compression signal to noise ratio is adjustable.The present invention can preset compression multiplying power, and compression signal to noise ratio can
Adjust, and compressed error control is more suitable for transmitting in the limited wireless radio-frequency link of speed within ± 5%.Overcome existing
Have technology by compare compression after the method for compressing image of data volume and the size of data of original image, learning compression multiplying power thing
The defects of post analysis.
Miniaturization, low-power consumption.FPGA program, ADV212 firmware file are stored in a piece of Flash and stored by the present invention
In device, the demand to the special eeprom memories of ADV212 is avoided, is advantageous to the miniaturization of equipment.Solves prior art
FPGA needs special program loading flash storage, and ADV212 is also required to special eeprom memory storage firmware file
Problem.The present invention utilizes the external special internal memory of DDR chips of the ARM cores embedded in FPGA, as the large capacity cache of image, profit
With same group of DDR chip, FPGA is combined with special compression chip ADV212, realizes the interior of ARM cores embedded in FPGA
Deposit with two kinds of functions of the large capacity cache of image, without special Large Copacity image buffer storage, avoided in image procossing generally
The demand of special Large Copacity ping-pong buffer image is needed, is advantageous to the miniaturization of missile equipment.
Brief description of the drawings
Fig. 1 is the schematic block circuit diagram of aircraft load terminal image compression of the present invention.
Fig. 2 is Fig. 1 flow chart of data processing figure.
Below in conjunction with the accompanying drawings the present invention is further illustrated with implementation.
Embodiment
Refering to Fig. 1.Programming logic gate array FPGA is that double ARM the kernels FPGA, ADV212 for embedding two ARM kernels are
Image compression chip is also known as codec chip, and QSPI Flash are FPGA program load store device, and LVDS is the input of image
Interface, 4 DDR3 are the special internal memory that ARM cores are embedded in FPGA, and PHY 88E1111 are Ethernet chip, and ADC9639 is
Analog-digital converter, AD9779 are D-A converter.
According to the present invention.With with image input interface LVDS, serial ports, internal memory DDR programming logic gate array FPGA
Chip is core, electrical connection biplate program load store device QSPI Flash, Ethernet chip PHY, A/D converter
ADC, D/A converter DAC and image compression chip ADV212 composition image compression systems；FPGA loading procedure and
ADV212 firmware file is stored in a piece of flash storage jointly；AXI_ is passed through using the embedded ARM kernels in FPGA
Bus buses carry out parameter configuration to ADV212, and the parameter of configuration includes ADV212 initialization registers, coding parameter, image pressure
Demagnification rate, compression signal to noise ratio etc.；Programming logic gate array FPGA is with VHDL language to from image input interface LVDS
The view data of interface is resequenced, framing, verification and segmentation, to complete the collection of view data, reception, the pre- place of compression
Reason input, and by view data storage into Large Copacity internal memory DDR, fpga logic part is realized by large capacity cache DDR schemes
As the matching between input interface LVDS speed and image compression chip ADV212 processing speeds, after fpga logic part will be split
Data give image compression chip ADV212, realization interacts with the view data between ADV212；ADV212 is by data pressure
After contracting, export to programming logic gate array FPGA, after fpga logic part detects the interruption that ADV212 processing is completed, then from
LVDS interface circulation receives original image information and is compressed processing；Data flow after compression of images, by double ARM kernels FPGA
With ADC device AD9639, DAC device AD9779 collective effects, realize modulation, the demodulation function of compressed data stream, and with channel,
Antenna, which coordinates, realizes basic twireless radio-frequency communication function, and data are sent into other aircraft by wireless radio-frequency communication link
Or ground based terminal.
FPGA embeds ARM cores and passes through AXI_bus buses and the figure for an AXI_bus bus peripheral hardware for being used as arm processor
As compression chip ADV212 is connected, ARM is configured by AXI_bus buses to ADV212, and image compression chip ADV212 matches somebody with somebody
The parameter put includes ADV212 initialization registers, coding parameter, compression of images multiplying power volume and compression signal to noise ratio.
Bus AXI_EMC parameter is：Work clock 50MHz, address bus 32, data/address bus 32, ADV212 pairs
The peripheral hardware address space answered is 0x42000000-0x42FFFFFF.
It is 0xFC000000- that image compression chip ADV212 shares a piece of address space with programming logic gate array FPGA
Verification QSPI Flash enter in embedded arm processor in 0xFDFFFFFF program load store device QSPI Flash, FPGA
Row applies the read and write access of layer functions, to carry out online updating to ADV212 firmware information.
Program load store device QSPI Flash address spaces 0xFC000000-0xFDEFFFFF is used to store adding for FPGA
Program is carried, address space 0xFDF00000-0xFDFFFFFF is used for the firmware information for storing ADV212.
It is 0x8 that FPGA, which embeds arm processor and compiles shifting amount to image compression chip ADV212 address by AXI_bus buses,
Coding parameter setting compression multiplying power, and compressed error is controlled into embedded arm processor and FPGA in FPGA within ± 5%
In logical gate share capacity altogether be 1024MB large capacity cache DDR.
Large capacity cache DDR effects have two, and DDR address is embedded at ARM for 0-511MB low address spaces as FPGA
Manage the internal memory of device operation operating system；DDR address is 512-1024MB high address space as ADV212 image data sources
Input-buffer.
Refering to Fig. 2.Image input interface LVDS in LVDS corresponding diagrams 1, FIFO include first in first out buffer FIFO1 and
FIFO2；Dual_port bram are the RAM for including Dual_port bram1 and Dual_port bram2；DMA
It is a kind of controller of high-speed data interactive mode, it is that ARM is embedded in FPGA that dma controller, which includes DMA 1 and DMA 2, DDR3,
The special internal memory of core；Interrupt is the interruption for including Interrupt1 and Interrupt2；ADV212 compresses for special image
Chip；ARM is the embedded ARM cores in FPGA；AXI_Bus be ARM a kind of EBI, peripheral hardware AXI_GPIO0, AXI_
GPIO1, AXI_GPIO2 are articulated in AXI_Bus buses.Double ARM kernels FPGA in corresponding diagram 1, except ADV212 and
Outside DDR3, remaining is the resource in programming logic gate array FPGA.
The ARM cores embedded in FPGA are connected by AXI_bus buses with image compression chip ADV212, and pass through AXI_
Bus buses carry out parameter configuration to ADV212, and after the completion of configuration, fpga logic part is notified by AXI_GPIO0 modes, will
ADV212 control transfers to fpga logic part by embedded ARM.Realized using VHDL language and LVDS is connect in fpga logic part
The collection of mouth view data receives, by data buffer storage in first in first out buffer FIFO1, first in first out buffer FIFO1's
Data write-in bit wide is 16, and data read-out bit wide is 32.First in first out buffer FIFO1 output interface and dual port RAM
Memory Dual_port bram1 port A is connected, and data are delivered into RAM Dual_port bram1, meanwhile,
According to the non-NULL mark in first in first out buffer FIFO1, produce and interrupt Interrupt1, notify the embedded ARM cores in FPGA,
Configuration Control Unit DMA1, data are moved from RAM Dual_port bram1 by port B special to ARM kernels
With internal memory DDR3, Dual_port bram1 port A and B data bit width are 32.ARM kernels calculate DMA1 purpose
Address offset amount and number is moved, after DMA1 is moved and completed a frame image data, produce and interrupt Interrupt2, notify FPGA
In embedded ARM caryogamy put dma controller DMA2, data are moved to double from the special internal memory DDR3 of ARM kernels by port A
Mouth RAM memory Dual_port bram2, DMA2 source address offset is calculated in ARM and moves number, Dual_port
Bram2 port B is connected by FIFO2 with ADV212, and initial data is delivered into ADV212 is compressed, and ADV212 has received one
After frame data, with AXI_GPIO1 notices fpga logic part, by specific delay, data after output squeezing, and by compressed data
Fpga logic part is transferred to, and notifies FPGA logical gate compresses to complete with AXI_GPIO2, then is connect from LVDS interface circulation
Receive original image information and be compressed processing etc..
Programming logic gate array FPGA contains embedded double ARM cores, and kernel setup ADV212 chips write C language application
Program file accesses FPGA QSPI Flash, reads ADV212 firmware file, and pass through AXI_EMC bus access ADV212
Chip, the inside configuration space of ADV212 chips is written to, realizes the configuration to ADV212, the parameter of configuration includes ADV212's
Mode of operation, work clock, frequency multiplication relation, data-interface mode, image resolution ratio, compression multiplying power etc., after the completion of configuration, with
AXI_GPIO0 high impulse mode, notify and surrender ADV212 logical gate of the control to FPGA.
The raw image data of LVDS interface receives.After FPGA logical gate detects AXI_GPIO0 high impulse, open
Beginning receives the raw image data of LVDS interface, writes logical code according to LVDS interface agreement, data are sent into first in first out
Buffer FIFO1.
Raw image data imports internal memory.In FPGA logical gate, RAM Dual_port bram1
Port A be connected first in first out buffer FIFO1 output interface, data are delivered into Dual_port bram1, while according to elder generation
Enter first to go out buffer FIFO1 non-NULL mark, produce and interrupt Interrupt1, notify the embedded ARM cores in FPGA, ARM caryogamy
Dma controller DMA1 is put, data are moved to ARM kernels from RAM Dual_port bram1 by port B
Special internal memory DDR3, DMA1 destination address offset and number is moved, by ARM in Interrupt1 interruption service function
Calculate.
FPGA logical gate produces a two field picture and completely interrupted.ARM kernels are moved number and moved every time according to DMA1's
Data volume, calculate and produce DDR3 receive a two field picture full interrupt identification.Image resolution ratio of illustrating is 1024 × 1024,8
Position gray level image, DMA1 move 32KB data, then produce a two field picture and completely interrupt every time, need DMA1 to move altogether 32 times.Image is expired
Interrupt as Interrupt2 signals.
Raw image data exports internal memory.FPGA embedded ARM kernel responds image completely interrupts Interrupt2,
In Interrupt2 interruption service function, dma controller DMA2 is put in ARM caryogamy, the special internal memory by data from ARM kernels
DDR3A is moved to RAM Dual_port bram2, and DMA2 source address offset is calculated in ARM, and is counted
Move number.
FPGA logical gate send raw image data to compression chip ADV212.In FPGA logical gate, dual port RAM
Memory Dual_port bram2 port B works as RAM by the connected ADV212 of first in first out buffer FIFO2
When valid data be present in Dual_port bram2, data are delivered into ADV212, after often transferring a data, notify ARM,
DMA2 data-moving is carried out again, raw image data is exported into internal memory, and gives ADV212, is moved number and is carried out adding 1
Operation, repeats this step, until ADV212 has received a two field picture, if having received a two field picture can be by DMA2's
Move number and each amount of moving calculates.Citing, image resolution ratio is 1024 × 1024,8 gray level images, and DMA2 is removed every time
32KB data are moved, then ADV212 has received a two field picture, needs DMA2 to move altogether 32 times.
Compressing image data exports.After ADV212 has received a FIFO2 frame image data, notified with AXI_GPIO1
Fpga logic part, switches the direction of ADV212 data-interfaces, and waits ADV212 compressed data to export, ADV212 compression
Data output is started with 0xFFF0 or 0xFFF1, is terminated with 0xFFD9.0xFFF0 or 0xFFF1 beginnings~0xFFD9 (is included
Data between 0xFFD9) are the valid data after compression of images.
Frame switching signal is produced, continues to compress next frame image data.In FPGA logical gate, compressed data is judged
Start (0xFFF0 or 0xFFF1), ending (0xFFD9), and by AXI_GPIO2 high impulse mode, notify FPGA logic
Partly this two field picture compression is completed, then is received raw image data from LVDS interface and be compressed processing etc..Circulation performs, then real
The lasting output of image compression data stream is showed.So far, the implementation method for minimizing the compression of missile-borne terminal image is completed.
It is described above, it is only the embodiment in the present invention, but protection scope of the present invention is not limited thereto, and is appointed
What be familiar with the people of the technology disclosed herein technical scope in, it will be appreciated that expect entirely minimizing missile-borne terminal image
Compression is changed, adjustment, or the partial function unit being related in increase, the reduction present invention, is such as replaced by double ARM kernels FPGA
The FPGA of embedded other processors (Microblaze can PowerPC), is replaced by other types of Flash by Qpsi Flash and deposits
Reservoir etc., these should all cover within the scope of the present invention, and therefore, protection scope of the present invention should be with claim
The protection domain of book is defined.
Claims (10)
1. a kind of aircraft load terminal image compression method, there is following technical characteristic：With with image input interface LVDS,
Serial ports, internal memory DDR programming logic gate array FPGA chip are core, electrically connect biplate program load store device
QSPIFlash, Ethernet chip PHY, A/D converter ADC, D/A converter DAC and image compression chip ADV212
Form image compression system；FPGA loading procedure and ADV212 firmware file are stored in a piece of flash storage jointly
In；Then use the ARM kernels embedded in FPGA to carry out parameter to image compression chip ADV212 by bus AXI_EMC to match somebody with somebody
Put, by programming logic gate array FPGA with Hardware Description Language VHDL to the image from image input interface LVDS
Data are resequenced, framing, verification and segmentation, to complete the collection of view data, reception, compression pretreatment input, and
By view data storage into Large Copacity internal memory DDR, image compression chip is given the data after segmentation in fpga logic part
ADV212 carries out view data interaction, by the data output after compression to programming logic gate array FPGA, FPGA logic cell
After module is according to detecting that ADV212 handles the interruption completed, then is circulated from LVDS interface and receive original image information and pressed
Contracting is handled.
2. aircraft load terminal image compression method as claimed in claim 1, it is characterised in that：After FPGA compression of images
Data flow by the programming logic gate array FPGAs of embedded double ARM kernels and AD9639 A/D converter ADC, AD9779 number/
Weighted-voltage D/A converter DAC collective effects, modulation, the demodulation function of compressed data stream are realized, and coordinate with channel, antenna and realize substantially
Twireless radio-frequency communication function, data are sent to other aircraft or ground based terminal by wireless radio-frequency communication link.
3. aircraft load terminal image compression method as claimed in claim 1, it is characterised in that：FPGA logic cell module
Between image input interface LVDS speed and image compression chip ADV212 processing speeds is realized by large capacity cache DDR
Match somebody with somebody.
4. aircraft load terminal image compression method as claimed in claim 1, it is characterised in that：FPGA embeds ARM cores and led to
The image compression chip ADV212 that AXI_bus buses are crossed with an AXI_bus bus peripheral hardware as arm processor is connected, ARM
ADV212 is configured by AXI_bus buses, the parameter of image compression chip ADV212 configurations initializes comprising ADV212
Register, coding parameter, compression of images multiplying power volume and compression signal to noise ratio.
5. aircraft load terminal image compression method as claimed in claim 1, it is characterised in that：Peripheral hardware corresponding to ADV212
Address space is 0x42000000-0x42FFFFFF, and bus AXI_EMC parameter is：Work clock 50MHz, address bus 32
Position, data/address bus 32.
6. aircraft load terminal image compression method as claimed in claim 1, it is characterised in that：Image compression chip
ADV212 shares the program that a piece of address space is 0xFC000000-0xFDFFFFFF with programming logic gate array FPGA and loaded
Verification QSPI Flash visited using the read-write of layer functions in embedded arm processor in memory QSPI Flash, FPGA
Ask, to carry out online updating to ADV212 firmware information, wherein, program load store device QSPI Flash address spaces
0xFC000000-0xFDEFFFFF is used for the loading procedure for storing FPGA, and address space 0xFDF00000-0xFDFFFFFF is used for
Store ADV212 firmware information.
7. aircraft load terminal image compression method as claimed in claim 6, it is characterised in that：FPGA embeds ARM processing
Device compiles the coding parameter setting compression multiplying power that shifting amount is 0x8 by AXI_bus buses to image compression chip ADV212 address,
And by compressed error control within ± 5%.
8. aircraft load terminal image compression method as claimed in claim 1, it is characterised in that：Embedded ARM in FPGA
Processor shares the large capacity cache DDR that capacity is 1024MB altogether, and large capacity cache DDR ground with the logical gate in FPGA
Location is the internal memory that 0-511MB low address spaces embed arm processor operation operating system as FPGA；DDR address is 512-
Input-buffer of the 1023MB high address space as ADV212 image data sources.
9. aircraft load terminal image compression method as claimed in claim 1, it is characterised in that：Programmable gate array
Containing embedded double ARM cores in FPGA, kernel setup ADV212 chips write the QSPI that C language application file accesses FPGA
Flash, ADV212 firmware file is read, and by AXI_EMC bus access ADV212 chips, be written to ADV212 chips
Internal configuration space, the configuration to ADV212 is realized, after the completion of configuration, in a manner of AXI_GPIO0 high impulse, notify and surrender
Logical gate of the ADV212 control to FPGA.
10. aircraft load terminal image compression method as claimed in claim 1, it is characterised in that：In FPGA logic section
In point, the RAM Dual_port bram1 connected first in first out buffer FIFO1 of port A output interface will
Data deliver to Dual_port bram1, while according to first in first out buffer FIFO1 non-NULL mark, produce interruption
Interrupt1, the embedded ARM cores in FPGA are notified, ARM caryogamy puts dma controller DMA1, by data from RAM
Dual_port bram1 are moved to the special internal memory DDR3 of ARM kernels by port B, DMA1 destination address offset and are removed
Number is moved, is calculated by ARM in Interrupt1 interruption service function；RM kernels are moved number and removed every time according to DMA1's
The data volume of shifting, calculate and produce the full interrupt identification that DDR3 receives a two field picture.
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| CN109313608A (en) * | 2018-09-19 | 2019-02-05 | 深圳市汇顶科技股份有限公司 | Read method, flash controller, system and the storage medium of image verification coefficient |
| CN109379597A (en) * | 2018-10-27 | 2019-02-22 | 北京控制与电子技术研究所 | A kind of compression of images controller based on FPGA |
| CN109451317A (en) * | 2018-12-27 | 2019-03-08 | 郑州云海信息技术有限公司 | A kind of image compression system and method based on FPGA |
| CN110012201A (en) * | 2019-04-10 | 2019-07-12 | 山东尤雷克斯智能电子有限公司 | A kind of USB3.0 ultrahigh speed camera and its working method based on complete programmable SOC |
| CN110730304A (en) * | 2019-10-25 | 2020-01-24 | 北京凯视佳光电设备有限公司 | Intelligent camera for accelerating image acquisition and display |
| CN112463651A (en) * | 2020-12-07 | 2021-03-09 | 长沙景嘉微电子股份有限公司 | QSPI controller, image processor and flash memory access method |
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| CN113608693A (en) * | 2021-07-26 | 2021-11-05 | 中国科学院国家空间科学中心 | Search ordering system and method for satellite-borne on-orbit data |
| CN114090500A (en) * | 2022-01-13 | 2022-02-25 | 南京初芯集成电路有限公司 | All-pass image processing SOC chip and image processing method |
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| CN110012201A (en) * | 2019-04-10 | 2019-07-12 | 山东尤雷克斯智能电子有限公司 | A kind of USB3.0 ultrahigh speed camera and its working method based on complete programmable SOC |
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| CN110730304B (en) * | 2019-10-25 | 2022-06-28 | 北京凯视佳光电设备有限公司 | Intelligent camera for accelerating image acquisition and display |
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