CN104951334A - FPGA double-chip QSPI flash program loading method - Google Patents
FPGA double-chip QSPI flash program loading method Download PDFInfo
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- CN104951334A CN104951334A CN201510263302.2A CN201510263302A CN104951334A CN 104951334 A CN104951334 A CN 104951334A CN 201510263302 A CN201510263302 A CN 201510263302A CN 104951334 A CN104951334 A CN 104951334A
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Abstract
The invention provides an FPGA double-chip QSPI flash program loading method which is high in loading speed, flexible and efficient. According to the technical scheme, the method comprises the steps of establishing an APP for read-write testing of a four-bit-serial peripheral memorizer interface (QSPI) flash in an FPGA software development kit (SDK) of the Xilinx company; conducting parameter configuration on the QSPI flash in the APP, and configuring the QSPI flash to be of an input/output mode; importing a solidification file, downloading the content to be solidified into the flash to a peripheral memory chip DDR3 of the FPGA from a PC, reading the content to be solidified page by page by means of the QSPI flash APP, and writing the content to the solidified to a corresponding address of the QSPI flash. By the adoption of the method, double-chip parallel 8-bit Quad-SPI flash loading is achieved, and the problem that the FPGA development tool SDK and a programming tool IMPACT can not program a 8-bit parallel QSPI flash is solved.
Description
Technical field
The present invention relates to the program loading method of a kind of biplate QSPI flash of Zynq-7000 Series FPGA, and this method is applicable to Zynq-7000 Series FPGA platform used.
Background technology
Along with the development of programming logic gate array FPGA (hereinafter referred to as FPGA) technology, the function of FPGA is more and more stronger, and type also gets more and more.Due to FPGA inner structure, the program of FPGA is generally all stored in outside nonvolatile memory, and upon power-up of the system, program is loaded into FPGA from external memory storage and run, this process is called as program and loads.Zynq-7000 Series FPGA (hereinafter referred to as Zynq-7000) is a novel FPGA that Xilinx company of the U.S. releases, compared with other model FPGA, its processing unit is divided into PS and PL bis-part, PS refers to embedded pair of arm processor core in zynq-7000, and PL partly refers to traditional fpga logic part.Zynq-7000 takes as the leading factor with ARM core, guided, configure PL part, therefore Zynq-7000 is more prone to classify as the flush bonding processor similar with PowerPC from principle of work by ARM, instead of a kind of traditional FPGA.The program loading method of Zynq-7000 has multiple, usually has 4 bit serial peripheral memory interface Quad-SPI flash (hereinafter referred to as Quad-SPI flash) loading methods, NAND flash storer load mode, NOR flash storer load mode, SD card load mode four kinds.Quad-SPI flash program load mode has the advantage that program loading frequency is high, chip area footprints is little, therefore is used widely.
Quad-SPI flash program load mode is divided into again monolithic 4-bit load mode, and biplate walks abreast 8-bit load mode and biplate cascade 4-bit load mode three kinds, as shown in the table:
Because Zynq-7000 is powerful, the capacity of general required flash storer is greater than 16MB, therefore usually adopt 2 Quad-SPI flash storing program therefors, the programming process of flash is generally provided by developing software of FPGA, the ISE/Vivado that develops software of Zynq-7000 Series FPGA also provides Quad-SPI flash program burn writing function, but existing problems, namely programming can not be carried out to the biplate of the Quad-SPI flash 8-bit mode that walks abreast, cause Zynq-7000 Series FPGA can not carry out normal program loading, the self-starting function that powers on cannot be completed, high performance Zynq-7000 Series FPGA is applied limited.
Current Zynq-7000 Series FPGA develops software (version is ISE14.7 or vivado2013.4) can't to walk abreast QSPI flash by programming 8bit, usual technician only can use developing software of FPGA to realize the flash programming function of FPGA, does not have other to select.
Summary of the invention
Task of the present invention is for the deficiencies in the prior art, can not correctly to walk abreast the defect (being defined as the bug problem developed software of FPGA) of QSPI flash by programming biplate 8bit for developing software of Zynq-7000 Series FPGA, there is provided a kind of loading velocity fast, the program loading method of the biplate QSPI flash of flexible and efficient, new Zynq-7000 Series FPGA, developing software of FPGA must be relied on carry out the restriction of QSPI flash programming to depart from, the self-starting function that powers on of FPGA is accomplished.
Above-mentioned purpose of the present invention can be reached by following measures, the program loading method of a kind of FPGA biplate QSPI flash, it is characterized in that comprising the steps: in Xilinx company programmable logic array FPGA SDK (Software Development Kit) SDK, a newly-built application A PP to the readwrite tests of QSPI flash (hereinafter referred to as APP); In APP, carry out parameter configuration to QSPI flash, configuration QSPI flash is I/O pattern, i.e. IO pattern (hereinafter referred to as IO pattern); Import curing document, download to the peripheral hardware internal memory DDR3 (hereinafter referred to as DDR3) of FPGA by needing the content be cured in flash from PC, read needing the content of solidification to press page by QSPI flash APP application program, and be written in the corresponding address of QSPI flash.
The present invention has following beneficial effect compared to prior art:
The present invention adopts in Xilinx FPGA developing instrument SDK, a newly-built APP program to the readwrite tests of QSPI flash, based on autonomous coding programming, provide a kind of new programming mode, thus the program of Zynq-7000 Series FPGA is solidified, make the biplate 8bit of the current zynq-7000 QSPI flash programming method that walks abreast achieve and grow out of nothing;
The biplate 8bit that the present invention is based on autonomous coding programming zynq-7000 walks abreast QSPI flash, depart from the restriction developed software to FPGA, the biplate in Quad-SPI flash that can the be correct 8-bit flash that walks abreast carries out programming, the program of Zynq-7000 Series FPGA is solidified, and solving the walk abreast loading problem of 8-bit Quad-SPI flash and FPGA developing instrument SDK and flashburn tools IMPACT of biplate can not walk abreast the problem of QSPI flash by programming 8bit.
The present invention has the following advantages compared to prior art tool:
Burn writing speed is fast: the FPGA programming mode original compared to other, burn writing speed is constant, not easily adjust, the loading method that the present invention proposes, will need the content be cured in flash to download to the peripheral hardware internal memory DDR3 of FPGA from PC, presses page read by QSPI flash APP application program, and be written in the address of QSPI flash, the QSPI flash model that can use according to reality, adjustment programming frequency and speed, make it with maximal rate programming.
Flexible and efficient.The present invention is in Zynq-7000 Series FPGA, biplate 8bit based on SDK application program, completely independent development Zynq-7000 Series FPGA walks abreast the program loading method of QSPI flash, depart from necessary developing software of FPGA of dependence and carried out the restriction of QSPI flash programming, the self-starting function that powers on of FPGA is accomplished.
Accompanying drawing explanation
Accompanying drawing is the connected mode of Zynq-7000 Series FPGA and QSPI flash.
Fig. 1 is that Zynq-7000 Series FPGA connects 1 QSPI flash, and data are 4 bit bit wide fashion embodiment schematic diagram.
Fig. 2 is that Zynq-7000 Series FPGA connects 2 QSPI flash, cascade system, and data are 4 bit bit wide embodiment schematic diagram.
Fig. 3 is that Zynq-7000 Series FPGA connects 2 QSPI flash, parallel way, and data are 8 bit bit wide embodiment schematic diagram.
Embodiment
Consult Fig. 1-Fig. 3.Serial peripheral memory interface and the 4 bit serial peripheral memory connected modes of Zynq-7000 Series FPGA have 3 kinds, the wherein serial peripheral memory interface of the Series FPGA of Zynq-7000 shown in Fig. 1, have 4bit data line to be connected with 14 bit serial peripheral memory QSPI flash, this connected mode is called monolithic 4bit bit wide connected mode; The serial peripheral memory interface of the Series FPGA of Zynq-7000 shown in Fig. 2,4bit data line is had to be connected with 24 bit serial peripheral memory QSPI flash, 24 bit serial peripheral memory QSPI flash are called QSPI_flash_1, QSPI_flash_2, this connected mode is called monolithic 4bit bit wide cascade system; The serial peripheral memory interface of the Series FPGA of Zynq-7000 shown in Fig. 3,8bit data line is had to be connected with 24 bit serial peripheral memory QSPI flash, 24 bit serial peripheral memory QSPI flash are called QSPI_flash_1, QSPI_flash_2, this connected mode is called biplate 8bit bit wide parallel mode.
The program loading method of FPGA biplate QSPI flash specifically comprises the steps: in Xilinx company programmable logic array FPGA SDK (Software Development Kit) SDK, first a newly-built application A PP to the readwrite tests of QSPI flash (hereinafter referred to as APP), for the readwrite tests to QSPI flash; In SDK, utilize new construction guide, a newly-built APP application program, object is tested the peripheral hardware biplate 8bit of the Zynq-7000 Series FPGA QSPI flash that walks abreast, by modifying to QSPI flash APP application program, to complete, two QSPI flash to be read and write, erase operation.In APP application program, carry out parameter configuration to QSPI flash, configuration QSPI flash is I/O pattern, i.e. IO pattern (hereinafter referred to as IO pattern); Carry out read operation again, read the id information of QSPI flash chip in APP application program, and obtain the relevant information of QSPI flash, as information such as manufacturer, capacity, block sizes.Arrange register: in APP application program, the bit 1 arranging the configuration register 1 (Configuration Register 1, CR1) of QSPI flash chip is 1, makes QSPI flash chip support 4bit operation.Then curing document is imported, the content be cured in flash will be needed, below suppose that its file is called function.bin, download to the peripheral hardware internal memory DDR3 (hereinafter referred to as DDR3) of Zynq-7000 Series FPGA from PC, import in the peripheral hardware internal memory DDR3 of Zynq-7000 Series FPGA by curing document function.bin by JTAG, this operation can be completed by input command in the debugging interface XMD of SDK, order is dow – data function.bin 0x100000, represent and function.bin is deposited the address that start address is 0x100000, erasing QSPI flash, in APP application program, according to the model of QSPI flash, send specific erase command, its erase command is 60h, or C7h, h are expressed as 16 systems, carries out erase operation to QSPI flash, programming curing document, in APP application program, the function.bin file being positioned at 0x100000 place, address is read by the page of QSPI flash, and be written in QSPI flash, write order used is 02h or 32h, can not to walk abreast the problem of QSPI flash by programming 8bit for solving the FPGA developing instrument SDK of Xilinx company and FPGA flashburn tools IMPACT.
QSPI flash model used in the present invention is the S25FL128 of Spasion company, and method provided by the invention is also applicable to the QSPI flash model of other company.
Claims (9)
1. the program loading method of a FPGA biplate QSPI flash, it is characterized in that comprising the steps: in Xilinx company programmable logic array FPGA SDK (Software Development Kit) SDK, a newly-built application A PP to the readwrite tests of 4 bit serial peripheral memory interface QSPI flash; In APP, carry out parameter configuration to QSPI flash, configuration QSPI flash is I/O pattern IO; Import curing document, will the content be cured in flash be needed to download to the peripheral hardware memory chip DDR3 of FPGA from PC, read needing the content of solidification to press page by QSPI flash APP application program, and be written in the corresponding address of QSPI flash.
2. the program loading method of FPGA biplate QSPI flash as claimed in claim 1, it is characterized in that: FPGA is Zynq-7000 series, the QSPI flash interface of Zynq-7000 Series FPGA has 8 position datawires, be divided into 24 position datawires, be connected with 2 QSPI flash respectively, 2 QSPI flash are respectively qspi flash_1, qspi flash_2.
3. the program loading method of FPGA biplate QSPI flash as claimed in claim 1 or 2, it is characterized in that: in FPGA SDK (Software Development Kit) SDK, utilize new construction guide, a newly-built APP application program, the peripheral hardware biplate 8bit of the Zynq-7000 Series FPGA QSPI flash that walks abreast is tested, by modifying to QSPI flash APP application program, complete the reading and writing to two QSPI flash, erase operation.
4. the program loading method of FPGA biplate QSPI flash as claimed in claim 1, is characterized in that: when carrying out read operation, is read the id information of QSPI flash chip by APP application program, obtains the relevant information of QSPI flash.
5. the program loading method of FPGA biplate QSPI flash as claimed in claim 1, it is characterized in that: in APP application program, the bit 1 arranging the configuration register 1 of QSPI flash chip is 1, makes QSPI flash chip support 4bit operation.
6. the program loading method of FPGA biplate QSPI flash as claimed in claim 1, it is characterized in that: curing document function.bin is imported in the peripheral hardware internal memory DDR3 of Zynq-7000 Series FPGA by JTAG, this operation can be completed by input command in the debugging interface XMD of SDK, order is dow – data function.bin 0x100000, represents and function.bin is deposited the address that start address is 0x100000.
7. the program loading method of FPGA biplate QSPI flash as claimed in claim 1, is characterized in that: in APP application program, according to the model of QSPI flash, sends specific erase command, carry out erase operation to QSPI flash, programming curing document.
8. the program loading method of FPGA biplate QSPI flash as claimed in claim 1, it is characterized in that: in APP application program, the function.bin file being positioned at 0x100000 place, address is read by the page of QSPI flash, and be written in QSPI flash, write order used is that 02h or 32h, h are expressed as 16 systems.
9. the program loading method of FPGA biplate QSPI flash as claimed in claim 1, is characterized in that: the QSPI flash model used is S25FL128, and its erase command is 60h, or C7h, h are expressed as 16 systems.
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| CN105515709A (en) * | 2015-12-07 | 2016-04-20 | 中国电子科技集团公司第三十二研究所 | Time synchronization device based on domestic FPGA and uclinux operating system |
| CN105573800A (en) * | 2015-12-22 | 2016-05-11 | 中船重工（武汉）凌久电子有限责任公司 | Single-board or multi-board system based on ZYNQ and on-line updating method |
| CN106201580A (en) * | 2016-06-30 | 2016-12-07 | 北京智联友道科技有限公司 | Internet of Things experiment module program fast restore method |
| CN107196695A (en) * | 2017-04-07 | 2017-09-22 | 西安电子科技大学 | Inter-satellite Links test system based on Zynq |
| CN107347158A (en) * | 2017-06-01 | 2017-11-14 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Aircraft load terminal image compression method |
| CN107948653A (en) * | 2017-11-03 | 2018-04-20 | 中国航空无线电电子研究所 | A kind of video compress and recorder |
| CN108021385A (en) * | 2017-12-29 | 2018-05-11 | 北京神州龙芯集成电路设计有限公司 | A kind of programming system and method for onboard SPI Flash |
| CN108427651A (en) * | 2018-03-15 | 2018-08-21 | 天津光电丰泰科技有限公司 | A kind of difunctional multiplexing method based on Zynq Qspi-Flash |
| CN111124433A (en) * | 2018-10-31 | 2020-05-08 | 华北电力大学扬中智能电气研究中心 | Program programming device, system and method |
| CN111563059A (en) * | 2019-12-18 | 2020-08-21 | 中国船舶重工集团公司第七0九研究所 | PCIe-based multi-FPGA dynamic configuration device and method |
| CN112114874A (en) * | 2020-08-20 | 2020-12-22 | 北京百度网讯科技有限公司 | Data processing method and device, electronic equipment and storage medium |
| CN112445540A (en) * | 2020-11-10 | 2021-03-05 | 惠州市创荣发智能科技有限公司 | Program operation method, system, terminal and storage medium |
| CN113434207A (en) * | 2021-06-09 | 2021-09-24 | 山东航天电子技术研究所 | Zynq UltraScale + SoC configuration file loading reconstruction method |
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| CN107347158A (en) * | 2017-06-01 | 2017-11-14 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Aircraft load terminal image compression method |
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| CN111124433A (en) * | 2018-10-31 | 2020-05-08 | 华北电力大学扬中智能电气研究中心 | Program programming device, system and method |
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| CN111563059A (en) * | 2019-12-18 | 2020-08-21 | 中国船舶重工集团公司第七0九研究所 | PCIe-based multi-FPGA dynamic configuration device and method |
| CN111563059B (en) * | 2019-12-18 | 2022-05-24 | 中国船舶重工集团公司第七0九研究所 | PCIe-based multi-FPGA dynamic configuration device and method |
| CN112114874A (en) * | 2020-08-20 | 2020-12-22 | 北京百度网讯科技有限公司 | Data processing method and device, electronic equipment and storage medium |
| CN112445540A (en) * | 2020-11-10 | 2021-03-05 | 惠州市创荣发智能科技有限公司 | Program operation method, system, terminal and storage medium |
| CN113434207A (en) * | 2021-06-09 | 2021-09-24 | 山东航天电子技术研究所 | Zynq UltraScale + SoC configuration file loading reconstruction method |
| CN113434207B (en) * | 2021-06-09 | 2023-03-24 | 山东航天电子技术研究所 | Zynq UltraScale + SoC configuration file loading reconstruction method |
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