CN107704285B

CN107704285B - Multi-version configuration chip, system and method for field programmable gate array

Info

Publication number: CN107704285B
Application number: CN201710889479.2A
Authority: CN
Inventors: 谢元禄; 刘明; 张坤; 呼红阳; 霍长兴; 刘璟; 毕津顺; 王艳; 卢年端
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2017-09-27
Filing date: 2017-09-27
Publication date: 2021-01-05
Anticipated expiration: 2037-09-27
Also published as: CN107704285A

Abstract

The present disclosure provides a FPGA multi-version configuration chip, the chip is a package, including: the storage unit is used for storing a configuration data file of the FPGA; the control unit is connected with the storage unit and can perform reading, erasing and writing operations on the storage unit, and the control unit comprises: the version switching communication interface is used for receiving data, address and control information by the control unit to realize online switching of the matched data file, and after receiving the first address of the matched data version, the control unit reads the matched data of the corresponding version according to the specified address and completes FPGA configuration; and the FPGA configuration interface is used for controlling the interaction of the unit and the FPGA to complete the on-line configuration function of the FPGA. The method and the device provide more options for FPGA version configuration, and can perform version switching under the condition that the system is not powered down.

Description

Multi-version configuration chip, system and method for field programmable gate array

Technical Field

The present disclosure relates to the Field of Programmable logic device configuration, and in particular, to a Field Programmable Gate Array (FPGA) multi-version configuration chip, system, and method.

Background

An FPGA (Field Programmable Gate Array) is a common general logic device in a modern electronic system, and its functions can be customized by a user, and in practical application, the user can make the FPGA implement various functions by changing different configuration code streams. Due to their excellent flexibility and good versatility, FPGAs are finding increasingly widespread use in a variety of electronic systems.

In the mainstream application at present, the most common is SRAM type FPGA, and its code is stored in SRAM memory inside the FPGA chip. The SRAM is a volatile memory, and the configuration information is completely lost after the FPGA is powered off, so in practical application, the FPGA is often connected to a corresponding configuration memory chip (also referred to as a "configuration chip"), and the two are used in cooperation. After each power-on, the FPGA needs to read configuration information from the configuration chip to complete its own initialization.

The configuration chip is used for providing configuration data for the FPGA after being electrified, in the current mainstream application, one configuration chip can only store one code stream file, the configuration codes obtained after the FPGA is electrified every time are the same, and the function executed by the FPGA is fixed and unchanged. And the storage of a plurality of code stream files needs to be divided by taking fixed bytes as units, the code allocation of each version can occupy 1 or more 8Mbit data blocks, so that the storage space is wasted, and the code allocation can not be replaced during the normal working period of the FPGA, and the system can be switched only by power failure.

BRIEF SUMMARY OF THE PRESENT DISCLOSURE

Technical problem to be solved

The present disclosure provides an FPGA multi-version configuration chip, system and method to at least partially solve the technical problems set forth above.

(II) technical scheme

According to an aspect of the present disclosure, there is provided an FPGA multi-version configuration chip, where the chip is a package, including: the storage unit is used for storing a configuration data file of the FPGA; the control unit is connected with the storage unit and can perform reading, erasing and writing operations on the storage unit, the control unit can acquire data in the storage unit, modify the data content in the storage unit and control the storage unit, and the control unit comprises: the version switching communication interface is used for transmitting data, addresses and control information between the control unit and the outside to realize online switching of the configuration data file, wherein the outside can transmit the first address of the currently selected configuration data version to the control unit, and the control unit can read the configuration data of the corresponding version according to the specified address and complete FPGA configuration; and the FPGA configuration interface is used for realizing the configuration of the FPGA by the interaction of the control unit and the FPGA and comprises a working time sequence signal and a control signal interface.

In some embodiments of the present disclosure, the FPGA multi-version configuration chip includes three storage units, data in the three storage units is subjected to triple modular redundancy processing, and votes for the data from the three storage units through a voting circuit, where inputs of the voting circuit are outputs of the three storage units, respectively.

In some embodiments of the present disclosure, the version switching communication interface of the control unit is an SPI communication interface, a UART serial interface, or an IIC communication interface.

According to another aspect of the present disclosure, there is provided a system for multi-version configuration of an FPGA, which employs the FPGA multi-version configuration chip of any one of claims 1 to 3, the system further comprising: and the version switching module is used for controlling the on-line switching of the code matching version of the FPGA, and the function of the FPGA can be changed in real time or the code matching version of the FPGA can be switched on line through the version switching module during the normal working period of the FPGA.

In some embodiments of the present disclosure, when the function of the FPGA needs to be updated, that is, when the code configuration version of the FPGA needs to be updated, the version switching module switches the communication interface through the version of the control unit in the FPGA multi-version configuration chip, transmits the first address of the desired target version in the storage unit to the control unit, and then resets the configuration logic of the FPGA through the PROG _ B signal; after the reset signal of the PROG _ B is cancelled, the control unit reads the configuration code of the corresponding version from the storage unit according to the first address received by the version switching communication interface of the previous control unit, and transmits the configuration code to the FPGA.

In some embodiments of the present disclosure, the version switching module is disposed in the FPGA or in a third-party controller outside the FPGA chip; under the condition of adopting a third-party controller, a superior controller is arranged for judging when the FPGA needs to update the version and informing the third-party controller to switch the version at the correct time, and the superior controller is connected to the FPGA and the third-party version switching module.

In some embodiments of the present disclosure, the timing for switching the code matching versions of the FPGA may be determined by the user logic of the FPGA itself or by another upper computer; when the upper computer considers that the code matching version of the FPGA needs to be switched, a version switching instruction and the first address of the new version in the storage unit can be sent to the FPGA through the instruction link, and after the FPGA receives the instruction and the address, the corresponding version switching operation is completed through the version switching module.

According to another aspect of the present disclosure, there is provided a method for multi-version configuration of an FPGA, including:

step S1, the FPGA multi-version configuration chip and the FPGA to be configured are electrified, the FPGA carries out initialization configuration, and the configuration code of the lowest address space, namely the configuration code of the 1 st version, is loaded in a default mode when the FPGA is electrified;

step S2, the FPGA enters a normal working mode, and when the FPGA is in the normal working mode, if the function of the FPGA needs to be updated, namely the code matching version of the FPGA needs to be updated, the step S3 is switched to; if the function of the FPGA does not need to be updated, the operation is continuously returned to the normal mode;

step S3, the version switching module transmits the first address of the expected target version in the storage unit to the control unit in the FPGA multi-version configuration chip through the version switching communication interface of the control unit in the FPGA multi-version configuration chip;

and step S4, restarting a new round of FPGA configuration through a reset signal, returning to step S2 after the configuration is finished, and enabling the FPGA to enter a normal working mode.

In some embodiments of the present disclosure, the step S3 includes:

in the substep S31, the version switching module firstly sets the chip select signal CS # to be valid, then turns over the clock signal SCLK and the output data signal SO, and transmits the first address of the expected target version in the storage unit to the control unit in the FPGA multi-version configuration chip;

substep S32, after the control unit successfully receives the first address of the target version, setting the SO to be in a predetermined state as a handshake response;

in the substep S33, when the version switching module detects that the output data signal SO transmitted by the control unit is configured to be in the predetermined state at the SI signal end, it is determined that the control unit successfully receives the first address of the target version, and the handshake process is completed;

in the substep S34, the version switching module sets PROG _ B connected with the reset pin of the FPGA to be low level and keeps for a period of time, and resets the self configuration logic of the FPGA;

in sub-step S35, after the version switch module releases PROG _ B to the high level again, the FPGA goes out of the reset state and starts a new loading operation from the storage unit, and the loaded target configuration code is the configuration code of the target version specified by the version switch communication interface.

In some embodiments of the present disclosure, the predetermined state may be a high level or a specific level sequence lasting for more than a predetermined time.

(III) advantageous effects

According to the technical scheme, the FPGA multi-version configuration chip, the system and the method have at least one of the following beneficial effects:

(1) because the storage unit can contain a plurality of matched code versions, and the number of the matched code versions is not limited, any plurality of matched code versions can be stored in the storage unit, more choices are provided for FPGA version configuration, and version switching can be performed under the condition that a system is not powered down;

(2) because the initial address of each version of the configuration code in the storage unit is not limited, the configuration codes of each version can be continuously arranged in the storage unit, and the problem of storage space waste does not exist;

(3) the storage unit can select a memory with a capacity of 128Mbit, 256Mbit or more, and can be applied to the configuration of a large-scale FPGA without cascading multiple chips;

(4) by encapsulating the control unit and the storage unit in 1 encapsulating body, the appearance form of the encapsulating body is 1 chip, so that the number of chips in the FPGA system can be reduced, the weight of the system is further reduced, and the reliability of the system is improved.

Drawings

Fig. 1 is a schematic structural diagram of an FPGA multi-version configuration chip according to an embodiment of the present disclosure.

Fig. 2 is a schematic structural diagram of an FPGA multi-version configuration chip having three memory cells according to an embodiment of the present disclosure.

Fig. 3 is a schematic structural diagram of a voting circuit in a control unit of an FPGA multi-version configuration chip having three memory cells according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of a system configured by multiple versions of an FPGA according to an embodiment of the present disclosure.

Fig. 5 is a schematic diagram of a working timing sequence of the version switching module according to the embodiment of the disclosure.

Fig. 6 is a schematic structural diagram of a version switching module implemented by a third-party controller according to an embodiment of the disclosure.

Fig. 7 is a schematic structural diagram illustrating a timing for determining switching of code allocation versions of an FPGA according to an instruction of an upper computer in the embodiment of the present disclosure.

Fig. 8 is a flowchart of a method for configuring multiple versions of an FPGA according to an embodiment of the present disclosure.

Detailed Description

The present disclosure provides a field programmable gate array multi-version configuration chip, system and method. For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

Certain embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the disclosure are shown. Indeed, various embodiments of the disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements.

In a first exemplary embodiment of the present disclosure, an FPGA multi-version configuration chip is provided. Fig. 1 is a schematic structural diagram of an FPGA multi-version configuration chip according to a first embodiment of the present disclosure. As shown in fig. 1, the FPGA multi-version configuration chip of the present disclosure is a package, and includes at least one storage unit and a control unit.

Each component of the FPGA multi-version configuration chip of this embodiment is described in detail below.

At least one storage unit connected with the control unit and controlled by the control unit; the storage unit stores the configuration data file of the FPGA. When the system is built, a memory model with larger capacity (such as 128Mbit, 256Mbit and the like) can be selected to provide more code data storage space.

In the storage unit, a plurality of versions of FPGA configuration codes can be stored, and the start address of each version of configuration code is not limited. In the configuration code files of the multiple versions, one configuration code is used as a boot area, and the meaning is that after the system is powered on, the control unit reads from the first address of the boot area by default and configures the FPGA. And after all the data of the guide area are read, the FPGA configuration is finished. Under the default condition, in the initial configuration after power-on, the control unit cannot read the configuration code files of other versions in the storage unit.

The control unit can perform reading, erasing, writing and other operations on the storage unit, and through the operations, the control unit can acquire the data in the storage unit and also can modify the data content in the storage unit. The control unit is externally provided with a JTAG interface, an FPGA configuration interface and a version switching communication interface. Through the JTAG interface, the control unit can communicate with an external JTAG upper computer to obtain control information and data of the upper computer and return working states and data of the upper computer. The control unit is used as a bridge, and the JTAG upper computer can realize the operations of reading, erasing, writing and the like on the storage unit through the control unit. When the multi-version configuration chip of the FPGA is used for configuring the FPGA, the JTAG upper computer can write configuration codes required by the FPGA to the storage unit.

The version switching communication interface of the control unit is used for transmitting data, addresses, control information and the like between the control unit and the outside, wherein the outside can transmit the first address of the currently selected configuration code version to the control unit, and the control unit can read the configuration code data of the corresponding version according to the specified address and complete FPGA configuration. And loading the configuration code of the boot area by default when the FPGA is powered on every time, namely loading the configuration code of the 1 st version of the lowest address space by default after the FPGA is powered on. Later, during the normal work period of the FPGA, the version can be replaced through the control unit, and the system does not power down in the version replacement period. The outside world can also access the storage unit through the version switching communication interface and perform reading, erasing, writing and other operations on data in the storage unit through the control unit.

The working time sequence of the FPGA configuration interface of the control unit and the control relation among all signals are compatible with the working specification of the configuration interface of the FPGA product. Through the FPGA configuration interface, the control unit can be matched with the FPGA to complete the power-on configuration function of the FPGA. When the function is executed, the control unit reads the configuration data in the storage unit, arranges the configuration data into a data format compatible with the FPGA configuration interface specification, and transmits the data format to the FPGA through the FPGA configuration interface.

In an embodiment, the storage unit stores a configuration data file of the Xilinx FPGA, and the FPGA configuration interface is a configuration interface compatible with the Xilinx FPGA.

In an embodiment, the version switching communication interface of the control unit is an SPI communication interface, and in different embodiments, the version switching communication interface of the control unit may be any other type of communication interface such as a UART serial port, an IIC, and the like.

In one embodiment, the FPGA multi-version configuration chip comprises one storage unit, in different embodiments, the FPGA multi-version configuration chip comprises three storage units, and the reliability of configuration data can be greatly improved by performing triple modular redundancy processing on data in the three storage units. Fig. 2 is a schematic structural diagram of an FPGA multi-version configuration chip having three memory cells according to an embodiment of the present disclosure. In this scenario, there should be a voting circuit in the control unit to vote for data from 3 memory cells, as shown in FIG. 2. Fig. 3 is a schematic structural diagram of a voting circuit in a control unit of an FPGA multi-version configuration chip having three memory cells according to an embodiment of the present disclosure. As shown in fig. 3, the inputs to the voting circuit are the outputs of 3 memory cells, respectively. The voting circuit is a circuit processing mechanism, and the basic idea is that 2 is taken as 3, and in case of error of 1 input path, the output can still give correct result.

The FPGA multi-version configuration chip is prepared by adopting a wafer to carry out processes such as film deposition, photoresist coating, exposure, photoresist removal, etching, doping, thermal annealing and the like, and the packaging form comprises the following steps: QFP, QFN, PGA, BGA, etc.

So far, introduction of the FPGA multi-version configuration chip is completed in the first embodiment of the present disclosure.

In a second exemplary embodiment of the present disclosure, a system for multi-version configuration of an FPGA is provided. Fig. 4 is a schematic structural diagram of a system configured by multiple versions of an FPGA according to an embodiment of the present disclosure. As shown in fig. 4, the system includes a JTAG upper computer, an FPGA multi-version configuration chip, and a version switching module, wherein:

the JTAG upper computer is used for downloading the FPGA code matching file to the FPGA multi-version configuration chip, the downloading of the code matching file can be realized through a USB port or other interfaces, a group of JTAG data lines are expanded through a downloading line and connected to the JTAG interface of the FPGA multi-version configuration chip, and the connection between the FPGA multi-version configuration chip and the JTAG upper computer can be established through the mode. In fig. 4, the JTAG upper computer can perform operations such as reading, erasing, and writing to the memory cell through the JTAG link, and can rewrite and update the data file of the arbitrary 1 or more versions. During the development and debugging of the FPGA product, the FPGA developer can conveniently rewrite target FPGA configuration data in the storage unit through the JTAG upper computer. After the FPGA developer finishes updating the data in the storage unit through the JTAG upper computer, the connection between the JTAG upper computer and the JTAG interface of the FPGA multi-version configuration chip can be disconnected. Generally speaking, after a user finishes development and debugging, a JTAG upper computer is not needed to frequently modify FPGA configuration codes in a storage unit, and the FPGA configuration can be finished only by an FPGA multi-version configuration chip.

The FPGA multi-version configuration chip is used for carrying out multi-version FPGA configuration. In fig. 4, after the user completes updating of the configuration data in the storage unit through the JTAG upper computer, the system is powered off and powered on again, and then the control unit of the FPGA multi-version configuration chip reads the version configuration data corresponding to the boot sector in the storage unit, and transmits the data to the FPGA through the FPGA configuration interface, thereby completing the configuration of the FPGA. After the FPGA finishes the power-on initialization configuration, the FPGA enters a normal working state.

And the version switching module is used for controlling the code matching version of the on-line switching FPGA. Through the version switching module in fig. 4, during the normal operation of the FPGA, the function of the FPGA can be changed in real time, or the code configuration version of the FPGA can be switched online. When the function of the FPGA needs to be updated, namely the code configuration version of the FPGA needs to be updated, the version switching module switches the communication interface through the version of the control unit in the FPGA multi-version configuration chip, transmits the first address of the expected target version in the storage unit to the control unit, and then resets the configuration logic of the FPGA through the PROG _ B signal. When the reset signal of the PROG _ B is cancelled, the FPGA starts a new configuration process, and in the configuration process, the control unit reads the configuration code of the corresponding version from the storage unit according to the first address received by the version switching communication interface of the previous control unit and transmits the configuration code to the FPGA. In this way, the code in the FPGA can be switched from one version to another without power loss.

In an embodiment of the present disclosure, an operation timing sequence of the version switching module of fig. 4 is shown in fig. 5, and the operation timing sequence is as follows:

when the user logic in the FPGA judges that the configuration code version needs to be switched, the version switching module firstly sets the chip selection signal CS # to be effective (namely low level), then turns over the clock signal SCLK and the output data signal SO, and transmits the first address of the expected target version in the storage unit to the control unit in the configuration memory of the FPGA multi-version configuration chip. And after the control unit successfully receives the first address of the target version, pulling up the SO for a period of time to serve as a handshake response. And when the version switching module in the FPGA detects a high level on the signal SI, the handshake process is considered to be finished. And then, the version switching module sets PROG _ B to be low level and keeps for a period of time, and resets the configuration logic of the FPGA. After PROG _ B is released to high level again, the FPGA starts a new loading operation from the FPGA multi-version configuration chip memory, and the loaded target configuration code is the configuration code of the target version specified by the SPI interface before.

In one embodiment, the version switching module is disposed in the FPGA, and in different embodiments, the version switching module disposed inside the FPGA may be replaced with a third-party controller outside the FPGA according to a specific requirement of the system. Fig. 6 is a schematic structural diagram of a version switching module implemented by a third-party controller according to an embodiment of the disclosure. As shown in fig. 6, the third controller may be a CPLD, a single chip microcomputer or other FPGA. In the case of using the third controller, a superior controller (not shown) is required to determine when the FPGA needs to update the version, and notify the third controller to switch the version at the correct time. And the upper-level controller is connected to the FPGA and the third-party version switching module.

In one embodiment, the timing for switching the code matching versions of the FPGA can be determined by the user logic of the FPGA, and in different embodiments, the timing for switching the code matching versions can be determined by another upper computer. Fig. 7 is a schematic structural diagram illustrating a timing for determining switching of code allocation versions of an FPGA according to an instruction of an upper computer in the embodiment of the present disclosure. As shown in fig. 7, the FPGA is connected to another upper computer through an instruction link. When the upper computer considers that the code matching version of the FPGA needs to be switched, a version switching instruction and the first address of the new version in the storage unit can be sent to the FPGA through the instruction link, and after the FPGA receives the instruction and the address, the corresponding version switching operation is completed through the version switching module.

Certainly, the hardware structure may further include functional modules such as a power module (not shown), which can be understood by those skilled in the art, and those skilled in the art may also add corresponding functional modules according to the functional requirements, which are not described herein.

For the purpose of brief description, any technical features of the first embodiment that can be applied to the same are described herein, and the same description is not repeated.

So far, the introduction of the system with the multi-version FPGA configuration of the second embodiment of the disclosure is completed.

In a third exemplary embodiment of the present disclosure, a method of multi-version configuration of an FPGA is provided. Fig. 8 is a flowchart of a method for configuring multiple versions of an FPGA according to an embodiment of the present disclosure. As shown in fig. 8, the workflow of the complete steps of the method for performing multi-version configuration on the FPGA is as follows:

step S1, electrifying the FPGA multi-version configuration chip and the FPGA to be configured, carrying out initialization configuration on the FPGA, and loading configuration codes of the boot area in a default mode when the FPGA is electrified;

step S3, the version switching module switches the communication interface through the version of the control unit in the FPGA multi-version configuration chip, and transmits the first address of the expected target version in the storage unit to the control unit;

further, the step S3 includes:

in the substep S31, the version switching module firstly sets the chip select signal CS # to be valid (i.e. low level), then turns over the clock signal SCLK and the output data signal SO, and transmits the first address of the expected target version in the storage unit to the control unit in the FPGA multi-version configuration chip configuration memory;

in the substep S33, when the version switching module detects that the output data signal SO transmitted by the control unit is configured to be in the predetermined state at the SI signal end, it is determined that the control unit successfully receives the first address of the target version, and the handshake process is completed; the predetermined state may be a high level or a specific level sequence lasting for a predetermined time or more;

in the substep S34, the version switching module sets PROG _ B to be low level and keeps for a period of time, and resets the configuration logic of the FPGA;

in sub-step S35, after PROG _ B is released to high level again, the FPGA starts a new loading operation from the storage unit of the FPGA multi-version configuration chip, and the loaded target configuration code is the configuration code of the target version specified by the version switching communication interface.

Further, in step S4, the version switching module resets the configuration logic of the FPGA through the PROG _ B reset signal. When the reset signal of the PROG _ B is cancelled, the FPGA starts a new configuration process, and in the configuration process, the control unit reads the configuration code of the corresponding version from the storage unit according to the first address received by the version switching communication interface of the previous control unit and transmits the configuration code to the FPGA.

So far, the introduction of a method for configuring multiple versions of an FPGA in the third embodiment of the present disclosure is completed.

According to the method and the device, the version switching module is added in the user circuit of the FPGA, so that various code matching versions of the FPGA can be updated on line, and the function of the FPGA can be updated in real time. In this way, the code in the FPGA can be switched from one version to another without power loss.

So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. Further, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by those of ordinary skill in the art.

Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.

The disclosure may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. Various component embodiments of the disclosure may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functionality of some or all of the components in the relevant apparatus according to embodiments of the present disclosure. The present disclosure may also be embodied as apparatus or device programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present disclosure may be stored on a computer-readable medium or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.

Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Also in the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that is, the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.

The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims

1. A system for multi-version configuration of an FPGA, the system comprising:

an FPGA multi-version configuration chip, the chip is a packaging body, comprising:

the storage unit is used for storing a configuration data file of the FPGA;

the control unit is connected with the storage unit and can perform reading, erasing and writing operations on the storage unit, the control unit can acquire data in the storage unit, modify the data content in the storage unit and control the storage unit, and the control unit comprises:

the version switching communication interface is used for receiving data, address and control information by the control unit to realize online switching of the matched data file, and after receiving the first address of the matched data version, the control unit reads the matched data of the corresponding version according to the specified address and completes FPGA configuration;

the FPGA configuration interface is used for realizing the configuration of the FPGA by the interaction of the control unit and the FPGA and comprises a working time sequence signal and a control signal interface; the version switching module is used for controlling the on-line switching of the code matching version of the FPGA, and changing the function of the FPGA in real time or switching the code matching version of the FPGA on line through the version switching module during the normal working period of the FPGA;

when the function of the FPGA needs to be updated, namely the code matching version of the FPGA needs to be updated, the version switching module switches the communication interface through the version of the control unit in the FPGA multi-version configuration chip, transmits the first address of the expected target version in the storage unit to the control unit, and then resets the configuration logic of the FPGA through a PROG _ B signal; after the reset signal of the PROG _ B is cancelled, the control unit reads the configuration code of the corresponding version from the storage unit according to the first address received by the version switching communication interface of the previous control unit and transmits the configuration code to the FPGA;

the version switching module is arranged in the FPGA or a third-party controller outside the FPGA chip; under the condition of adopting a third-party controller, a superior controller is arranged for judging when the FPGA needs to update the version and informing the third-party controller to switch the version at the correct time, and the superior controller is connected to the FPGA and the third-party version switching module.

2. The system of claim 1, wherein the timing of switching the code matching versions of the FPGA is determined by the self user logic inside the FPGA or by another upper computer; when the upper computer considers that the code matching version of the FPGA needs to be switched, a version switching instruction and the first address of the new version in the storage unit are sent to the FPGA through the instruction link, and after the FPGA receives the instruction and the address, the corresponding version switching operation is completed through the version switching module.

3. A method of multi-version configuration of an FPGA, employing the system of multi-version configuration of an FPGA of any one of claims 1-2, comprising:

4. The method according to claim 3, wherein the step S3 includes:

5. The method of claim 4, wherein the predetermined state is a high level or a specific sequence of levels that last for more than a predetermined time.