CN107704285A - Field programmable gate array multi version configuration chip, system and method - Google Patents
Field programmable gate array multi version configuration chip, system and method Download PDFInfo
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- CN107704285A CN107704285A CN201710889479.2A CN201710889479A CN107704285A CN 107704285 A CN107704285 A CN 107704285A CN 201710889479 A CN201710889479 A CN 201710889479A CN 107704285 A CN107704285 A CN 107704285A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44536—Selecting among different versions
Abstract
Present disclose provides a kind of FPGA multi versions to configure chip, and the chip is a packaging body, including：At least one memory cell, match somebody with somebody code data file for store FPGA；Control unit, it is connected with memory cell, memory cell can be read out, wiped, write operation, including：Version switches communication interface, data, address and control information are received for control unit, realization switch online with code data file, after described control unit receives the first address with code version, according to specified address, read respective version with code data and complete FPGA configure；FPGA configures interface, for interacting for control unit and FPGA, completes FPGA Configuration Online function.The disclosure is FPGA version configuration provides more more options, and can carry out version switching in the case of system not power down.
Description
Technical field
This disclosure relates to PLD field of configuration, more particularly to a kind of field programmable gate array (Field
Programmable Gate Array, abbreviation FPGA) multi version configuration chip, system and method.
Background technology
FPGA (Field Programmable Gate Array, field programmable gate array) is in contemporary electronic systems
Very conventional generic logic device, its function can be by user's customized, and in actual applications, user can pass through replacing
Different configuration bit streams makes the FPGA realize a variety of functions.Due to its excellent flexibility and good versatility,
FPGA is obtaining more and more extensive application in various electronic systems.
In current mainstream applications, most commonly SRAM type FPGA, it is stored in inside fpga chip with code
In SRAM memory.SRAM is volatile memory, and then configuration information is all to lose after FPGA power down, therefore in practical application
In, FPGA usually (also referred to as " configuration chip ") is connected with corresponding configuration memory chip, and the two is used cooperatively.Upper electricity every time
Afterwards, FPGA is required for reading configuration information from configuration chip, to complete the initialization of itself.
Configuration chip, which is used to provide to FPGA after the power-up, matches somebody with somebody code data, in current mainstream applications, a configuration core
Piece can only store an ASCII stream file ASCII, and at this moment FPGA is obtained after upper electricity identical with code every time, and the function that FPGA is performed is
It is changeless.And storing multiple ASCII stream file ASCIIs needs to carry out cutting in units of fixed byte, each version can be with code
One or more 8Mbit data block is taken, causes waste of storage space, and during FPGA normal works, can not be changed again
With code, it is necessary to which system power failure could switch.
Disclosure
(1) technical problems to be solved
It is mentioned above at least partly to solve present disclose provides a kind of FPGA multi versions configuration chip, system and method
The technical problem gone out.
(2) technical scheme
According to an aspect of this disclosure, there is provided a kind of FPGA multi versions configure chip, and the chip is an encapsulation
Body, including：At least one memory cell, match somebody with somebody code data file for store FPGA；Control unit, it is connected with memory cell
Connecing, memory cell can be read out, wiped, write operation, described control unit can obtain the data in memory cell,
And the data content in memory cell is changed, and memory cell is controlled, described control unit includes：Version switching is logical
Believe interface, for transmitting data, address, control information between control unit and the external world, realization is cut online with code data file
Change, wherein, the first address with code version currently selected can be transferred to control unit by the external world, and control unit can be according to specified
Address, read respective version with code data and complete FPGA configuration；FPGA configures interface, for control unit and FPGA
FPGA configuration, including work schedule signal and control signal interface are realized in interaction.
In the disclosure some embodiments, described FPGA multi versions configuration chip includes three memory cell, by right
Data in three memory cell carry out triplication redundancy processing, by voting circuit to the data from three memory cell
Voted, it is described vote circuit input be respectively three memory cell output.
In the disclosure some embodiments, the version switching communication interface of described control unit is SPI communication interface, UART
Serial ports or IIC communication interfaces.
According to another aspect of the disclosure, there is provided a kind of system of FPGA multi versions configuration, using such as claim
FPGA multi versions configuration chip any one of 1-3, system also include：Version handover module, for controlling online switching
FPGA's matches somebody with somebody code version, by the version handover module, during FPGA normal works, can change FPGA work(in real time
Or can switch FPGA online matches somebody with somebody code version.
In the disclosure some embodiments, when needing to update FPGA function, that is, need to update FPGA matches somebody with somebody code version
When, the version that the version handover module configures control unit in chip by FPGA multi versions switches communication interface, it would be desirable to
Target version first address in the memory unit be transferred to control unit, then FPGA configuration is patrolled by PROG_B signals
Collect and reset；After PROG_B reset signal revocation, control unit can switch communication interface according to the version of control unit before
What the first address received read respective version from memory cell matches somebody with somebody code, and is transmitted to FPGA.
In the disclosure some embodiments, the version handover module is arranged on the third party in FPGA or outside FPGA pieces
Controller；In the case of using third party's controller, a higher controller is set to be used to judge when FPGA needs more new edition
This simultaneously carries out version switching in correct time announcement third party controller, and the higher controller is connected to FPGA and the 3rd
Square version handover module.
In the disclosure some embodiments, FPGA carry out the opportunity with the switching of code version can by inside FPGA itself
User logic is determined or determined by other host computer；, can when host computer is thought to need to switch when matching somebody with somebody code version of FPGA
To send the first address of version switching command and redaction in the memory unit to FPGA by command link, FPGA is being received
To after instruction and address, corresponding version handover operation is completed by version handover module.
According to another aspect of the disclosure, there is provided a kind of method of FPGA multi versions configuration, including：
Step S1, FPGA multi version configure electricity on chip and FPGA to be configured, and FPGA carries out initial configuration, on FPGA
Code match somebody with somebody in acquiescence loading lowest address space when electric, i.e. the 1st version match somebody with somebody code match somebody with somebody code；
Step S2, FPGA enter normal mode of operation, in FPGA normal mode of operation, if desired update FPGA work(
Can, that is, need renewal FPGA's to match somebody with somebody code version, then go to step S3；If FPGA function need not be updated, continue to return just
Normal mode operation；
Step S3, the version switching communication that version handover module configures control unit in chip by FPGA multi versions connect
Mouthful, it would be desirable to target version first address in the memory unit be transferred to control unit in FPGA multi versions configuration chip；
Step S4, new round FPGA configurations are restarted by reset signal, configuration terminates rear return to step S2, and FPGA enters just
Normal mode of operation.
In the disclosure some embodiments, in the step S3, including：
Chip selection signal CS# is set to effectively by sub-step S31, version handover module first, afterwards turns over clock signal SCLK
With outputting data signals SO, it would be desirable to target version first address in the memory unit be transferred to FPGA multi versions configuration chip
In control unit；
Sub-step S32, control unit are successfully received after the first address of target version, using SO be set to predetermined state as
Shake hands response；
Sub-step S33, version handover module detect the outputting data signals SO of control unit transmission on SI signal ends
It is configured to predetermined state, then it is assumed that control unit is successfully received the first address of target version, and handshake procedure has been completed；
The PROG_B for connecting FPGA reseting pins is set to one section of low level and holding by sub-step S34, version handover module
Time, by FPGA itself configuration logic reset；
Sub-step S35, after PROG_B is released as high level by version handover module again, FPGA, which departs from, resets shape
State and since memory cell new round loading operation, the target of loading be with code before by version switching communication
Target version specified by interface matches somebody with somebody code.
In the disclosure some embodiments, the predetermined state can be high level or specific more than predetermined hold-time
Sequence of levels.
(3) beneficial effect
It can be seen from the above technical proposal that the disclosure FPGA multi versions configuration chip, system and method at least have with
One of lower beneficial effect：
(1) due to can be accommodated in memory cell it is a variety of match somebody with somebody code version, and the version quantity with code is unrestricted, therefore
Can store in the memory unit it is any number of match somebody with somebody code version, be FPGA version configuration provides more more options, and can be
Version switching is carried out in the case of system not power down；
(2) due in memory cell initial address of each version with code it is unrestricted, so as to which each version is storing with code
Can be with continuous arrangement, the problem of in the absence of waste of storage space in unit；
(3) memory cell can select the memory using 128Mbit, 256Mbit or more Large Copacity, can not enter
Row multi-disc can be applied to large-scale F PGA configuration in the case of cascading；
(4) among by the way that control unit, memory cell are packaged in into 1 packaging body, its solid appearance form is 1 core
Piece, this can reduce the number of chips in FPGA system, and then reduce system weight, improve system reliability.
Brief description of the drawings
Fig. 1 is the structural representation that embodiment of the present disclosure FPGA multi versions configure chip.
Fig. 2 is the structural representation that there is the embodiment of the present disclosure FPGA multi versions of three memory cell to configure chip.
Fig. 3 is to be voted in the control unit for the FPGA multi versions configuration chip that the embodiment of the present disclosure has three memory cell
The structural representation of voting circuit.
Fig. 4 is the structural representation of the system of embodiment of the present disclosure FPGA multi versions configuration.
Fig. 5 is a kind of work schedule schematic diagram of embodiment of the present disclosure version handover module.
Fig. 6 is the embodiment of the present disclosure by structural representation of third party's controller as version handover module.
Fig. 7 is that the embodiment of the present disclosure determines that FPGA carries out the structural representation on the opportunity with the switching of code version by host computer instruction
Figure.
Fig. 8 is the flow chart of the method for embodiment of the present disclosure FPGA multi versions configuration.
Embodiment
Present disclose provides a kind of field programmable gate array multi version configuration chip, system and method.To make the disclosure
Purpose, technical scheme and advantage be more clearly understood, below in conjunction with specific embodiment, and referring to the drawings, one is entered to the disclosure
Step describes in detail.
The some embodiments of the disclosure will be done with reference to appended accompanying drawing in rear and more comprehensively describe to property, some of but not complete
The embodiment in portion will be illustrated.In fact, the various embodiments of the disclosure can be realized in many different forms, and should not be construed
To be limited to this several illustrated embodiment；Relatively, there is provided these embodiments cause the disclosure to meet applicable legal requirement.
In first exemplary embodiment of the disclosure, there is provided a kind of FPGA multi versions configure chip.Fig. 1 is this public affairs
Open the structural representation of first embodiment FPGA multi versions configuration chip.As shown in figure 1, disclosure FPGA multi versions configure core
Piece is a packaging body, including at least one memory cell, control unit.
The each part for configuring chip to the present embodiment FPGA multi versions individually below is described in detail.
At least one memory cell, is connected and the control of controlled unit with control unit；Stored in memory cell
It is that FPGA matches somebody with somebody code data file.When building system, the storage of capacity larger (such as 128Mbit, 256Mbit) can be selected
Type number, more match somebody with somebody code data space to provide.
In the memory unit, the FPGA that can store multiple versions matches somebody with somebody code, to the initial address with code of each version not
It is restricted.In this multiple version is with code file, there is one to be used as boot section with code, it is meant that, on every subsystem
After electricity, control unit acquiescence reads since the first address of boot section, FPGA is configured.Continue and take the whole of boot section
After data, then FPGA configurations are completed.In default situations, the initial configuration after upper electricity, control unit will not read memory cell
In other versions match somebody with somebody code file.
Control unit, the operation such as it can be read out, wipe, writing to memory cell, passing through these operations, control unit
The data in memory cell can be obtained, the data content in memory cell can also be changed.Control unit externally has JTAG
Interface, FPGA configurations interface, version switching communication interface.By jtag interface, control unit can be upper with the JTAG of outside
Machine is communicated, and obtains the control information and data of host computer, and itself working condition and data are returned to host computer.It is single to control
Member is used as bridge, and JTAG host computers can pass through the operations such as reading of the control unit realization to memory cell, erasing, write-in.Will
When disclosure FPGA multi versions configuration chip is used to configure FPGA, JTAG host computers can work FPGA required match somebody with somebody
Code write-in is into memory cell.
The version switching communication interface of control unit is used to transmit data, address, control between control unit and the external world
Information etc., wherein, the first address with code version currently selected can be transferred to control unit by the external world, and control unit can be according to
The address specified, read respective version with code data and complete FPGA configurations.All give tacit consent to loading when electric FPGA is each to draw
Lead the code of matching somebody with somebody in area, i.e., the 1st version in FPGA acquiescence loading lowest address space matches somebody with somebody code after upper electricity.Afterwards, it is normal in FPGA
During work, the replacing of version, the system not power down of the version stage of replacement can be realized by control unit.The external world can also pass through version
This switching communication interface, memory cell is accessed, the data in memory cell are read out, wipe, write via control unit
The operation such as enter.
Control planning between the FPGA configurations work schedule of interface of control unit, each signal, match somebody with somebody with FPGA products
The job specification for putting interface is mutually compatible.Interface is configured by FPGA, control unit can be engaged with FPGA, complete the upper of FPGA
Electric configuration feature.When performing this function, control unit to being read out with code data in memory cell, be organized into
The compatible data format of FPGA configuration interface specification phases, and interface is configured by FPGA and is transferred to FPGA.
In one embodiment, what is stored in memory cell is that Xilinx FPGA match somebody with somebody code data file, and FPGA configurations connect
Mouth is the configuration interface compatible with Xilinx FPGA phases, and in various embodiments, what is stored in memory cell is that other are any
The FPGA products of producer match somebody with somebody code data file, and FPGA configuration interfaces could alternatively be mutually simultaneous with the FPGA products of other any producers
The FPGA configuration interfaces of appearance.
In one embodiment, the version switching communication interface of control unit is SPI communication interface, in different embodiments
In, the version switching communication interface of control unit can be other any kind of communication interfaces such as UART serial ports, IIC.
In one embodiment, FPGA multi versions configuration chip includes a memory cell, in various embodiments, FPGA
Multi version configuration chip includes three memory cell, can by carrying out triplication redundancy processing to the data in three memory cell
To greatly improve the reliability for matching somebody with somebody code data.Fig. 2 is the FPGA multi versions configuration that the embodiment of the present disclosure has three memory cell
The structural representation of chip.As shown in Fig. 2 under this scene, circuit should be voted in a control unit to from 3
The data of individual memory cell are voted.Fig. 3 is that the FPGA multi versions that the embodiment of the present disclosure has three memory cell are matched somebody with somebody
Put the structural representation that circuit is voted in the control unit of chip.As shown in figure 3, voting the input of circuit is respectively
The output of 3 memory cell.The circuit of voting is a kind of processing of circuit mechanism, and its basic thought is exactly 3 to take 2, just in case
There is the input of 1 tunnel mistake occur, output remains to provide correct result.
The FPGA multi versions configuration chip uses wafer progress thin-film deposition, coating photoresistance, exposure, photoresistance to remove, carve
Prepared by the techniques such as erosion, doping and thermal annealing, its packing forms includes：The types such as QFP, QFN, PGA, BGA.
So far, first embodiment of the present disclosure FPGA multi versions configuration chip introduction finishes.
In second exemplary embodiment of the disclosure, there is provided a kind of system of FPGA multi versions configuration.Fig. 4 is this
The structural representation of the system of open embodiment FPGA multi versions configuration.As shown in figure 4, system includes JTAG host computers, FPGA
Multi version configures chip and version handover module, wherein：
JTAG host computers are used to FPGA configuring chip with code file download to FPGA multi versions, and the download with code file can
By USB port or other interfaces, via downloading wire, to expand one group of JTAG data wire, JTAG data wires are connected to FPGA
Multi version configures the jtag interface of chip, passes through this mode, you can establishes FPGA multi versions configuration chip and JTAG host computers
Connection.In Fig. 4, JTAG host computers are by JTAG link, the operation such as can be read out, wipe, writing to memory cell,
Can being rewritten and being updated with code data file to one or more arbitrary versions.FPGA developer carries out FPGA products
During exploitation debugging, the target FPGA that can be easily rewritten by JTAG host computers in memory cell matches somebody with somebody code data.Work as FPGA
, can also be by JTAG host computers and more editions of FPGA after developer completes the data renewal in memory cell by JTAG host computers
Connection between the jtag interface of this configuration chip disconnects.In general, after user completes exploitation debugging, it is no longer necessary to make
With JTAG host computers come frequently changing the FPGA in memory cell matches somebody with somebody code, FPGA multi versions are at this moment only needed to configure chip
Complete the configuration to FPGA.
FPGA multi versions configuration chip is used to carry out multi version FPGA configurations.In Fig. 4, user is complete by JTAG host computers
Into after in memory cell with the renewal of code data, by system cut-off and re-power, then the control of FPGA multi versions configuration chip
Unit processed can read version corresponding to boot section in memory cell and match somebody with somebody code data, and configuring interface by FPGA transfers data to
FPGA, complete FPGA configuration.After FPGA completes power-up initializing configuration, i.e., into normal operating conditions.
Version handover module is used to control online switching FPGA's to match somebody with somebody code version.By the version handover module in Fig. 4,
During FPGA normal works, the function or online switching FPGA that can change FPGA in real time match somebody with somebody code version.When needing to update
During FPGA function, that is, need to update when matching somebody with somebody code version of FPGA, version handover module is configured in chip by FPGA multi versions
The version switching communication interface of control unit, it would be desirable to target version first address in the memory unit to be transferred to control single
Member, then by PROG_B signals by FPGA configuration logic reset.After PROG_B reset signal revocation, FPGA will
Start new round configuration process, in the configuration process of this wheel, control unit can switch according to the version of control unit before
What the first address that communication interface receives read respective version from memory cell matches somebody with somebody code, and is transmitted to FPGA.Pass through this
Kind mode, can will be switched to another version with code in FPGA in the case of not power down from a version.
In the embodiment of the disclosure one, a kind of work schedule of Fig. 4 version handover module is as shown in figure 5, during the work
Sequence is as follows：
User logic in FPGA judges that version handover module is first by chip selection signal when thinking that code version is matched somebody with somebody in needs switching
CS# is set to effective (i.e. low level), afterwards turns over clock signal SCLK and outputting data signals SO, it would be desirable to target version exist
First address in memory cell is transferred to the control unit among FPGA multi versions configuration chip configuration memory.Control unit
It is successfully received after the first address of target version, SO is drawn high into a period of time as response of shaking hands.Version switching in FPGA
Module detects high level on signal SI, then it is assumed that handshake procedure has been completed.Then, version handover module puts PROG_B
For low level and kept for a period of time, by FPGA itself configuration logic reset.Treat PROG_B be released as again high level it
Afterwards, FPGA will new round loading operation, the target of loading be with code since being configured in chip memory FPGA multi versions
Code is matched somebody with somebody by the target version specified by SPI interface before.
In one embodiment, the version handover module is arranged in FPGA, in various embodiments, is arranged at FPGA
Internal version handover module, according to the particular demands of system, could alternatively be third party's controller outside FPGA pieces.Fig. 6 is
The embodiment of the present disclosure is by structural representation of third party's controller as version handover module.As shown in fig. 6, third party's control
Device processed can be CPLD, single-chip microcomputer or other FPGA etc..In the case of using third party's controller, a higher level need to be set to control
Device (not shown) is used to judge when FPGA needs more redaction and carry out version in correct time announcement third party controller
Switching.The higher controller is connected to FPGA and third party's version handover module.
In one embodiment, FPGA carry out the opportunity with the switching of code version can by the user logic of itself inside FPGA Lai
Determine, it is in various embodiments, described to be determined with code version switching time by other host computer.Fig. 7 is this
Open embodiment determines that FPGA carries out the structural representation on the opportunity with the switching of code version by host computer instruction.As shown in fig. 7,
FPGA is connected by command link with other host computer., can when host computer is thought to need to switch when matching somebody with somebody code version of FPGA
To send the first address of version switching command and redaction in the memory unit to FPGA by command link, FPGA is being received
To after instruction and address, corresponding version handover operation is completed by version handover module.
Certainly, above-mentioned hardware configuration can also include the functional modules such as power module (not shown), and these are in the art
Those skilled in the art it should be understood that those skilled in the art in the art can also add corresponding according to the needs of function
Functional module, therefore not to repeat here.
In order to reach the purpose of brief description, any technical characteristic narration for making same application in above-mentioned first embodiment
All and in this, without repeating identical narration.
So far, the system introduction of second embodiment of the present disclosure FPGA multi versions configuration finishes.
In the 3rd exemplary embodiment of the disclosure, there is provided a kind of method of FPGA multi versions configuration.Fig. 8 is this
The flow chart of the method for open embodiment FPGA multi versions configuration.As shown in figure 8, the side that multi version configuration is carried out to FPGA
Method, the workflow of its entire protocol are as follows：
Step S1, FPGA multi version configure electricity on chip and FPGA to be configured, and FPGA carries out initial configuration, on FPGA
That bootload area is given tacit consent to when electric matches somebody with somebody code；
Step S2, FPGA enter normal mode of operation, in FPGA normal mode of operation, if desired update FPGA work(
Can, that is, need renewal FPGA's to match somebody with somebody code version, then go to step S3；If FPGA function need not be updated, continue to return just
Normal mode operation；
Step S3, the version switching communication that version handover module configures control unit in chip by FPGA multi versions connect
Mouthful, it would be desirable to target version first address in the memory unit be transferred to control unit；
Further, in the step S3, including：
Sub-step S31, chip selection signal CS# is set to effective (i.e. low level) by version handover module first, when afterwards turning over
Clock signal SCLK and outputting data signals SO, it would be desirable to target version first address in the memory unit be transferred to more editions of FPGA
Control unit among this configuration chip configuration memory；
Sub-step S32, control unit are successfully received after the first address of target version, using SO be set to predetermined state as
Shake hands response；
Sub-step S33, version handover module detect the outputting data signals SO of control unit transmission on SI signal ends
It is configured to predetermined state, then it is assumed that control unit is successfully received the first address of target version, and handshake procedure has been completed；It is described
Predetermined state can be high level or specific sequence of levels more than predetermined hold-time；
PROG_B is set to low level and is kept for a period of time by sub-step S34 versions handover module, by matching somebody with somebody for FPGA itself
Put logic reset；
Sub-step S35 treats that PROG_B is released as after high level again, and FPGA will configure chip from FPGA multi versions
Start new round loading operation in memory cell, the target of loading be with code before by specified by version switching communication interface
Target version match somebody with somebody code.
Step S4, new round FPGA configurations are restarted by reset signal, configuration terminates rear return to step S2, and FPGA enters just
Normal mode of operation.
Further, in the step S4, version handover module is answered FPGA configuration logic by PROG_B reset signals
Position.After PROG_B reset signal revocation, FPGA will start new round configuration process, in the configuration process of this wheel,
Control unit can read phase according to the first address that the version switching communication interface of control unit before receives from memory cell
That answers version matches somebody with somebody code, and is transmitted to FPGA.
So far, a kind of method introduction of FPGA multi versions configuration of the third embodiment of the present disclosure finishes.
The disclosure realizes online updating FPGA's by increasing a version handover module in FPGA subscriber's line circuit
It is a variety of to match somebody with somebody code version, so as to real-time update FPGA function.In this way, can be in the case of not power down, by FPGA
In be switched to another version from a version with code.
So far, the embodiment of the present disclosure is described in detail combined accompanying drawing.It should be noted that in accompanying drawing or say
In bright book text, the implementation that does not illustrate or describe is form known to a person of ordinary skill in the art in art, and
It is not described in detail.In addition, the above-mentioned definition to each element and method be not limited in mentioning in embodiment it is various specific
Structure, shape or mode, those of ordinary skill in the art simply can be changed or replaced to it.
Furthermore word " comprising " does not exclude the presence of element or step not listed in the claims.Before element
Word "a" or "an" does not exclude the presence of multiple such elements.
In addition, unless specifically described or the step of must sequentially occur, the order of above-mentioned steps, which has no, is limited to above institute
Row, and can change or rearrange according to required design.And above-described embodiment can based on design and reliability consideration, that
This mix and match uses using or with other embodiment mix and match, i.e., the technical characteristic in different embodiments can be with independent assortment
Form more embodiments.
The disclosure can be by means of including the hardware of some different elements and by means of properly programmed computer
Realize.The all parts embodiment of the disclosure can realize with hardware, or to be run on one or more processor
Software module is realized, or is realized with combinations thereof.It will be understood by those of skill in the art that can be in practice using micro-
Processor either digital signal processor (DSP) come realize in the relevant device according to the embodiment of the present disclosure some or it is complete
The some or all functions of portion's part.The disclosure be also implemented as a part for performing method as described herein or
Person whole equipment or program of device (for example, computer program and computer program product).Such disclosure realized
Program can store on a computer-readable medium, or can have the form of one or more signal.Such signal
It can download and obtain from internet website, either provide on carrier signal or provided in the form of any other.
Those skilled in the art, which are appreciated that, to be carried out adaptively to the module in the equipment in embodiment
Change and they are arranged in one or more equipment different from the embodiment.Can be the module or list in embodiment
Member or component be combined into a module or unit or component, and can be divided into addition multiple submodule or subelement or
Sub-component.In addition at least some in such feature and/or process or unit exclude each other, it can use and appoint
What combination is disclosed to all features disclosed in this specification (including adjoint claim, summary and accompanying drawing) and so
All processes or unit of any method or equipment are combined.Unless expressly stated otherwise, this specification is (including adjoint
Claim, summary and accompanying drawing) disclosed in each feature can by alternative features that identical, equivalent or similar purpose are provided Lai
Instead of.Also, in if the unit claim of equipment for drying is listed, several in these devices can be by same
Hardware branch embodies.
Similarly, it will be appreciated that in order to simplify the disclosure and help to understand one or more of each open aspect,
Above in the description to the exemplary embodiment of the disclosure, each feature of the disclosure is grouped together into single implementation sometimes
In example, figure or descriptions thereof.However, the method for the disclosure should be construed to reflect following intention：I.e. required guarantor
The disclosure of shield requires features more more than the feature being expressly recited in each claim.It is more precisely, such as following
Claims reflect as, open aspect is all features less than single embodiment disclosed above.Therefore,
Thus the claims for following embodiment are expressly incorporated in the embodiment, wherein each claim is in itself
Separate embodiments all as the disclosure.
Particular embodiments described above, the purpose, technical scheme and beneficial effect of the disclosure are carried out further in detail
Describe in detail bright, should be understood that the specific embodiment that the foregoing is only the disclosure, be not limited to the disclosure, it is all
Within the spirit and principle of the disclosure, any modification, equivalent substitution and improvements done etc., the guarantor of the disclosure should be included in
Within the scope of shield.
Claims (10)
1. a kind of FPGA multi versions configure chip, the chip is a packaging body, including：
At least one memory cell, match somebody with somebody code data file for store FPGA；
Control unit, it is connected with memory cell, memory cell can be read out, wiped, write operation, the control is single
Member can obtain the data in memory cell, change the data content in memory cell, and memory cell is controlled, described
Control unit includes：
Version switches communication interface, and data, address and control information are received for control unit, realizes online with code data file
Switching, after described control unit receives the first address with code version, according to specified address, read respective version and match somebody with somebody yardage
According to and complete FPGA configuration；
FPGA configures interface, and FPGA configuration, including work schedule signal and control are realized for interacting for control unit and FPGA
Signaling interface processed.
2. FPGA multi versions according to claim 1 configure chip, including three memory cell, by single to three storages
Data in member carry out triplication redundancy processing, and ballot table is carried out to the data from three memory cell by voting circuit
Certainly, it is described vote circuit input be respectively three memory cell output.
3. FPGA multi versions according to claim 1 configure chip, the version switching communication interface of described control unit is
SPI communication interface, UART serial ports or IIC communication interfaces.
4. a kind of system of FPGA multi versions configuration, is configured using the FPGA multi versions as any one of claim 1-3
Chip, system also include：
Version handover module, for controlling online switching FPGA's to match somebody with somebody code version, by the version handover module, in FPGA just
Often during work, the function or online switching FPGA that can change FPGA in real time match somebody with somebody code version.
5. system according to claim 4, when needing to update FPGA function, that is, need renewal FPGA's to match somebody with somebody code version
When, the version that the version handover module configures control unit in chip by FPGA multi versions switches communication interface, it would be desirable to
Target version first address in the memory unit be transferred to control unit, then FPGA configuration is patrolled by PROG_B signals
Collect and reset；After PROG_B reset signal revocation, control unit can switch communication interface according to the version of control unit before
What the first address received read respective version from memory cell matches somebody with somebody code, and is transmitted to FPGA.
6. system according to claim 5, the version handover module is arranged on the third party in FPGA or outside FPGA pieces
Controller；In the case of using third party's controller, a higher controller is set to be used to judge when FPGA needs more new edition
This simultaneously carries out version switching in correct time announcement third party controller, and the higher controller is connected to FPGA and the 3rd
Square version handover module.
7. system according to claim 6, FPGA carries out the opportunity with the switching of code version can be by FPGA inside itself
User logic is determined or determined by other host computer；, can when host computer is thought to need to switch when matching somebody with somebody code version of FPGA
To send the first address of version switching command and redaction in the memory unit to FPGA by command link, FPGA is being received
To after instruction and address, corresponding version handover operation is completed by version handover module.
8. a kind of method of FPGA multi versions configuration, is configured using the FPGA multi versions as any one of claim 4-7
Chip, including：
Step S1, FPGA multi version configure the upper electricity of chip and FPGA to be configured, FPGA progress initial configurations, when electric on FPGA
Code is matched somebody with somebody in acquiescence loading lowest address space, i.e. the 1st version matches somebody with somebody code；
Step S2, FPGA enter normal mode of operation, in FPGA normal mode of operation, if desired update FPGA function, i.e.,
Need renewal FPGA's to match somebody with somebody code version, then go to step S3；If FPGA function need not be updated, continue to return in normal mode
Operation；
Step S3, the version that version handover module configures control unit in chip by FPGA multi versions switch communication interface, will
The first address of desired target version in the memory unit is transferred to the control unit in FPGA multi versions configuration chip；
Step S4, new round FPGA configurations are restarted by reset signal, configuration terminates rear return to step S2, and FPGA enters normal work
Operation mode.
9. according to the method for claim 8, in the step S3, including：
Chip selection signal CS# is set to effectively by sub-step S31, version handover module first, afterwards turns over clock signal SCLK and defeated
Go out data-signal SO, it would be desirable to target version first address in the memory unit be transferred in FPGA multi versions configuration chip
Control unit；
Sub-step S32, control unit are successfully received after the first address of target version, and SO is set into predetermined state as shaking hands
Response；
Sub-step S33, version handover module detect the outputting data signals SO configurations of control unit transmission on SI signal ends
For predetermined state, then it is assumed that control unit is successfully received the first address of target version, and handshake procedure has been completed；
The PROG_B for connecting FPGA reseting pins is set to low level and kept for a period of time by sub-step S34, version handover module,
By FPGA itself configuration logic reset；
Sub-step S35, after PROG_B is released to high level by version handover module again, FPGA departs from reset state and from depositing
Start new round loading operation in storage unit, the target of loading by the version switches communication interface meaning before being with code
Fixed target version matches somebody with somebody code.
10. according to the method for claim 9, the predetermined state can be high level or spy more than predetermined hold-time
Fixed sequence of levels.
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