CN113157334B - FPGA multi-version program loading method - Google Patents
FPGA multi-version program loading method Download PDFInfo
- Publication number
- CN113157334B CN113157334B CN202110338013.XA CN202110338013A CN113157334B CN 113157334 B CN113157334 B CN 113157334B CN 202110338013 A CN202110338013 A CN 202110338013A CN 113157334 B CN113157334 B CN 113157334B
- Authority
- CN
- China
- Prior art keywords
- fpga
- version
- program
- flash
- loading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/70—Software maintenance or management
- G06F8/71—Version control; Configuration management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a method for loading a multi-version program of an FPGA (field programmable gate array), which has the advantages of low hardware cost, simple software implementation, strong fault-tolerant capability and high reliability loading efficiency. The invention is realized by the following technical scheme: an FPGA program loading control unit is formed by adopting FPGA + MSU + CPLD, the CPLD is divided into 2 storage spaces with the same size through a highest bit address, and BIN files are combined in a mode that the space utilization rate of a Flash block is as high as possible; the MSU module issues a program version loading instruction to the CPLD, injects version configuration information of the program to be loaded, starts a software reset command, enables the Flash to carry out function program version loading from a set WBSTAR address starting position, stores an FPGA basic version program in an online programming mode through a JTAG mode at a first address of a first block of each Flash, and realizes the solidification of other function version programs in an online updating mode.
Description
Technical Field
The invention relates to the field of airborne platforms, in particular to a method for realizing FPGA multi-version program loading by utilizing ICAP3 control.
Background
The field programmable gate array FPGA is a device that realizes various functions by a logic combination circuit. Because a large amount of logic resources and configurable I/O pins are integrated in the FPGA and a unique parallel processing architecture is added, the configuration and management of a plurality of external devices and the transmission of internal and external interface data can be easily realized. Due to the flexibility of programming and the diversity of functions of the FPGA program, the FPGA program has great limitation on the use scheduling and overall management of each program in a complex project, so that an operating system is required to be introduced for uniform management. The FPGA is programmed based on a Static Random Access Memory (SRAM), and program data of the FPGA stored on the SRAM is lost when the system is powered off. When the system is powered on, the FPGA needs to load a program to be run from the outside, and this process is called program loading. The FPGA chip has five loading modes, namely a JTAG mode, a serial slave mode, a serial master mode, a parallel slave mode and a parallel master mode. The JTAG mode is often used for loading a program integrated by a host computer to the FPGA when debugging, and the priority is higher than other modes. Other load modes depend on the setting of the load mode pins (M0, M1, M2) on the FPGA. When an external processor is used for loading programs for the FPGA, a serial slave mode, a parallel slave mode or even a JTAG mode can be adopted. Due to its volatility, the FPGA needs to be reloaded after each power-up. In many cases, the FPGA reads a program from an EPROM dedicated to the outside. This approach is slow and can only load fixed programs. FPGAs come in a variety of configuration/loading modes. Roughly classified into active and passive types. The active loading refers to controlling a configuration flow by the FPGA, and the passive loading refers to passively receiving configuration data only by the FPGA. The most common passive configuration mode is the JTAG download bit file. In this mode, the device actively initiating operation is a computer, the data path is JTAG, the FPGA passively receives data, and updates the FPGA configuration according to the required operation. Regardless of the configuration mode, the configuration data is stored in the CMOS latch in the FPGA, and the data is lost after power failure every time and is reconfigured after power up. With the update of FPGA products, the resources of Xilnx UltraScale series FPGA chips are improved by several times compared with the Kintex and Virtex7 series FPGA chips which are mainstream in recent years. So that several functions realized by a plurality of FPGA hardware modules can be put on one FPGA. With the rapid development of the FPGA technology, the number of logic resources integrated by the FPGA increases, and accordingly, the configuration files of the FPGA become larger. It is anticipated that as technology evolves, high-end FPGA configuration files will become larger in the future. The increase in configuration files directly leads to a large increase in FPGA loading time.
The ultra Scale series FPGA chip with strong functions is used as a mainstream configuration chip of the FPGA hardware board card, the functions completed by the FPGA chips are placed on the ultra Scale series FPGA chip, and the complexity of hardware board card design is not brought from the aspect of hardware design. However, the functions which can be realized only by a plurality of FPGA hardware boards are realized by adopting an UltraScale series FPGA chip, and compared with a single Kintex and Virtex7 series FPGA chip, the number of the needed stored FPGA program versions is much larger.
With the progress of the semiconductor technology, the capacity of the FPGA chip is larger and larger, and the capacity requirement for externally configured Flash is higher and higher; flash is used as a configuration chip for electrifying the FPGA, the electrifying configuration time of the FPGA is influenced by the size of loaded data of the Flash, the FPGA chip with large capacity means that more time is needed to finish loading, the traditional serial loading mode cannot meet the rigorous requirement of a system on the loading time, and the BPI (Byte-wide Peripheral Interface) Flash adopts a parallel (8bit and 16bit) mode to provide the electrifying loaded data for the FPGA, so that the loading time of the FPGA is greatly shortened, and the Flash is increasingly adopted in engineering. In many practical projects, because of different application environments, the FPGA is required to realize different functions in different environments, and at this time, the FPGA chip is required to dynamically update and load the content in the Flash and complete the reloading of the configuration data of the FPGA chip, which is the reconfigurable capability of the FPGA. The main BPI Flash memory space is generally between 64MByte and 256MByte at present. A single BPI Flash chip is difficult to meet the requirement of storing multiple program versions of an UltraScale series FPGA chip. For example, in the original design, 3 FPGA hardware boards each include one FPGA chip, each FPGA chip needs one BPI Flash chip, and each FPGA chip is composed of 3 program versions. Now, one UltraScale series FPGA chip is used for realizing the functions of the 3 FPGA chips and corresponding programsThe number of versions can reach up to 27. At present, FPGA storage space dividing method based on BPI Flash divides Flash into 2, 4, 8 and other equal 2 by controlling high-order address of BPI Flash n And (4) portions are obtained. The division of the versions must meet the precondition that the maximum FPGA version file is stored, the BIN file size of a single UltraScale FPGA program is generally 6-46 MByte, and if Flash with the size of 256MByte is selected, the single Flash can be divided into 4 storage spaces. To store 27 program versions requires 7 Flash of 256MByte size. The BPI Flash used for storing the Xilinx FPGA program is in an MCS or BIN file format when being programmed through Impact. And the MCS or BIN file is very large, the programming is very slow, and the time can reach dozens of minutes.
Although the hardware board card can be reduced from 3 blocks to 1 block by selecting the large-capacity UltraScale series FPGA chip. However, 7 BPI Flash chips are required to be placed on 1 hardware board card, so that the cost of the hardware board card is greatly increased on one hand; on the other hand, the wiring complexity of the PCB of the hardware board card is greatly improved and is difficult to realize. With the increase of the complexity of a communication system, the FPGA configuration file is larger and larger, the loading time is longer and longer, and the starting time of the system is seriously influenced.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides the FPGA multi-version program loading method which is low in hardware cost, simple in software implementation, strong in fault-tolerant capability, high in reliability loading efficiency and high in FPGA program version storage flexibility, so that the waste of Flash storage space in practical application is reduced, and the FPGA hardware board card cost is reduced.
The above object of the present invention can be achieved by the following measures, a method for loading an FPGA with multiple versions on line, characterized in that: an MSU module is connected with a Field Programmable Gate Array (FPGA) and a Complex Programmable Logic Device (CPLD) to form an FPGA program loading control unit, two BPI Flash chips with the same size are selected as configuration chips of an UltraScale series FPGA by an external memory, each Flash is divided into a space with the size of 8MByte, and an FPGA basic version program with the capability of updating the Flash and an internal access configuration interface ICAP3 software guide online is stored; the CPLD selects a plurality of flashes and internal blocks of the flashes, divides the Flash and the internal blocks of the flashes into 2 storage spaces with the same size through a highest bit address, sorts all the BIN files of the FPGA version programs to be stored according to the size, and combines the BIN files in a mode that the space utilization rate of the Flash blocks is as high as possible; two Flash chips are selected through chip selection CE to realize continuous storage of more than 4 program versions, and the initial address of the latter version starts with a new Flash sector initial address; loading different program versions in a single Flash block is realized by adopting an UltraScale series FPGA Internal access configuration interface ICAP3(Internal configuration access port); the MSU module issues a program version loading instruction to the CPLD, and the CPLD loads the FPGA basic version program; the MSU injects Program version configuration information to be loaded into the FPGA, a warm start address WBSTAR (warm boot start address) is set through an ICAP3 control unit, then software reset IPROG (Internal Program _ B) command is started, Flash carries out function Program version loading from the set WBSTAR address starting position, at the first address of the first block of each Flash, FPGA basic version programs are stored and written in an online mode through a JTAG mode, and solidification of other function version programs is realized in an online updating mode of the FPGA basic version programs.
Compared with the prior art, the method has the beneficial effects that:
the hardware cost is reduced. The invention adopts an MSU module to connect a field programmable gate array FPGA and a complex programmable logic device CPLD to form an FPGA program loading control unit, an external memory selects two BPI Flash chips with the same size as a configuration chip of an UltraScale series FPGA, each Flash divides a space with the size of 8MByte, and stores an FPGA basic version program with the capability of updating the Flash and an internal access configuration interface ICAP3 software guide online. The large-capacity UltraScale series FPGA chip is selected as the main configuration chip of the FPGA module, the functions completed by a plurality of FPGA hardware board cards in the original design are placed in one large-capacity FPGA hardware board card, the FPGA function version program is dynamically loaded in an ICAP3 software loading guide mode, the Flash storage space is maximally utilized, the utilization rate of the Flash storage space is effectively improved, the Flash quantity required by the FPGA multi-version program is reduced, and the cost of a hardware system is obviously reduced.
And the software is simple to implement. The invention adopts CPLD to select a plurality of flashes and internal blocks of the flashes, divides the internal blocks into 2 storage spaces with the size through the highest bit address, sorts all FPGA version program BIN files to be stored according to the size, combines the BIN files in a mode that the space utilization rate of the Flash blocks is as high as possible, and effectively improves the storage flexibility of the FPGA version program; by the on-line issuing of the program version loading instruction by the MSU, the software program version loading instruction input by the external MSU can be received and the FPGA software program version required by the loading is guided only by dividing a space with the size of 8MByte in Flash for storing the FPGA basic version program with the ICAP3 software guiding capability. The method for realizing the loading of the FPGA multi-version program by means of the CPLD and MSU units of the original programmable logic device in the system does not need to additionally increase a control unit, is easy to realize software and is simple to operate.
The fault-tolerant capability is strong. The invention adopts two Flash chips, selects by chip selection CE, realizes the continuous storage of more than 4 program versions, and the initial address of the latter version starts with a new Flash sector initial address; the loading of different program versions in a single Flash block is realized by adopting an UltraScale series FPGA internal configuration access interface ICAP3, the management of a general FPGA multi-version configuration program file is realized, and corresponding function program versions can be loaded according to the execution of different system task functions. According to practical engineering verification, compared with the traditional method for loading the FPGA configuration file, the technology can obviously improve the loading speed of the FPGA configuration file and enhance the universality and flexibility of the FPGA board card in the use of the system. The MSU module issues a program version loading instruction to the CPLD and loads an FPGA basic version program; and injecting the configuration information of the program version to be loaded into the FPGA, setting a warm start address WBSTAR through an ICAP3 control unit, and then resetting an IPROG command by starting software to enable Flash to load the program version from the set WBSTAR address. The Xilinx official part is used for providing an ICAP3 interface, and a program with the loading and guiding capacity of the ICAP3 software is independently used as a basic version program, so that the occupied internal logic resources of an FPGA (field programmable gate array) are less, and the time sequence convergence is easier. Meanwhile, as Flash multi-version program storage is realized, the basic version program also has the capability of realizing Flash online updating. When an online updating instruction issued by an external MSU is received, the illegal updating instruction is filtered by adding an instruction detection measure in the basic version program, so that the possibility that the basic version program with online updating capability is damaged due to misoperation or failure of online updating of the program is effectively avoided, and the defect that the Flash online updating operation cannot be completed again is overcome.
The reliability loading efficiency is high. The invention writes configuration information into an ICAP3 control unit by issuing version configuration information to be loaded outside an MSU, sets a warm start address WBSTAR, and then starts a software reset IPROG command to enable Flash to load program versions from the set WBSTAR address start. And (3) programming an FPGA basic version program with an ICAP3 loading bootstrap program on line in the head address of the first block of the Flash in a JTAG boundary scanning mode, and realizing the solidification of other version programs in an on-line updating mode of the FPGA basic version program. Through verification, the method can improve the loading efficiency of the FPGA, save GPIO pins of the CPU and the FPGA, reduce the starting time of the system, improve the reliability and is very suitable for modern complex communication systems.
Drawings
The method is further described with reference to the figures and the detailed description.
FIG. 1 is a schematic diagram of a multi-version FPGA program loading method according to the present invention;
FIG. 2 is a flow diagram of the CPLD loading process of FIG. 1;
FIG. 3 is a flowchart of the FPGA loading process of FIG. 1;
fig. 4 is a flowchart of reporting a loading result by the CPLD in fig. 1.
Detailed Description
See fig. 1. According to the invention, an MSU module is adopted to connect a Field Programmable Gate Array (FPGA) and a Complex Programmable Logic Device (CPLD) to form an FPGA program loading control unit, two BPI Flash chips with the same size are selected as configuration chips of an UltraScale series FPGA by an external memory, each Flash is divided into a space with the size of 8MByte, and an FPGA basic version program with the guiding capability of updating the Flash and an internal access configuration interface ICAP3 software on line is stored; the CPLD selects a plurality of flashes and internal blocks of the flashes, divides the Flash into 2 storage spaces with the same size through a highest bit address, sorts all FPGA version program BIN files to be stored according to the size, and combines the BIN files in a mode that the space utilization rate of the Flash blocks is as high as possible; two Flash chips are selected through chip selection CE to realize continuous storage of more than 4 program versions, and the initial address of the latter version starts with a new Flash sector initial address; loading different program versions in a single Flash block is realized by adopting an UltraScale series FPGA Internal access configuration interface ICAP3(Internal configuration access port); the MSU module issues a program version loading instruction to the CPLD, and the CPLD loads the FPGA basic version program; the MSU injects Program version configuration information to be loaded into the FPGA, a warm start address WBSTAR (warm boot start address) is set through an ICAP3 control unit, then software reset IPROG (Internal Program _ B) command is started, Flash carries out function Program version loading from the set WBSTAR address starting position, at the first address of the first block of each Flash, FPGA basic version programs are stored and written in an online mode through a JTAG mode, and solidification of other function version programs is realized in an online updating mode of the FPGA basic version programs. In an FPGA program loading control unit formed by FPGA + MSU + CPLD, an FPGA basic version, a function version 1_1 and a function version 1_2 … function version 1_ N are stored in Flash 1; the Flash2 stores an FPGA basic version, a function version 2_1 and a function version 2_2 … function version 2_ M.
In this embodiment, Flash with a size of 256MByte is used for explanation (the Flash capacity is not limited to the size of 256 MByte). Each Flash is divided into 2 storage spaces with the size of 128MByte by the highest-order address (the Flash with the size of 256MByte is divided into 2 storage spaces with the size of 128MByte because the Flash space with the size of 128MByte can be accessed by selecting an ICAP3 control port at the maximum in the following. The two Flash chips are selected by chip selection CE, and 4 storage spaces with the size of 128MByte can be realized. To implement storage of more than 4 program versions, one program version cannot be stored in a single 128MByte size storage space in a conventional design, but rather should be stored in a contiguous manner. Because of the mode of programming Flash on line by connecting a JTAG with a PC, local addresses in a single Flash block space cannot be accessed, and the method is only suitable for programming the software program version starting from the first address of the Flash block. To program the version of the software program except the first address of the Flash block, an online updating mode is required. The multiple program versions are stored continuously, and the initial address of the latter version must start with the initial address of a new Flash sector, so as to avoid the adhesion of the former and latter program versions in the same Flash sector. Once the blocking condition occurs, under the condition of online updating of the program version, after a sector erasing instruction is executed, partial content of the previous program version is erased, so that the integrity of the previous program version is damaged. The problem of storing multiple program versions in a single Flash block is solved in a Flash online updating + continuous storage mode. The method comprises the steps of writing program version configuration information to be loaded into an ICAP3 through an MSU module, setting a warm start address WBSTAR, executing a software reset IPROG start command, enabling Flash to load program versions from the set WBSTAR address, and realizing different program version loads in a single Flash block by adopting an UltraScale FPGA internal configuration access interface ICAP 3.
And at the initial address of the first 128MByte block of each Flash, programming an FPGA basic version program which has the loading and guiding capacity of ICAP3 software and the capacity of updating the Flash program online at the same time in a JTAG mode, and solidifying other version programs by adopting an online updating mode of the FPGA basic version program.
And after the hardware board card is powered on, the FPGA basic version program is started by default. And injecting version configuration information of a program to be loaded into the FPGA basic version program through an external MSU module, setting a warm start address WBSTAR through an ICAP3 control unit, and loading the program version started by the corresponding WBSTAR address in Flash into the FPGA for running in a software reset IPROG starting mode. The program size of a single FPGA basic version is within 8MByte, 0-8 MByte space stored in the first 128MByte of each Flash in the Flash in a JTAG online programming mode occupies 8MByte, and the rest is 120 MByte. Sequencing all FPGA version program BIN files to be stored according to sizes, and combining the BIN files in a mode that the space utilization rate of a Flash block is as high as possible. Therefore, in addition to the basic version program of the FPGA, the rest 2 120MByte Flash block spaces and 2 128MByte Flash block spaces are estimated according to 8MByte to 46MByte of the BIN file, and 22 to 62 FPGA function program version BIN files can be stored.
The FPGA comprises a data analysis unit and a loading return unit which are connected through a loading data frame Load _ packet and a loading data frame response Load _ response respectively. The data parsing unit is connected in sequence with the Swap conversion unit and the ICAP3 control unit through Load data Load _ data. The data analysis unit is used for confirming the validity of the type of the received Load _ packet frame of the loaded data frame, if the type of the data frame is invalid, a Load _ data _ error signal of the loaded data frame is output to the loading return unit, and the MSU is reported that the type of the loaded data frame Load _ packet frame is invalid; and if the data frame type is valid, outputting the analyzed Load data Load _ data to a Swap conversion unit, and outputting the converted ICAP3 control data Icap _ data to an ICAP3 control unit. And the ICAP3 control unit controls the dynamic loading of the corresponding function version program in the Flash block according to the hot start address load _ addr in the Icap _ data.
The CPLD comprises a Flash block selection unit, a Cmd response feedback unit and a function version loading feedback unit which are connected with a Cmd analysis unit. If the Cmd parsing unit parses that the Load instruction Load _ Cmd is invalid, the Cmd response returning unit reports that the Load instruction response Load _ Cmd _ response instruction has an error to the MSU. If the Load _ Cmd is valid, judging whether the current FPGA internal operation program is an FPGA basic version program, and if the current FPGA internal operation program is the FPGA basic version program, outputting a Flash chip selection Ce _ sel and a High-order address High _ addr corresponding to the functional version to be loaded to a Flash block selection unit by a Cmd analysis unit; the Flash block selection unit sets Flash1_ ce or Flash2_ ce and a Flash high address Flash _ high _ addr, reports a Load FPGA basic version instruction to the MSU through the Cmd response return unit, responds to Load _ Cmd _ response successfully, and sets an FPGA basic version Load success signal Load _ base _ done to be effective. And the Cmd responds to the return unit to start the function version loading result return unit to work, monitors whether the function version is loaded successfully or not, and reports the loading result to the MSU through a response Load _ func _ version _ response generated by the function version loading result return unit. If the current internal running program of the FPGA is not the basic version program of the FPGA, switching to the basic version program of the FPGA, and then setting a corresponding Flash high address Flash _ high _ addr.
See fig. 2. After the CPLD is electrified, the CPLD loading processing flow enters an initial state after the resetting is completed, the data input from the MSU is monitored, and the data input is sent to the Cmd analyzing unit. Confirming whether the Load instruction Load _ Cmd is valid, if the Load _ Cmd instruction is invalid, reporting that the MSU Load instruction Load _ Cmd is invalid through a Cmd response return unit, and returning to an initial state; if the Load _ cmd instruction is valid, judging whether the currently running FPGA program is stored in a Flash area where the functional version to be loaded is located, and if the currently running FPGA program is stored in the Flash area where the functional version to be loaded is located, judging whether the currently running FPGA program is a basic version program; if the currently running FPGA program is a basic version program, setting a Flash High-order address High _ addr to point to a Flash block space where the functional version is located through a Flash block selection unit, reporting successful loading of the MSU FPGA basic version program through a Cmd response return unit, and if the currently running FPGA program is not stored in a Flash area where the functional version to be loaded is located, setting the Flash High-order address High _ addr to point to the Flash block space where the basic version program is located after setting a Flash chip selection CE corresponding to the functional version to be loaded; and setting the FPGA reset signal PROG _ B to be effective, and setting the PROG _ B to be invalid after the FPGA initialization signal INIT is effective. If the FPGA starting signal DONE is effective within the set overtime, setting a Flash High-order address High _ addr to point to a Flash block space corresponding to the FPGA functional version program to be loaded, and reporting the successful loading of the MSU FPGA basic version program through a Cmd response return unit; within the set overtime, the FPGA starting signal DONE is invalid all the time, and the MSU FPGA basic version program loading failure is reported through the Cmd response feedback unit; the currently running FPGA program is stored in a Flash area where the functional version to be loaded is located, but the currently running FPGA program is not a basic version program, a Flash High-order address High _ addr is set to point to a Flash block space where the basic version program is located, an FPGA reset signal PROG _ B is set to be valid, and after an FPGA initialization signal INIT is valid, the PROG _ B is set to be invalid; if the FPGA starting signal DONE is effective within the set overtime, setting a Flash High-order address High _ addr to point to a Flash block space corresponding to the FPGA functional version program to be loaded, and reporting the successful loading of the MSU FPGA basic version program through a Cmd response return unit; if the FPGA starting signal DONE is invalid all the time within the set overtime, reporting MSU FPGA basic version program loading failure through a Cmd response feedback unit; and after receiving the Load instruction Load _ Cmd _ response successfully returned by the Cmd response return unit, the MSU sends a Load data frame Load _ packet to the FPGA.
See fig. 3. After the FPGA is powered on, the FPGA loading processing flow enters an initial state after the resetting is completed, data input from the MSU is monitored, the data input is sent to a data analysis unit, and frame type judgment is carried out on a received loading data frame Load _ packet. If the Load _ packet frame type is invalid, reporting a Load _ packet frame type error of a MSU loading data frame through a loading return unit; if the Load _ packet frame type is valid, the data analysis unit outputs the analyzed Load data Load _ data to the Swap conversion unit. The Swap conversion unit performs byte order conversion on the Load data Load _ data field according to the data format required by the ICAP3 interface until the data conversion of all the Load data Load _ data fields is completed, and outputs the converted data Icap _ data to the ICAP3 control unit to execute an ICAP instruction. After the IPROG _ B soft reset instruction is executed, the program in the FPGA is cleared, and the corresponding functional program version in the Flash is loaded into the FPGA for running.
Participate in fig. 4. After the CPLD is powered on, the CPLD reports a loading result flow to enter an initial state after resetting is completed, whether a Load _ base _ DONE signal which is outputted from the Cmd response feedback unit and successfully loads the basic version is effective or not is monitored, if yes, whether a rising edge of an FPGA starting signal DONE is generated or not is detected, and if the rising edge of the FPGA starting signal DONE is generated within a set overtime, a function version loading result feedback unit reports that the MSU function version is successfully loaded; if the Load _ base _ done signal is invalid, returning to the initial state; if the rising edge of the FPGA starting signal DONE is not generated all the time within the set overtime, reporting MSU FPGA function version program loading failure through a function version loading result returning unit.
The above embodiments are merely illustrative, and not restrictive, and any modifications, equivalents, improvements and the like that may occur to those skilled in the art without departing from the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (9)
1. A method for loading FPGA multi-version programs on line is characterized in that: an MSU module is connected with a Field Programmable Gate Array (FPGA) and a Complex Programmable Logic Device (CPLD) to form an FPGA program loading control unit, two BPI Flash chips with the same size are selected as configuration chips of an UltraScale series FPGA by an external memory, each Flash is divided into a space with the size of 8MByte, and an FPGA basic version program with the capability of updating the Flash and an internal access configuration interface ICAP3 software guide online is stored; the CPLD selects a plurality of flashes and internal blocks of the flashes, divides the Flash and the internal blocks of the flashes into 2 storage spaces with the same size through a highest bit address, sorts all the BIN files of the FPGA version programs to be stored according to the size, and combines the BIN files in a mode of high space utilization rate of the Flash blocks; two Flash chips are selected through chip selection CE to realize continuous storage of more than 4 program versions, and the initial address of the latter version starts with a new Flash sector initial address; loading different program versions in a single Flash block is realized by adopting an UltraScale series FPGA Internal access configuration interface (ICAP 3) (Internal configuration access port); the MSU module issues a program version loading instruction to the CPLD, and the CPLD loads the FPGA basic version program; the MSU injects Program version configuration information to be loaded into the FPGA, a warm start address WBSTAR (warm boot start address) is set through an ICAP3 control unit, then software reset IPROG (Internal Program _ B) command is started, Flash carries out function Program version loading from the set WBSTAR address starting position, at the first address of the first block of each Flash, FPGA basic version programs are stored and written in an online mode through a JTAG mode, and solidification of other function version programs is realized in an online updating mode of the FPGA basic version programs; after the CPLD is electrified, the CPLD loading processing flow enters an initial state after the resetting is completed, monitors the data input from the MSU and sends the data input to the Cmd analyzing unit; confirming whether the Load instruction Load _ Cmd is valid or not, if the Load _ Cmd instruction is invalid, reporting the MSU Load instruction Load _ Cmd invalidity through a Cmd response return unit, and returning to an initial state; if the Load _ cmd instruction is valid, judging whether the currently running FPGA program is stored in a Flash area where the functional version to be loaded is located, and if the currently running FPGA program is stored in the Flash area where the functional version to be loaded is located, judging whether the currently running FPGA program is a basic version program; if the currently running FPGA program is a basic version program, setting a Flash High-order address High _ addr to point to a Flash block space where the functional version is located through a Flash block selection unit, reporting successful loading of the MSU FPGA basic version program through a Cmd response return unit, and if the currently running FPGA program is not stored in a Flash area where the functional version to be loaded is located, setting the Flash High-order address High _ addr to point to the Flash block space where the basic version program is located after setting a Flash chip selection CE corresponding to the functional version to be loaded; setting the FPGA reset signal PROG _ B to be effective, and setting PROG _ B to be ineffective after the FPGA initialization signal INIT is effective; if the FPGA starting signal DONE is effective within the set overtime, setting a Flash High-order address High _ addr to point to a Flash block space corresponding to the FPGA functional version program to be loaded, and reporting the successful loading of the MSU FPGA basic version program through a Cmd response return unit; within the set overtime, the FPGA starting signal DONE is invalid all the time, and the MSU FPGA basic version program loading failure is reported through the Cmd response feedback unit; the currently running FPGA program is stored in a Flash area where the functional version to be loaded is located, but the currently running FPGA program is not a basic version program, and the MSU sends a Load data frame Load _ packet to the FPGA after receiving a Load instruction Load _ Cmd _ response successfully returned by the Cmd response return unit.
2. The method for loading the FPGA multi-version program on line according to claim 1, characterized in that: in an FPGA program loading control unit formed by FPGA + MSU + CPLD, an FPGA basic version, a function version 1_1 and a function version 1_2 … function version 1_ N are stored in Flash 1; the Flash2 stores an FPGA basic version, a function version 2_1 and a function version 2_2 … function version 2_ M; each Flash is divided into 2 128MByte storage spaces through the highest bit address, and two Flash chips are selected through chip selection CE to realize 4 128MByte storage spaces.
3. The method for loading the FPGA multi-version program online as recited in claim 1, wherein: in the multi-program version continuous storage, the initial address of the later version starts with a new Flash sector initial address, program version configuration information to be loaded is written into the ICAP3 through the MSU module, a warm start address WBSTAR is set, then a software reset IPROG start command is executed, Flash is enabled to load program versions from the initial position of the set WBSTAR address, and different program versions in a single Flash block are loaded by adopting an UltraScale FPGA internal configuration access interface ICAP 3.
4. The method for loading the FPGA multi-version program on line according to claim 1, characterized in that: after the hardware board card is powered on, the FPGA basic version program is started by default, then program version configuration information to be loaded is injected into the FPGA basic version program through an external MSU module, a warm start address WBSTAR is set through an ICAP3 control unit, and a program version started by a corresponding WBSTAR address in Flash is loaded into the FPGA to run in a software reset IPROG starting mode.
5. The method for loading the FPGA multi-version program on line according to claim 1, characterized in that: the program size of a basic version of a single FPGA is within 8MByte, 0-8 MByte space in first 128MByte of each Flash is stored in a JTAG online programming mode, 8MByte is occupied, and the rest 2 120MByte Flash block space and 2 128MByte Flash block space are estimated according to 8 MByte-46 MByte of a BIN file.
6. The method for loading the FPGA multi-version program online as recited in claim 1, wherein: the FPGA comprises a data analysis unit and a loading return unit which are connected through a Load data frame Load _ packet and a Load data frame response Load _ response respectively, the data analysis unit is sequentially connected with a Swap conversion unit and an ICAP3 control unit through a Load data Load _ data, the data analysis unit is used for confirming the validity of the type of the Load data frame Load _ packet received, if the type of the data frame is invalid, an error Load _ data _ error signal of the Load data frame is output to the loading return unit, and the MSU is reported that the type of the Load data frame Load _ packet is invalid; if the data frame type is valid, the analyzed Load data Load _ data is output to a Swap conversion unit, the converted ICAP3 control data Icap _ data is output to an ICAP3 control unit, and the CAP3 control unit controls the dynamic loading of a corresponding function version program in a Flash block according to a hot start address Load _ addr in the Icap _ data.
7. The method for loading the FPGA multi-version program online as recited in claim 1, wherein: the CPLD comprises a Flash block selection unit, a Cmd response feedback unit and a functional version loading feedback unit which are connected with the Cmd analysis unit, wherein the Cmd analysis unit analyzes that a loading instruction Load _ Cmd is invalid, and reports that the loading instruction response Load _ Cmd _ response instruction is wrong to the MSU through the Cmd response feedback unit; if the Load _ Cmd is valid, judging whether the current FPGA internal operation program is an FPGA basic version program, and if the current FPGA internal operation program is the FPGA basic version program, outputting a functional version to be loaded to a Flash block selection unit by a Cmd analysis unit corresponding to a Flash chip selection Ce _ sel and a High-order address High _ addr; the Flash block selection unit sets Flash1_ ce or Flash2_ ce and a Flash high address Flash _ high _ addr, reports a command for loading the FPGA basic version to the MSU through the Cmd response return unit, responds to Load _ Cmd _ response success, sets an FPGA basic version loading success signal Load _ base _ done to be effective, starts the function version loading result return unit to work through the Cmd response return unit, monitors whether the function version is loaded successfully or not, and reports the loading result to the MSU through a response Load _ func _ version _ response generated by the function version loading result return unit; if the current internal running program of the FPGA is not the basic version program of the FPGA, switching to the basic version program of the FPGA, and then setting a corresponding Flash high address Flash _ high _ addr.
8. The method for loading the FPGA multi-version program on line according to claim 1, characterized in that: after the FPGA is electrified, the FPGA loading processing flow enters an initial state after the resetting is completed, data input from the MSU is monitored, the data input is sent to a data analysis unit, and frame type judgment is carried out on a received loading data frame Load _ packet; if the Load _ packet frame type is invalid, reporting a Load _ packet frame type error of a MSU loading data frame through a loading return unit; if the Load _ packet frame type is valid, the data analysis unit outputs the analyzed Load data Load _ data to the Swap conversion unit; the Swap conversion unit performs byte order conversion on the Load data Load _ data field according to a data format required by an ICAP3 interface until the data conversion of all the Load data Load _ data fields is finished, and outputs the converted data Itap _ data to the ICAP3 control unit to execute an ICAP instruction; after the IPROG _ B soft reset instruction is executed, the program in the FPGA is cleared, and the corresponding functional program version in the Flash is loaded into the FPGA for running.
9. The method for loading the FPGA multi-version program online as recited in claim 1, wherein: after the PLD is powered on, the CPLD reports a loading result flow to enter an initial state after resetting is completed, whether a Load _ base _ DONE signal which is outputted from the Cmd response feedback unit and succeeds in loading the basic version is effective or not is monitored, if yes, whether a rising edge of an FPGA starting signal DONE is generated or not is detected, and if the rising edge of the FPGA starting signal DONE is generated within a set overtime, a function version loading result feedback unit reports that the MSU function version is successfully loaded; if the Load _ base _ done signal is invalid, returning to the initial state; if the rising edge of the FPGA starting signal DONE is not generated all the time within the set overtime, reporting MSU FPGA function version program loading failure through a function version loading result returning unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110338013.XA CN113157334B (en) | 2021-03-30 | 2021-03-30 | FPGA multi-version program loading method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110338013.XA CN113157334B (en) | 2021-03-30 | 2021-03-30 | FPGA multi-version program loading method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113157334A CN113157334A (en) | 2021-07-23 |
| CN113157334B true CN113157334B (en) | 2022-09-02 |
Family
ID=76885284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110338013.XA Active CN113157334B (en) | 2021-03-30 | 2021-03-30 | FPGA multi-version program loading method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113157334B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115202752B (en) * | 2022-06-27 | 2023-04-07 | 深圳市科楠科技开发有限公司 | Method and device for loading FPGA (field programmable Gate array) version |
| CN115167885B (en) * | 2022-08-03 | 2024-02-06 | 江苏新质信息科技有限公司 | Method and system for loading program after power-on of multi-FPGA system |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101206564A (en) * | 2006-12-20 | 2008-06-25 | 鸿富锦精密工业（深圳）有限公司 | Document version pipe control interface arrangement and method |
| CN204166522U (en) * | 2014-10-28 | 2015-02-18 | 南京长峰航天电子科技有限公司 | A kind of high-speed high capacity FLASH veneer memory circuit plate |
| CN107193567A (en) * | 2017-05-25 | 2017-09-22 | 湖北航天技术研究院总体设计所 | Missile-borne dsp software clean boot generation patterns and its realize system, system preparation method |
| CN107704285A (en) * | 2017-09-27 | 2018-02-16 | 中国科学院微电子研究所 | Field programmable gate array multi version configuration chip, system and method |
| CN107832078A (en) * | 2017-09-15 | 2018-03-23 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | FPGA program online updating circuits based on DSP |
| CN207264382U (en) * | 2017-09-27 | 2018-04-20 | 中国科学院微电子研究所 | The chip and system of field programmable gate array multi version configuration |
| CN107977217A (en) * | 2017-11-22 | 2018-05-01 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The method of on-line loaded XILINX-FPGA multi versions more new procedures |
| CN108052355A (en) * | 2017-11-22 | 2018-05-18 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The spaceborne in-orbit recombination method of load cell software |
| CN211264295U (en) * | 2020-03-30 | 2020-08-14 | 四川鸿创电子科技有限公司 | Multi-version program loading structure |
| CN111562932A (en) * | 2020-05-08 | 2020-08-21 | 北京计算机技术及应用研究所 | High-reliability embedded software upgrading method and system |
| CN112214345A (en) * | 2020-11-02 | 2021-01-12 | 西安电子工程研究所 | Multi-loading-based multi-FPGA software programming fault recovery method |
| CN112231005A (en) * | 2020-10-19 | 2021-01-15 | 天津津航计算技术研究所 | Method for managing FPGA (field programmable Gate array) version based on UBOOT (Universal boot on Board) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8176296B2 (en) * | 2000-10-26 | 2012-05-08 | Cypress Semiconductor Corporation | Programmable microcontroller architecture |
| US7391237B2 (en) * | 2005-04-29 | 2008-06-24 | O2 Micro International Limited | Robust and economic solution for FPGA bitfile upgrade |
-
2021
- 2021-03-30 CN CN202110338013.XA patent/CN113157334B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101206564A (en) * | 2006-12-20 | 2008-06-25 | 鸿富锦精密工业（深圳）有限公司 | Document version pipe control interface arrangement and method |
| CN204166522U (en) * | 2014-10-28 | 2015-02-18 | 南京长峰航天电子科技有限公司 | A kind of high-speed high capacity FLASH veneer memory circuit plate |
| CN107193567A (en) * | 2017-05-25 | 2017-09-22 | 湖北航天技术研究院总体设计所 | Missile-borne dsp software clean boot generation patterns and its realize system, system preparation method |
| CN107832078A (en) * | 2017-09-15 | 2018-03-23 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | FPGA program online updating circuits based on DSP |
| CN107704285A (en) * | 2017-09-27 | 2018-02-16 | 中国科学院微电子研究所 | Field programmable gate array multi version configuration chip, system and method |
| CN207264382U (en) * | 2017-09-27 | 2018-04-20 | 中国科学院微电子研究所 | The chip and system of field programmable gate array multi version configuration |
| CN107977217A (en) * | 2017-11-22 | 2018-05-01 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The method of on-line loaded XILINX-FPGA multi versions more new procedures |
| CN108052355A (en) * | 2017-11-22 | 2018-05-18 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The spaceborne in-orbit recombination method of load cell software |
| CN211264295U (en) * | 2020-03-30 | 2020-08-14 | 四川鸿创电子科技有限公司 | Multi-version program loading structure |
| CN111562932A (en) * | 2020-05-08 | 2020-08-21 | 北京计算机技术及应用研究所 | High-reliability embedded software upgrading method and system |
| CN112231005A (en) * | 2020-10-19 | 2021-01-15 | 天津津航计算技术研究所 | Method for managing FPGA (field programmable Gate array) version based on UBOOT (Universal boot on Board) |
| CN112214345A (en) * | 2020-11-02 | 2021-01-12 | 西安电子工程研究所 | Multi-loading-based multi-FPGA software programming fault recovery method |
Non-Patent Citations (4)
| Title |
|---|
| "Multi-diversity versus common cause failures：FPGA-based multi-version NPP I&C systems";Vyacheslav Kharchenko 等;《Proceedings of the 7th Conference NPIC&HMIT》;20101130;第1-12页 * |
| "一种基于Nand Flash多版本程序的FPGA智能加载方法";刘剑 等;《雷达与对抗》;20150915;第35卷(第3期);第68-70页 * |
| "基于Parallel NOR Flash的多FPGA配置方案";廖海黔;《数字技术与应用》;20170815(第8期);第66-67页 * |
| "基于RapidIO的FPGA远程更新系统设计与实现";朱道山;《雷达科学与技术》;20171015;第15卷(第5期);第543-547页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113157334A (en) | 2021-07-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107977217B (en) | Method for online loading XILINX-FPGA multi-version updating program | |
| CN113157334B (en) | FPGA multi-version program loading method | |
| US7131114B2 (en) | Debugger breakpoint management in a multicore DSP device having shared program memory | |
| CN105930186B (en) | The method for loading software of multi -CPU and software loading apparatus based on multi -CPU | |
| US6662314B1 (en) | Microcomputer including program for rewriting data in an internal flash memory | |
| US10552047B2 (en) | Memory system | |
| CN108121672A (en) | A kind of storage array control method and device based on Nand Flash memorizer multichannel | |
| CN107832078B (en) | FPGA program online updating circuit based on DSP | |
| CN107704285B (en) | Multi-version configuration chip, system and method for field programmable gate array | |
| CN112230955B (en) | Computer FPGA reconstruction system based on dual-core ARM SoC and operation method | |
| CN113434162B (en) | Method for remotely updating FPGA multi-version program on line | |
| CN107885517B (en) | Program loading circuit of embedded system processor | |
| CN111625286B (en) | External boot loading method and loading system for satellite-borne DSP (digital Signal processor) program | |
| CN112014726A (en) | DSP chip testing device and method | |
| US6675289B1 (en) | System and method for executing hybridized code on a dynamically configurable hardware environment | |
| US20060020764A1 (en) | Information processing apparatus including non-volatile memory device, non-volatile memory device and methods thereof | |
| CN111190855A (en) | FPGA multiple remote configuration system and method | |
| CN115309602B (en) | Debugging device of GPU, GPU and debugging system | |
| US20020144066A1 (en) | Status register architecture for flexible read-while-write device | |
| US7647485B2 (en) | Data processing system for debugging utilizing halts in a parallel device | |
| CN106649137B (en) | Nand Flash bad block management method and device and memory | |
| CN114489743A (en) | Program programming and loading operation method of on-chip programmable system | |
| CN100483349C (en) | Software loading method and its system | |
| CN111338700B (en) | Method and device for loading FPGA version and storage medium | |
| US6240377B1 (en) | Integrated circuit with embedded reprogrammable EEPROM and emulation method to facilitate debugging |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |