CN202615386U - Single board and data processing system - Google Patents
Single board and data processing system Download PDFInfo
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- CN202615386U CN202615386U CN 201220049960 CN201220049960U CN202615386U CN 202615386 U CN202615386 U CN 202615386U CN 201220049960 CN201220049960 CN 201220049960 CN 201220049960 U CN201220049960 U CN 201220049960U CN 202615386 U CN202615386 U CN 202615386U
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Abstract
The utility model discloses a single board and a data processing system. The single board and the data processing system comprise a serial port level conversion module, an erasable programmable logic device (EPLD) module, a processer module and a memory module, wherein the serial port level conversion module is used for converting serial port level, the EPLD module is used for receiving and sending serial port signals, parsing command, processing data, reading and writing the memory module, switching the working state of the single board and controlling links, the processor module is used for carrying out debugging of the single board, and the memory module is used for storing version data. The EPLD module is respectively connected with a state selection module, the serial port level conversion module, the processer module and the memory module. By means of the single board and the data processing system, the fact that two interface modes including serial ports and parallel ports are needed for single board debugging and FLASH downloading can be replaced, only a single serial port is needed to finish the single board debugging and the FLASH downloading, inconvenience caused by using the parallel ports is avoided, single board interface is simplified, and a novel downloading method is provided for a place where no parallel port environment exists at the same time.
Description
Technical field
The utility model relates to the communication apparatus technical field, relates in particular to a kind of veneer and data handling system.
Background technology
The software startup of embedded system is divided into BOOT ROM and application software part, and early stage BOOT ROM leaves in the independent BOOT chip, on the PLCC socket that is inserted in veneer after the burned content on the fever writes.Present BOOT ROM major part and application software are integrated on the FLASH together.The encapsulation of FLASH determined it to take off from veneer to carry out programming, and therefore present common practice is the parallel port through PC, and simulation LPC sequential etc. is carried out programming to FLASH, needs special parallel port to load cable and environment support.
On the other hand, the function of veneer, performance adjustment all are to accomplish with a serial ports in addition.So, in the process of debugging veneer, must prepare following equipment and environment simultaneously: (1) possesses the PC of parallel port; (2) cable and environment are downloaded in the parallel port; (3) AccessPort cable.
When the debugging veneer, connect serial ports and debug; Download the FLASH version and then need electricity under the veneer be connected the parallel port again, plug interface back and forth, uses numerous and diversely, increase and debug complexity.
The utility model content
The technical matters that the utility model will solve provides a kind of veneer and data handling system, can support debugging single board and load application version data simultaneously through serial ports.
For solving the problems of the technologies described above; A kind of veneer of the utility model; Comprise: but be used to change the serial ports level the serial ports level switch module, be used to carry out wiping editorial logic device (EPLD) module, be used to carry out the processor module of debugging single board and be used for storage version memory of data module of serial data transmitting-receiving, command analysis, data processing, memory module read-write, single-board operation state conversion and controlling links; Wherein, said EPLD module is connected with serial ports level switch module, processor module and memory module respectively.
Further; Said EPLD module comprises: be used to carry out serial communication the serial data transceiver module, be used for resolve command word and edition data; Sending command word to state switches and link control module; With edition data send to the FLASH bus interface module command analysis and data processing module, be used for edition data is loaded into the FLASH bus interface module of memory module and is used for the processor controls module and the link-attached state of serial data transceiver module switches and link control module; Wherein, Said state switches and link control module is connected with command analysis and data processing module with said serial data transceiver module respectively, and said command analysis and data processing module also are connected with the FLASH bus interface module with said serial data transceiver module respectively.
Further; Said serial data transceiver module and processor module all comprise serial data and send (TXD) end and serial data reception (RXD) end; The TXD end of said serial data transceiver module links to each other with the TXD end of serial ports; The RXD end of said serial data transceiver module links to each other with the RXD end of serial ports through said state switching and link control module, and the TXD end of said processor module all switches through said state with the RXD end and link control module links to each other with the RXD end with the TXD end of serial ports respectively.
Further, adopt parallel data communication between said serial data transceiver module and command analysis and the data processing module.
Further; Also comprise the state selection module that is used to be provided with single-board operation state; Said state selects module to comprise: resistance and jumper wire device, and an end of said resistance connects power supply, and the other end connects said jumper wire device; The end ground connection that said jumper wire device is not connected with said resistance, the link of said resistance and said jumper wire device are connected to the input/output port of said EPLD.
Further; A kind of data handling system; Comprise: main equipment and veneer with serial ports; Said main equipment is connected with said veneer through serial ports; Wherein, said veneer comprises: but be used to change the serial ports level the serial ports level switch module, be used to carry out wiping editorial logic device (EPLD) module, be used to carry out the processor module of debugging single board and be used for storage version memory of data module of serial data transmitting-receiving, command analysis, data processing, memory module read-write, single-board operation state conversion and controlling links, said EPLD module is connected with serial ports level switch module, processor module and memory module respectively.
Further; Said EPLD module comprises: be used to carry out serial communication the serial data transceiver module, be used for resolve command word and edition data; Sending command word to state switches and link control module; With edition data send to the FLASH bus interface module command analysis and data processing module, be used for edition data is loaded into the FLASH bus interface module of memory module and is used for the processor controls module and the link-attached state of serial data transceiver module switches and link control module; Wherein, Said state switches and link control module is connected with command analysis and data processing module with said serial data transceiver module respectively, and said command analysis and data processing module also are connected with the FLASH bus interface module with said serial data transceiver module respectively.
Further; Said serial data transceiver module and processor module all comprise serial data and send (TXD) end and serial data reception (RXD) end; The TXD end of said serial data transceiver module links to each other with the TXD end of serial ports; The RXD end of said serial data transceiver module links to each other with the RXD end of serial ports through said state switching and link control module, and the TXD end of said processor module all switches through said state with the RXD end and link control module links to each other with the RXD end with the TXD end of serial ports respectively.
Further, adopt parallel data communication between said serial data transceiver module and command analysis and the data processing module.
Further; Also comprise the state selection module that is used to be provided with single-board operation state; Said state selects module to comprise: resistance and jumper wire device, and an end of said resistance connects power supply, and the other end connects said jumper wire device; The end ground connection that said jumper wire device is not connected with said resistance, the link of said resistance and said jumper wire device are connected to the input/output port of said EPLD.
In sum, the utility model can replace debugging single board and FLASH downloads the mode that needs use serial ports and these two kinds of interfaces of parallel port, only needs single serial ports can accomplish debugging single board and FLASH download; Avoid the inconvenience of using the parallel port to bring, simplified single board interface; For not possessing the environment of downloading the parallel port a kind of new downloading mode is provided simultaneously.
Description of drawings
Fig. 1 is the hardware synoptic diagram of the data handling system of the utility model;
Fig. 2 is that the state in the utility model selects the hardware of module to connect block diagram;
Fig. 3 is the inner function module block diagram of the EPLD module in the utility model;
Fig. 4 is the duty and the conversion block diagram of the veneer of the utility model.
Embodiment
Consider being showing improvement or progress day by day and simplifying of PC, a lot of PCs no longer provide external parallel port; The parallel port cable is made and is used all not as good as serial ports conveniently simultaneously; Adopt the parallel port under environment such as laboratory, machine room and outfield thereof, veneer to be debugged and FLASH Boot version carries out that more new capital is very inconvenient; Therefore; The proposition of this embodiment is a kind of can support to debug veneer and the data handling system that loads with FLASH simultaneously through serial ports; Through multiplexing single serial ports, cooperate the EPLD logic function to realize that the debugging of veneer and FLASH load.
For serial ports, connect in many application one, because the order that serial ports can not the automatic arbitration equipment sending data; So the state that is provided with switches and link control module; The changeable duty of this module, the corresponding path of control connects, and realizes that a band multibus formula time-division communication of serial ports connects.This topology connects, and can realize easily that veneer function, performance adjustment and FLASH download.
For technical matters, technical scheme and advantage that this embodiment is solved is clearer, will combine accompanying drawing and specific embodiment to be described in detail below.
Fig. 1 is serial ports and closes debugging and the hardware synoptic diagram of the device of loading FLASH, comprising: the main equipment (PC) of band serial ports, download cable, state are selected module, serial ports level switch module, EPLD module, processor module (CPU module) and memory module (FLASH module).
The 101st, the RS232 serial ports that PC is external, the order on backstage or version send on the veneer through this serial ports.
The 102nd, state is selected module, and this module realizes through a jumper wire device and a pull-up resistor.EPLD reads the duty that level state is provided with veneer.
The 103rd, the serial ports level switch module is realized the conversion of 232 level and Transistor-Transistor Logic level, adopts level transferring chip commonly used to realize, like MAX3232.
The 104th, the EPLD module, multinomial functions such as serial data transmitting-receiving, command analysis and data processing, FLASH read-write, state exchange and controlling links will be accomplished in EPLD inside.The see below description of Fig. 3 of the specific descriptions of EPLD internal module.
The 105th, the CPU module, under the AccessPort state, the serial ports direct communication of the serial ports of PC and CPU is printed or is read information and is used for debugging single board.
The 106th, the FLASH module can mark off the BOOT version that the 1MByte zone is used to deposit veneer with its low side.
Serial ports is connected to EPLD and CPU simultaneously; PC sends data through serial ports, and EPLD and CPU can receive data simultaneously; But EPLD and CPU can not send data simultaneously, can cause the output competition like this, for effectively addressing this problem; In the EPLD set inside state switch and link control module, this module receives duty instruction, when device is in the debugging attitude; Connect the CPU sendaisle, break off the sendaisle of EPLD; When device is in the download attitude, connect the sendaisle of EPLD, break off the sendaisle of CPU; Thereby one of realization serial ports is with the communication of two bus type time-divisions to connect.
Load step comprises:
(1) plugs wire jumper, be chosen as the serial ports loading mode; Perhaps send order and switch to the serial ports downloading mode through serial ports
(2), BOOT file to be loaded is imported in PC running background downloaded software;
(3) version sends to the serial data transceiver module of EPLD through the debug serial port line, again through delivering to the FLASH interface module behind command analysis and the data processing module;
(4) EPLD writes version among the FLASH through local bus.
But state selects the support hardware wire jumper that duty is set, and goes back support software order switch operating state, realizes hardware, the two switching controls of software, has further increased the dirigibility of device.
Fig. 2 is that state selects the hardware of module to connect block diagram.The 201st, resistance, S202 are jumper wire devices.One end of resistance is pulled to VCC, the end ground connection that other end tie jumper device, jumper wire device are not connected with resistance.Receive between resistance and the jumper wire device on the IO mouth of EPLD.During the debugging veneer, wire jumper is not inserted, and the IO mouth of EPLD reads high level, veneer is set is the debugging attitude.When needing to load FLASH, can plug wire jumper, the IO mouth of EPLD reads low level, is chosen as hard mode and downloads attitude.
Fig. 3 is an EPLD inner function module block diagram.EPLD inside is with AccessPort and load relevant totally four modules: 301 is the serial data transceiver module; 302 is command analysis and data processing module; 303 is the FLASH bus interface module; 304 are state switching and link control module.
The communication of the serial ports of 301 completion and PC, the while and 302 is realized parallel data communications.
302 analyze the data that the serial data transceiver module receives, and parse command word and edition data, send command word to 304, and edition data sends 303 to; Receive 303 data that read on the other hand and send 301 to.
303 simulate the FLASH read-write sequences, edition data is loaded into perhaps reads the data among the FLASH among the FLASH.
304 settings according to hardware jumper, perhaps according to setting or the switching of software command word to duty, the control link corresponding connects, and implement device debugging and download time-division are difunctional, specifically describe the description of the Fig. 4 that sees below.
Fig. 4 is the block diagram of duty and conversion.
S401 is the attitude that resets, and is the initial state of system; The EPLD module powers on and device resets all gets into this state, and system starts working from this stationary state.
S402 shows that for the debugging attitude system is in the debugging single board state, connects the serial ports sendaisle of CPU this moment, breaks off the serial ports sendaisle of EPLD, and serial ports is realized the debugging single board function; The EPLD module receives serial data, resolves whether the duty switching command is arranged, and has then to switch to S403; Whether the detection hardware wire jumper is set to S404, and testing then, state switches to S404.
S403 is that soft mode is downloaded attitude; Show that system switches to download state by software instruction; Connect the serial ports sendaisle of EPLD module this moment, break off the serial ports passage of CPU, serial ports is realized the FLASH download function; To send the edition data that gets off by serial ports and write among the FLASH, perhaps the data that read among the FLASH sent to serial ports; EPLD receives serial data, resolves whether the duty switching command is arranged, and has then to switch to S402.
S404 is that hard mode is downloaded attitude; Show that device is to be set to download state by hardware jumper; Connect the serial ports sendaisle of EPLD module this moment, break off the serial ports passage of CPU, serial ports is realized the FLASH download function; To send the edition data that gets off by serial ports and write among the FLASH, perhaps the data that read among the FLASH sent to serial ports; Whether the detection hardware wire jumper is set to S402, and testing then, state switches to S402.
System powers on or resets and all can be introduced into S401, starts working from this state; S401 detection hardware wire jumper is set to S402, and S404 detection hardware wire jumper is set to S402, and S403 receives orders and switches to S402, and system all can get into S402; S401 detection hardware wire jumper is set to S404, and S402 detection hardware wire jumper is set to S404, and system all can get into S404; S402 receives orders and switches to S403, and system gets into S403.
Only be used for the function and the performance adjustment of veneer to present serial port of a board, special-purpose PC is downloaded the applied environment of FLASH content through the parallel port, and this embodiment has following advantage:
(1) can carry out veneer function, performance adjustment;
(2) no parallel port PC download FLASH data (at present a lot of PC have not supported the parallel port);
(3) need not the parallel port and download cable environment download FLASH data, like test, software development department concrete parallel port download environment
(4) reduce single board interface and connect, only need a serial ports to connect and get final product, flexible and convenient to use;
(5) outfield veneer FLASH content update.
More than be in order to make those of ordinary skills understand the utility model; And to detailed description that the utility model carried out; But can expect; Under the situation of the thought that does not break away from the utility model, any distortion, revise and be equal to and substitute all in the scope that claim contained of the utility model.
Claims (10)
1. veneer; It is characterized in that; Comprise: but be used to change the serial ports level the serial ports level switch module, be used to carry out wiping editorial logic device (EPLD) module, be used to carry out the processor module of debugging single board and be used for storage version memory of data module of serial data transmitting-receiving, command analysis, data processing, memory module read-write, single-board operation state conversion and controlling links; Wherein, said EPLD module is connected with serial ports level switch module, processor module and memory module respectively.
2. veneer as claimed in claim 1; It is characterized in that; Said EPLD module comprises: be used to carry out serial communication the serial data transceiver module, be used for resolve command word and edition data; Sending command word to state switches and link control module; With edition data send to the FLASH bus interface module command analysis and data processing module, be used for edition data is loaded into the FLASH bus interface module of memory module and is used for the processor controls module and the link-attached state of serial data transceiver module switches and link control module; Wherein, said state switches and link control module is connected with command analysis and data processing module with said serial data transceiver module respectively, and said command analysis and data processing module also are connected with the FLASH bus interface module with said serial data transceiver module respectively.
3. veneer as claimed in claim 2; It is characterized in that: said serial data transceiver module and processor module all comprise serial data and send (TXD) end and serial data reception (RXD) end; The TXD end of said serial data transceiver module links to each other with the TXD end of serial ports; The RXD end of said serial data transceiver module links to each other with the RXD end of serial ports through said state switching and link control module, and the TXD end of said processor module all switches through said state with the RXD end and link control module links to each other with the RXD end with the TXD end of serial ports respectively.
4. veneer as claimed in claim 2 is characterized in that: adopt parallel data communication between said serial data transceiver module and command analysis and the data processing module.
5. veneer as claimed in claim 1; It is characterized in that also comprise the state selection module that is used to be provided with single-board operation state, said state selects module to comprise: resistance and jumper wire device; One end of said resistance connects power supply; The other end connects said jumper wire device, the end ground connection that said jumper wire device is not connected with said resistance, and the link of said resistance and said jumper wire device is connected to the input/output port of said EPLD.
6. data handling system; It is characterized in that; Comprise: main equipment and veneer with serial ports; Said main equipment is connected with said veneer through serial ports; Wherein, said veneer comprises: but be used to change the serial ports level the serial ports level switch module, be used to carry out wiping editorial logic device (EPLD) module, be used to carry out the processor module of debugging single board and be used for storage version memory of data module of serial data transmitting-receiving, command analysis, data processing, memory module read-write, single-board operation state conversion and controlling links, said EPLD module is connected with serial ports level switch module, processor module and memory module respectively.
7. data handling system as claimed in claim 6; It is characterized in that: said EPLD module comprises: be used to carry out serial communication the serial data transceiver module, be used for resolve command word and edition data; Sending command word to state switches and link control module; With edition data send to the FLASH bus interface module command analysis and data processing module, be used for edition data is loaded into the FLASH bus interface module of memory module and is used for the processor controls module and the link-attached state of serial data transceiver module switches and link control module; Wherein, Said state switches and link control module is connected with command analysis and data processing module with said serial data transceiver module respectively, and said command analysis and data processing module also are connected with the FLASH bus interface module with said serial data transceiver module respectively.
8. data handling system as claimed in claim 7; It is characterized in that: said serial data transceiver module and processor module all comprise serial data and send (TXD) end and serial data reception (RXD) end; The TXD end of said serial data transceiver module links to each other with the TXD end of serial ports; The RXD end of said serial data transceiver module links to each other with the RXD end of serial ports through said state switching and link control module, and the TXD end of said processor module all switches through said state with the RXD end and link control module links to each other with the RXD end with the TXD end of serial ports respectively.
9. data handling system as claimed in claim 7 is characterized in that: adopt parallel data communication between said serial data transceiver module and command analysis and the data processing module.
10. data handling system as claimed in claim 6; It is characterized in that also comprise the state selection module that is used to be provided with single-board operation state, said state selects module to comprise: resistance and jumper wire device; One end of said resistance connects power supply; The other end connects said jumper wire device, the end ground connection that said jumper wire device is not connected with said resistance, and the link of said resistance and said jumper wire device is connected to the input/output port of said EPLD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220049960 CN202615386U (en) | 2012-02-16 | 2012-02-16 | Single board and data processing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220049960 CN202615386U (en) | 2012-02-16 | 2012-02-16 | Single board and data processing system |
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| Publication Number | Publication Date |
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| CN202615386U true CN202615386U (en) | 2012-12-19 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201220049960 Expired - Fee Related CN202615386U (en) | 2012-02-16 | 2012-02-16 | Single board and data processing system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107391321A (en) * | 2016-05-17 | 2017-11-24 | 中兴通讯股份有限公司 | Electronic computer veneer and server debugging system |
-
2012
- 2012-02-16 CN CN 201220049960 patent/CN202615386U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107391321A (en) * | 2016-05-17 | 2017-11-24 | 中兴通讯股份有限公司 | Electronic computer veneer and server debugging system |
| CN107391321B (en) * | 2016-05-17 | 2021-10-12 | 中兴通讯股份有限公司 | Electronic computer single board and server debugging system |
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| C14 | Grant of patent or utility model | ||
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121219 Termination date: 20190216 |