CN105487875B - Control method, control device and its processor system of program storage - Google Patents
Control method, control device and its processor system of program storage Download PDFInfo
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- CN105487875B CN105487875B CN201510967558.1A CN201510967558A CN105487875B CN 105487875 B CN105487875 B CN 105487875B CN 201510967558 A CN201510967558 A CN 201510967558A CN 105487875 B CN105487875 B CN 105487875B
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Abstract
Disclose control method, control device and its processor system of program storage.Described program storage control device, comprising: first port, for being connected with processor；Second port, for being connected with cache memory；And third port, for being connected with interface controller, wherein, described program storage control device provides the routing function of control signal, so that the first control signal path between second port and third port or the second control signal path between first port and third port are connected to.The control method makes the program storage interface of processor system can be realized PLC technology, to realize the extension of the online upgrading and data storage of program storage.
Description
Technical field
The invention belongs to computer technologies, more particularly, to the control method of program storage, control device and its place
Manage device system.
Background technique
In processor system, program storage may be simultaneously used for protecting for saving application code (instruction)
Deposit the data (such as operand, look-up table information) used when program executes.For the place of those only one program storages
Device system is managed, CPU often has instruction buffer.When required instruction not in the buffer when will finger on reading program memory
It enables.So the interface of CPU and program storage is constantly communicated when processor system program behaves.This time-histories
The control of sequence memory interface gives CPU, therefore can not carry out programmable read-write operation to program storage.
Fig. 1 shows the schematic block diagram of processor system according to prior art.Processor system includes system on chip
(SoC) 100 and program storage 200.System on chip 100 includes central processing unit (CPU) 101, cache memory
(CACHE) 102 and interface controller 103.Although being not shown, system on chip 100 can also include memory (RAM).It connects
Mouth controller 103 is responsible for control program storage 200, and a part of data of program storage 200 are called in speed buffering automatically
In memory 102.The instruction of CPU and operand are perhaps obtained by cache memory 102 or via Interface Controller
Device 103 is obtained from program storage 200.
In the operating condition, central processing unit 101 is according to present instruction and operand content, from program storage 200
Next destination address obtains new instruction and operand, executes aforesaid operations repeatedly.Therefore, CPU is exclusive in the operating condition
The interface of program storage 200.
Due to the limitation of the processor architecture, so that showing inconvenience when realizing certain applications.For example, upgrading in program
When it is necessary to using external debugging device that system is first allowed to enter debugging mode, then carry out program upgrading, or need to store program
Under device is welded from circuit board, after the good new procedures of burning, then program storage device burn-on machine.
However, it is expected that can be logical with system by peripheral apparatus (such as USB flash disk of built-in upgrade file) in the operating condition
Letter completes the upgrading of program.
Summary of the invention
The purpose of the present invention is to provide a kind of journeys that can carry out peripheral operation to program storage in the operating condition
Control method, control device and its processor system of sequence memory.
According to an aspect of the present invention, a kind of program storage control device is provided, comprising: first port is used for and place
Device is managed to be connected；Second port, for being connected with cache memory；And third port, for being connected with interface controller,
Wherein, described program storage control device provides the routing function of control signal, so that between second port and third port
First control signal path or first port and third port between second control signal path be connected to.
Preferably, the third port includes third control port and third data port, the control of described program memory
Device further include: control register is connected, and via third data port and interface with processor respectively via first port
Controller is connected；And selector, it is connected respectively via second port with cache memory, via the 4th internal port
It is connected with control register, and is connected via third control port with interface controller, wherein the selector further includes choosing
Port is selected, the control register provides selection signal to the selection port of the selector, so that second port and the 4th end
One of mouth is connected to third control port, to select one of first control signal path and second control signal path.
According to another aspect of the present invention, a kind of processor system is provided, comprising: program storage, for storing program
Data；Interface controller is connect with program storage, and manages the access for being directed to program storage；Cache memory,
It is connect with interface controller, for obtaining program data from program storage via interface controller, to provide needed for processor
Instruction and operand；Processor is connect with cache memory, is used for from cache memory acquisition instruction and operation
Number；And program storage control device, including first port, for being connected with processor；Second port, for slow with high speed
Memory is rushed to be connected；And third port, for being connected with interface controller, wherein described program storage control device mentions
For controlling the routing function of signal, so that first control signal path or first end between second port and third port
Mouth is connected to the second control signal path between third port, when first control signal path is connected to, the Interface Controller
Device works in CPU control model, wherein carry out data buffer storage automatically between cache memory and program storage,
When second control signal path is connected to, the interface controller works in register control model, and wherein processor deposits program
Reservoir reads and writes and at least one of erasing operation operation.
Preferably, the third port includes third control port and third data port, the control of described program memory
Device further include: control register is connected, and via third data port and interface with processor respectively via first port
Controller is connected；And selector, it is connected respectively via second port with cache memory, via the 4th internal port
It is connected with control register, and is connected via third control port with interface controller, wherein the selector further includes choosing
Port is selected, the control register provides selection signal to the selection port of the selector, so that second port and the 4th end
One of mouth is connected to third control port, to select one of first control signal path and second control signal path.It is preferred that
Ground, processor are the internal processor in system on chip.
Preferably, in CPU control model, processor is deposited via cache memory and interface controller from program
Acquisition instruction and/or operand in reservoir.
Preferably, the processor system further includes memory, and the Memory linkage is used between processor and peripheral apparatus
In the data that storage is read from peripheral apparatus, wherein in register control model, processor reads the data of memory, and
Via program storage control device and interface controller write-in program memory.
Preferably, the data of memory are at least part of upgrade file.
Preferably, cache memory has address lock function, and driver is copied to speed buffering in advance
In memory and after locking, the driver in cache memory, the operating mode of switching interface controller are just executed.
Preferably, the interface of program storage is the interface of programmable multiplexing.
Preferably, described program memory is SPI FLASH, also, the processor system further includes that SPI interface is set
Standby, the SPI FLASH and the SPI equipment are connected to interface controller via public spi bus.
Preferably, by the Time-sharing control of chip selection signal, the multiplexing control of SPI FLASH and SPI interface equipment is realized.
According to another aspect of the invention, a kind of control method of program storage is provided, comprising: in interface controller
First mode copies to driver in cache memory；Interface controller is switched into the second mould from first mode
Formula；And the second mode in interface controller, by data from memory write-in program memory, wherein first mode is interface
The CPU control model of controller, wherein carry out data buffer storage automatically between cache memory and program storage, second
Mode be interface controller register control model, wherein processor to program storage read and write and erasing operation in
At least one operation.
Preferably, described program memory includes program area and reserved area, wherein the first reproducer of program area storage,
Upgrade driver and the second reproducer.
Preferably, including: the first reproducer of execution for the step that driver copies in cache memory will
Driver copies in cache memory, wherein copies to driver in cache memory simultaneously in advance
After locking, the driver in cache memory, the operating mode of switching interface controller are just executed, the high speed is delayed
Memory is rushed with address lock function.
Preferably, before the step of by data from memory write-in program memory further include: executing the second reproducer will
File in peripheral apparatus reads in memory.
Preferably, the routing function of control signal is provided by program storage control device, so that interface controller work
Make in one of first mode and second mode.
Preferably, program storage control device include respectively with processor, cache memory, interface controller phase
First even is to third port, and program storage control device is according to selection signal, so that second port and third port
Between first control signal path or first port and third port between second control signal path be connected to.
It preferably, include: the reserved area of erasing program storage from memory write-in program memory by data；Judgement is external
Whether data are greater than memory headroom；And according to judging result, by external data one-time write program storage or piecemeal
Write-in program memory, wherein if external data is less than or equal to memory headroom, by external data one-time write program
It, will be in external data piecemeal write-in program memory if external data is greater than memory headroom in memory.
Preferably, before by external data one-time write program storage, further includes: all read in external data
In memory；And the program area of erasing program storage.
It preferably, include: that external data piecemeal is copied into program storage by external data piecemeal write-in program memory
The reserved area of device；Wipe the program area of program storage；And the reserved area content of program storage is copied to program area.
It preferably, include: by a part of external data by the reserved area that external data piecemeal copies to program storage
It is read into memory；Data in memory are copied to the reserved area of program storage；And repeat to read in step and copy step,
Until external data all copies to the reserved area of program storage.
Preferably, by data after memory write-in program memory, further includes: system re-powers, or in height
Reset routine is run in fast buffer storage, so that the program that system newly upgrades execution.
Preferably, the data in the memory are at least part of upgrade file, also, the driver is upgrading
Driver.
According to the processor system of above-described embodiment, wherein using the work of storage control device configuration interface controller
Mode carries out data buffer storage, in register in CPU control model automatically between cache memory and program storage
In control model, central processing unit can read and write to program storage and erasing operation.
Since the program storage interface of processor system can be realized PLC technology, thus the application of processor system
Flexibility increases, and is not limited only to provide scalable system, and can provide memory expansion function.
According to the processor system of above-described embodiment, increase hardware access, so that the control access of program storage increases
, free switching channel in program operation process is realized, makes it possible to realize the function of program upgrading.
In a preferred embodiment, interface controller first works in CPU control model, by executing the first reproducer,
Driver is transported in cache.Then driver is locked, driver is run, so that interface controller
Register control model is worked in, data to be upgraded are written to reserved area.
The preferred embodiment has the advantage that
In register control model, driver is executed, using a part of region of cache as upgrade procedure
Carrier comes using upgrade procedure is placed on cache locking region, has shared program memory resource, has saved hardware money
Source.
The processor system is a kind of programmable from upgrade-system.The first duplication of storage in the program area of program storage
Program, upgrading driver and the second reproducer, can be realized upgrading using itself program.In contrast, in existing skill
In the upgrading scheme of art, the upgrade file of peripheral apparatus needs to provide the first reproducer and upgrading driver, otherwise upgrades
Just it cannot achieve.Of the invention does not have in addition open up new upgrading memory block, saves memory headroom.Since processor system itself wraps
Upgrade procedure is included, therefore the compatibility of upgrade procedure can be improved.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1 shows the schematic block diagram of processor system according to prior art；
Fig. 2 shows the schematic block diagrams of the processor system of first embodiment according to the present invention；
Fig. 3 shows the schematic block diagram of program storage control device in Fig. 2；
Fig. 4 shows the schematic block diagram of the processor system of second embodiment according to the present invention；
Fig. 5 shows the flow chart of the processor system program upgrading of third embodiment according to the present invention；
Fig. 6 shows the flow chart of upgrade file write operation in Fig. 5；
Fig. 7 to 9 shows the storage operation schematic block diagram of different step；And
Figure 10 shows the schematic block diagram of the storage operation of program storage and data storage multiplexing.
Specific embodiment
The various embodiments that the present invention will be described in more detail that hereinafter reference will be made to the drawings.In various figures, identical element
It is indicated using same or similar appended drawing reference.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.
The present invention can be presented in a variety of manners, some of them example explained below.
Fig. 2 shows the schematic block diagrams of the processor system of first embodiment according to the present invention.The processor system packet
Include system on chip (SoC) 100 and program storage 200.The system on chip 100 includes central processing unit (CPU) 101, high speed
Buffer storage (CACHE) 102, interface controller 103 and memory 105 (for example, read-only memory, i.e. RAM).
In processor system, central processing unit 101 is for executing instruction.Cache memory 102 and central processing
Device 101 connects, for instruction and/or operand needed for caching central processing unit 101.Cache memory 102 is via connecing
Mouth controller 103 is connected to program storage 200.For example, peripheral apparatus 300 stores upgrade file.Connect by peripheral apparatus 300
It is connected to after system on chip 100, upgrade file is read in from peripheral apparatus 300 to memory 105.
In the working condition of system, a part of data of program storage 200 are called in speed buffering by interface controller 103
In memory 102.The instruction of CPU and operand are perhaps obtained by cache memory 102 or via Interface Controller
Device 103 is obtained from program storage 200.The data needed for cache memory 102 is stored with central processing unit 101 and
In the case of capable of reliably accessing, central processing unit 101 can directly obtain corresponding data from cache memory 102,
The situation is referred to as speed buffering hit (CACHE HIT).In contrast, when storage quilt no in cache memory 102
The case where data of the address of access request referred to as speed buffering miss (CACHE MISS).In this case, it needs quilt
The data requested access to are transferred to cache memory 102 via interface controller 103 from program storage 200.
It is different from the processor system of the prior art described in Fig. 1, in the processor system of embodiment according to the present invention
In, system on chip 100 further includes program storage control device 104.
Program storage control device 104 include respectively with central processing unit 101, cache memory 102, interface control
Device 103 processed be connected first to third port.For example, between program storage control device 104 and central processing unit 101,
It is connected via first port using register read-write bus.Program storage control device 104 and cache memory 102
Between, control signal is transmitted via second port.The third port of program storage control device 104 is divided into third control port
With third data port.Between program storage control device 104 and interface controller 103, transmitted via third control port
Signal is controlled, and transmits data-signal via third data port.
Program storage control device 104 provides the routing function of control signal.In this embodiment, signal is controlled for example
It is the read-write of program storage 200, data-signal is, for example, instruction needed for central processing unit 101 executes procedure operation
And/or operand.Figure it is seen that directly controlling signal between cache memory 102 and interface controller 103
Path has been modified to the first control signal path selected via program storage control device 104.In addition, program stores
Device control device 104 is also an option that the second control signal path between central processing unit 101 and interface controller 103.
Central processing unit 101 executes the pattern switching behaviour of interface controller 103 using program storage control device 104
Make, so that interface controller 103 may be at one of following first and second kinds of modes.First mode, that is, CPU control model,
In between cache memory 102 and program storage 200, carry out data buffer storage automatically.Second mode, that is, register control
Molding formula, wherein central processing unit 101 can read and write program storage 200 and erasing operation.For example, in the second mould
In formula, central processing unit 101 reads memory 105, obtains upgrade file and is written into program storage 200, to realize journey
The upgrading of sequence memory 200.
Central processing unit 101 not only can access program storage via cache memory 102 and interface controller 103
Device 200 can also access program storage 200 via program storage control device 104 and interface controller 103.
It can make the program storage interface of system other than instruction using the processor system of the framework, additionally it is possible to
Program storage is supported to upgrade.The program can be compatible with original processor system, and provide what's new at low cost.
In a preferred embodiment, the interface of program storage 200 is the interface of programmable multiplexing.Therefore, program stores
200 reusable of device is data storage.Program storage can be multiplexed with data storage, and program storage interface can be multiplexed
For the control bus of certain standards, so that systematic difference flexibility increases.
Fig. 3 shows the schematic block diagram of program storage control device according to an embodiment of the invention, wherein adopting
The module being indicated by the dashed box outside program storage control device, in order to describe program storage control device and external mould
Relationship between block.Program storage control device 104 includes control register 1041 and selector 1042.
Controlling register 1041 includes bus port and data port, respectively as program storage control device 104
First port and third data port, are connected with central processing unit 101 and interface controller 103.For example, control register
1041 bus port is connected with the register of standard read-write bus.Controlling register 1041 further includes selection port, with choosing
The selection port for selecting device 1042 is connected, so that latter provides selection signal.
Selector 1042 further includes first to third control port.First control port of selector 1042 is deposited as program
The second port of storage controller 104 is connected with cache memory 102.Second control port of selector 1042
It is connected with control register 1041.The third control port of selector 1042 as program storage control device 104
Three control ports are connected with interface controller 103.
According to the selection signal Spimux of the selection port of control register 1041, selector 1042 is controlled first and second
One of port processed is connected with third control port, select above-mentioned first control signal path and second control signal path it
One, to realize the routing function of control signal.When selecting the first signal path, interface controller 103 is that CPU controls mould
Formula.When selecting second signal path, interface controller 103 is register control model.
Since the data port of control register 1041 is connected with interface controller 103, mould is controlled in register
In formula, central processing unit 101 can transmit upgrade file via the data port of control register 1041, thus in Interface Controller
Under the control of device 103, by upgrade file write-in program memory 200.
Fig. 4 shows the schematic block diagram of the processor system of second embodiment according to the present invention.According to second embodiment
System on chip include system on chip (SoC) 100, SPI FLASH 210 and SPI interface equipment 220.It adopts in a second embodiment
System on chip 100 is identical as the structure of the system on chip 100 used in the first embodiment, thus omits its details.
Interface between system on chip 100 and SPI FLASH 210 and SPI interface equipment 220 uses public SPI
(Serial Peripheral Interface, i.e. Serial Peripheral Interface (SPI)) bus system.The bus system is a kind of synchronous serial
Peripheral Interface communicates processor in a serial fashion to exchange information with various peripheral equipments.
In a second embodiment, the example of program storage is SPI FLASH 210.Due to system on chip 100 and program
It is connected between memory using spi bus, therefore, which can be compatible with SPI interface equipment 220.It is selected and is believed by piece
The Time-sharing control of number CS1 and CS2, the multiplexing control of Lai Shixian SPI FLASH 210 and SPI interface equipment 220.
Fig. 5 is the flow chart of the program storage upgrade method of embodiment according to the present invention, and Fig. 7 to 9 shows asynchronous
Rapid storage operation schematic block diagram.Described program memory upgrade method includes following multiple steps.
The memory block of program storage 200 can be divided into different regions, i.e. program area and reserved area.Program area is center
The addressing space of processor 101 can schematically be divided into tri- pieces of A, B, C according to function, as shown in Figure 7.In program storage 200
Region A, B, C in store the first reproducer, upgrading driver and the second reproducer respectively.
In the step s 100, in the first mode of interface controller, upgrading driver is copied into caches
In device.First mode, that is, interface controller CPU control model, wherein in cache memory 102 and program storage 200
Between, data buffer storage is carried out automatically.
Upgrading driver is used to execute various operations of the upgrading hour hands to interface controller 103, for example including interface shape
The control program such as state changeover program and read-write erasing.In a preferred embodiment, carry out ground after duplication upgrades driver
Location locking, so that upgrading driver is in the address space of cache memory locking.
Fig. 7 shows the storage operation schematic block diagram of step S100, wherein for executing upgrading driver duplication behaviour
The first reproducer made is expressed as A program, and upgrades driver itself and be expressed as B program.
In step s 200, central processing unit 101 executes Interface status changeover program, by interface controller from first mode
Switch to second mode.Second mode, that is, interface controller register control model.
As described above, the interface controller 103 for only working as program storage 200 is switched to register control model,
The operation such as it can be written and read and wipe to interface, otherwise can conflict with 101 interface of central processing unit.
In step S300, in the second mode of interface controller, by upgrade file write-in program memory 200.If
When data storage cannot disposably read the case where upgrade file, then piecemeal reads upgrade file.Upgrade file write-in step
Suddenly it will be further described in conjunction with Fig. 6.
In a preferred embodiment, after step S300, system is re-powered, or is transported in the cache
Row reset routine, so that the program that system newly upgrades execution.
Fig. 6 shows the flow chart of upgrade file write step in Fig. 5.In order to execute the step S300 in Fig. 5, can execute
Multiple steps below.
In step S301, central processing unit 101 executes the upgrading driver in cache memory 102, to journey
Sequence memory 200 carries out erasing operation, to wipe the reserved area of program storage 200, prepares next step upgrade file data
Write-in.
In step s 302, judge whether upgrade file is greater than memory headroom.
If upgrade file is less than memory headroom, S303 is thened follow the steps to S305.
In step S303, the second reproducer in 101 executive memory 200 of central processing unit sets peripheral hardware
Standby interior upgrade file is all read into memory.
In step s 304, central processing unit 101 executes the upgrading driver in cache memory 102, to journey
Sequence memory 200 carries out erasing operation, to wipe the program area of program storage.
In step S305, central processing unit 101 executes the upgrading driver in cache memory 102, to journey
Sequence memory 200 carries out write operation, so that internal storage data to be written to the program area of program storage.
If upgrade file is greater than memory headroom, S306 is thened follow the steps to S310.
In step S306, the second reproducer in 101 executive memory 200 of central processing unit sets peripheral hardware
A part of standby interior upgrade file is read into memory.
In step S307, central processing unit 101 executes the upgrading driver in cache memory 102, to journey
Sequence memory 200 carries out write operation, so that internal storage data to be written to the reserved area of program storage.
In step S308, judge whether replicated whole upgrade files.If not replicating whole upgrade files, weigh
Multiple step S306 to S308.By repeatedly recycling, until whole upgrade files to be copied to the reserved area of program storage, into one
Step executes step S309 to S310.
Fig. 8 shows the storage operation schematic block diagram of step S306 to S308, wherein c program includes for executing liter
Second reproducer of grade file copy operation, and upgrade driver itself and be expressed as B program.
In step S309, central processing unit 101 executes the upgrading driver in cache memory 102, to journey
Sequence memory 200 carries out erasing operation, to wipe the program area of program storage 200.The step erases program storage
200 region A, B, C, such system code life is with regard to this termination.
In step s310, central processing unit 101 executes the upgrading driver in cache memory 102, to journey
Sequence memory 200 is read and writen operation, and the reserved area content of program storage 200 is copied to program area.
Fig. 9 shows the storage operation schematic block diagram of step S309 to S310, wherein upgrading driver itself indicates
For B program.
Figure 10 shows the schematic block diagram of the storage operation of program storage and data storage multiplexing.Such as Figure 10 institute
Show, can by reserved area as data storage come using.It can store some solid with the data field of expansion system, reserved area
Fixed data read reserved area when system needs in use, running driver in cache memory lock address
Write operation realizes data from memory 105 to the communication of the reserved area of program storage 200.
According to the processor system of above-described embodiment, wherein using the work of storage control device configuration interface controller
Mode carries out data buffer storage, in register in CPU control model automatically between cache memory and program storage
In control model, central processing unit can read and write to program storage and erasing operation.
In a preferred embodiment, cache memory has address lock function, replicates driver in advance
Into cache memory and after locking, the operating mode of ability switching interface controller.
The advantages of above-mentioned processor system is that upgrading is convenient, wired or wireless suitable for the communication interface of any mode
It is ok.It is run since upgrading driver is moved in cache memory, since cache memory is system
Essential module, so without additionally increasing hardware resource, save the cost.It will be upgraded using the reserved area of program storage
File temporarily saves, as long as having reference significance for lower cost solution so that system opens up a smaller memory.
Due to can be in the operating mode of the operating status switching interface controller of system, the application of above-mentioned processor system
Flexibility increases, and is not limited only to provide scalable system, and can provide memory expansion function.For example, storage is deposited
Reservoir is multiplexed with data storage, thus the data field of expansion system.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.Protection model of the invention
The range that the claims in the present invention are defined should be subject to by enclosing.
Claims (24)
1. a kind of program storage control device, comprising:
First port, for being connected with processor；
Second port, for being connected with cache memory；And
Third port, for being connected with interface controller,
Wherein, described program storage control device provides the routing function of control signal, so that second port and third port
Between first control signal path or first port and third port between second control signal path be connected to；
When first control signal path is connected to, the interface controller works in CPU control model, wherein in speed buffering
Automatically data buffer storage is carried out between memory and program storage,
When second control signal path is connected to, the interface controller works in register control model, and wherein processor will
The data writing program memory read from peripheral apparatus.
2. program storage control device according to claim 1, wherein the third port includes third control port
With third data port, described program storage control device further include:
Register is controlled, is connected respectively via first port with processor, and via third data port and interface controller
It is connected；And
Selector is connected via second port with cache memory respectively, deposits via the 4th internal port and control
Device is connected, and is connected via third control port with interface controller,
Wherein, second port is connected to form first between second port and third port via selector and third control port
Control signal path；First port is connected shape via control register, the 4th internal port, selector with third control port
At the second control signal path between first port and third port；
The selector further includes selection port, and the control register provides selection letter to the selection port of the selector
Number, so that one of second port and the 4th port are connected to third control port, to select first control signal path and
One of two control signal paths.
3. a kind of processor system, comprising:
Program storage, for storing program data；
Interface controller is connect with program storage, and manages the access for being directed to program storage；
Cache memory is connect with interface controller, for obtaining program number from program storage via interface controller
According to instruction and operand needed for providing processor；
Processor is connect with cache memory, is used for from cache memory acquisition instruction and operand；And
Program storage control device, including first port, for being connected with processor；Second port, is used for and speed buffering
Memory is connected；And third port, for being connected with interface controller,
Wherein, described program storage control device provides the routing function of control signal, so that second port and third port
Between first control signal path or first port and third port between second control signal path be connected to,
When first control signal path is connected to, the interface controller works in CPU control model, wherein in speed buffering
Automatically data buffer storage is carried out between memory and program storage,
When second control signal path is connected to, the interface controller works in register control model, and wherein processor will
The data writing program memory read from peripheral apparatus.
4. processor system according to claim 3, wherein the third port includes third control port and third number
According to port, described program storage control device further include:
Register is controlled, is connected respectively via first port with processor, and via third data port and interface controller
It is connected；And
Selector is connected via second port with cache memory respectively, deposits via the 4th internal port and control
Device is connected, and is connected via third control port with interface controller,
Wherein, second port is connected to form first between second port and third port via selector and third control port
Control signal path；First port is connected shape via control register, the 4th internal port, selector with third control port
At the second control signal path between first port and third port；
The selector further includes selection port, and the control register provides selection letter to the selection port of the selector
Number, so that one of second port and first port are connected to third control port, to select first control signal path and
One of two control signal paths.
5. processor system according to claim 3, wherein processor is the internal processor in system on chip.
6. processor system according to claim 3, wherein processor is deposited via speed buffering in CPU control model
Reservoir and interface controller, acquisition instruction and/or operand from program storage.
7. processor system according to claim 3 further includes memory, the Memory linkage is in processor and peripheral apparatus
Between, for storing the data read from peripheral apparatus, wherein in register control model, processor reads the number of memory
According to, and via program storage control device and interface controller write-in program memory.
8. processor system according to claim 7, wherein the data of memory are at least part of upgrade file.
9. processor system according to claim 3, wherein cache memory has address lock function, preparatory
Driver is copied in cache memory and after locking, the driver in cache memory is just executed,
The operating mode of switching interface controller.
10. processor system according to claim 3, wherein the interface of program storage is the interface of programmable multiplexing.
11. processor system according to claim 3, described program memory is SPI FLASH, also, the processing
Device system further includes SPI interface equipment, and the SPI FLASH and the SPI interface equipment are connected to via public spi bus
Interface controller.
12. processor system according to claim 11, wherein by the Time-sharing control of chip selection signal, realize SPI
The multiplexing of FLASH and SPI interface equipment controls.
13. a kind of control method of program storage, comprising:
In the first mode of interface controller, driver is copied in cache memory；
Interface controller is switched into second mode from first mode；And
In the second mode of interface controller, using driver by data from memory write-in program memory,
Wherein, first mode is the CPU control model of interface controller, wherein cache memory and program storage it
Between carry out data buffer storage automatically,
Second mode is the register control model of interface controller, and wherein processor reads and writes and wipes to program storage
Except at least one of operation operation.
14. control method according to claim 13, wherein described program memory includes program area and reserved area,
In, program area stores the first reproducer, upgrading driver and the second reproducer.
15. control method according to claim 14, wherein driver is copied to the step in cache memory
It suddenly include: to execute the first reproducer to copy to driver in cache memory,
Wherein, driver is being copied in advance in cache memory and after locking, is just executing caches
Driver in device, the operating mode of switching interface controller, the cache memory have address lock function.
16. control method according to claim 14, wherein before the step of by data from memory write-in program memory
Further include: the second reproducer, which is executed, by the file in peripheral apparatus reads in memory.
17. control method according to claim 13, wherein provide control signal by program storage control device
Routing function, so that interface controller works in one of first mode and second mode.
18. control method according to claim 17, wherein program storage control device include respectively with processor,
Cache memory, interface controller be connected first to third port, and program storage control device is according to selection
Signal, so that between first control signal path or first port and third port between second port and third port
Second control signal path connection.
19. control method according to claim 13, wherein include: from memory write-in program memory by data
Wipe the reserved area of program storage；
Judge whether external data is greater than memory headroom；And
According to judging result, by external data one-time write program storage or piecemeal write-in program memory,
Wherein, if external data is less than or equal to memory headroom, by external data one-time write program storage, such as
Fruit external data is greater than memory headroom, then will be in external data piecemeal write-in program memory.
20. control method according to claim 19, wherein by external data one-time write program storage it
Before, further includes:
External data is all read in memory；And
Wipe the program area of program storage.
21. control method according to claim 20, wherein include: by external data piecemeal write-in program memory
External data piecemeal is copied to the reserved area of program storage；
Wipe the program area of program storage；And
The reserved area content of program storage is copied to program area.
22. control method according to claim 21, wherein external data piecemeal is copied to the reservation of program storage
Area includes:
A part of external data is read into memory；
Data in memory are copied to the reserved area of program storage；And
It repeats to read in step and copy step, until external data all copies to the reserved area of program storage.
23. control method according to claim 13, by data after memory write-in program memory, further includes:
System re-powers, or runs reset routine in the cache, so that the journey that system newly upgrades execution
Sequence.
24. control method according to claim 13, wherein the data in the memory are at least one of upgrade file
Point, also, the driver is upgrading driver.
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| US20080183968A1 (en) * | 2007-01-30 | 2008-07-31 | Chi-Ting Huang | Computer system having cache system directly connected to nonvolatile storage device and method thereof |
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