CN105487875A - Control method and control device for program memory and processor system thereof - Google Patents
Control method and control device for program memory and processor system thereof Download PDFInfo
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- CN105487875A CN105487875A CN201510967558.1A CN201510967558A CN105487875A CN 105487875 A CN105487875 A CN 105487875A CN 201510967558 A CN201510967558 A CN 201510967558A CN 105487875 A CN105487875 A CN 105487875A
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Abstract
The invention discloses a control method and a control device for a program memory and a processor system thereof. The control device for a program memory comprises a first port connected with a processor, a second port connected with a cache memory, and a third port connected with an interface controller, wherein the control device for a program memory provides a routing function of control signals, so that a first control signal path between the second port and the third port or a second control signal path between the first port and the third port is communicated. By adopting the control method, a program memory interface of the processor system can be controlled in a programmable mode, so that on-line upgrade of a program memory and expansion of a data memory are realized.
Description
Technical field
The invention belongs to computer technology, more specifically, relate to the control method of program storage, control device and processor system thereof.
Background technology
In processor system, program storage, for preserving application code (instruction), can also be used for the data (such as operand, look-up table information) used when save routine performs simultaneously.Those are only had to the processor system of a program storage, CPU often has instruction buffer.When required instruction not in the buffer time will instruction on fetch program storer.So when processor system program is run, CPU constantly communicates with the interface of program storage.Now the control of program storage interface gives CPU, therefore cannot carry out programmable read-write operation to program storage.
Fig. 1 illustrates the schematic block diagram of the processor system according to prior art.Processor system comprises SOC (system on a chip) (SoC) 100 and program storage 200.SOC (system on a chip) 100 comprises central processing unit (CPU) 101, cache memory (CACHE) 102 and interface controller 103.Although do not illustrate in the drawings, SOC (system on a chip) 100 can also comprise internal memory (RAM).Control program storer 200 is responsible for by interface controller 103, a part of data of program storage 200 automatically called in cache memory 102.The instruction of CPU and operand or obtained by cache memory 102, or obtain from program storage 200 via interface controller 103.
In working order, central processing unit 101, according to present instruction and operand content, obtains new instruction and operand from the next destination address of program storage 200, repeatedly performs aforesaid operations.Therefore, CPU is descended to monopolize the interface of program storage 200 in working order.
Due to the restriction of this processor architecture, make when realizing some application aobvious inconvenient.Such as, when program upgrade, external debugging device will be used first to allow system enter debugging mode, then carry out program upgrade, or need by program storage device under circuit board weldering, after the good new procedures of burning, then machine that program storage device is burn-on.
But, expect can in working order under, completed the upgrading of program by peripheral apparatus (such as the USB flash disk of built-in upgrade file) and system communication.
Summary of the invention
The object of the present invention is to provide a kind of can in working order under the control method of the program storage of peripheral operation, control device and processor system thereof are carried out to program storage.
According to an aspect of the present invention, a kind of program storage control device is provided, comprises: the first port, for being connected with processor; Second port, for being connected with cache memory; And the 3rd port, for being connected with interface controller, wherein, described program storage control device provides the routing function of control signal, and the first control signal path between the second port with the 3rd port or the second control signal path between the first port with the 3rd port are communicated with.
Preferably, described 3rd port comprises the 3rd control port and the 3rd FPDP, and described program storage control device also comprises: control register, is connected respectively via the first port with processor, and is connected with interface controller via the 3rd FPDP; And selector switch, be connected with cache memory via the second port respectively, the 4th port via inside is connected with control register, and be connected with interface controller via the 3rd control port, wherein, described selector switch also comprises selection port, and described control register provides selection signal to the selection port of described selector switch, second port is communicated with the 3rd control port with one of the 4th port, thus selects one of the first control signal path and the second control signal path.
According to a further aspect in the invention, a kind of processor system is provided, comprises: program storage, for program data, interface controller, is connected with program storage, and management is for the access of program storage, cache memory, is connected with interface controller, for obtaining routine data via interface controller from program storage, to provide instruction needed for processor and operand, processor, is connected with cache memory, for obtaining instruction and operand from cache memory, and program storage control device, comprise the first port, for being connected with processor, second port, for being connected with cache memory, and the 3rd port, for being connected with interface controller, wherein, described program storage control device provides the routing function of control signal, make the first control signal path between the second port and the 3rd port, or the second control signal path between the first port with the 3rd port is communicated with, when the first control signal path is communicated with, described interface controller works in CPU control model, wherein, automatically data buffer storage is carried out between cache memory and program storage, when the second control signal path is communicated with, described interface controller works in register control model, wherein processor is read program storage, at least one operation in write and erase operation.
Preferably, described 3rd port comprises the 3rd control port and the 3rd FPDP, and described program storage control device also comprises: control register, is connected respectively via the first port with processor, and is connected with interface controller via the 3rd FPDP; And selector switch, be connected with cache memory via the second port respectively, the 4th port via inside is connected with control register, and be connected with interface controller via the 3rd control port, wherein, described selector switch also comprises selection port, and described control register provides selection signal to the selection port of described selector switch, second port is communicated with the 3rd control port with one of the 4th port, thus selects one of the first control signal path and the second control signal path.Preferably, processor is the internal processor in SOC (system on a chip).
Preferably, in CPU control model, processor, via cache memory and interface controller, obtains instruction and/or operand from program storage.
Preferably, described processor system also comprises internal memory, described Memory linkage is between processor and peripheral apparatus, for storing the data read from peripheral apparatus, wherein, in register control model, processor reads the data of internal memory, and via program storage control device and interface controller write-in program storer.
Preferably, the data of internal memory be upgrade file at least partially.
Preferably, cache memory has address lock function, in advance driver being copied in cache memory and after locking, and the driver just in execution cache memory, the mode of operation of switching interface controller.
Preferably, the interface of program storage is multiplexing interface able to programme.
Preferably, described program storage is SPIFLASH, and described processor system also comprises SPI interfacing equipment, and described SPIFLASH and described SPI equipment are connected to interface controller via public spi bus.
Preferably, by the Time-sharing control of chip selection signal, realize the multiplexing control of SPIFLASH and SPI interfacing equipment.
According to another aspect of the invention, a kind of control method of program storage is provided, comprises: at the first mode of interface controller, driver is copied in cache memory; Interface controller is switched to the second pattern from first mode; And in the second pattern of interface controller, by data from internal memory write-in program storer, wherein, first mode is the CPU control model of interface controller, wherein between cache memory and program storage, automatically carry out data buffer storage, second pattern is the register control model of interface controller, wherein processor program storage is read and write and in erase operation at least one operation.
Preferably, described program storage comprises program area and reserved area, and wherein, program area stores the first reproducer, upgrading driver and the second reproducer.
Preferably, the step copied to by driver in cache memory comprises: perform the first reproducer and copy in cache memory by driver, wherein, in advance driver being copied in cache memory and after locking, just perform the driver in cache memory, the mode of operation of switching interface controller, described cache memory has address lock function.
Preferably, data were also comprised before the step of internal memory write-in program storer: perform the second reproducer and the file in peripheral apparatus is read in internal memory.
Preferably, provided the routing function of control signal by program storage control device, make interface controller work in one of first mode and the second pattern.
Preferably, program storage control device comprises the first to the 3rd port be connected with processor, cache memory, interface controller respectively, and program storage control device, according to selection signal, makes the first control signal path between the second port with the 3rd port or the second control signal path between the first port with the 3rd port be communicated with.
Preferably, data are comprised from internal memory write-in program storer: the reserved area of erasing program storage; Judge whether external data is greater than memory headroom; And according to judged result, by external data one-time write program storage, or piecemeal write-in program storer, wherein, if external data is less than or equal to memory headroom, then by external data one-time write program storage, if external data is greater than memory headroom, then by external data piecemeal write-in program storer.
Preferably, before by external data one-time write program storage, also comprise: external data is all read in internal memory; And the program area of erasing program storage.
Preferably, external data piecemeal write-in program storer is comprised: reserved area external data piecemeal being copied to program storage; The program area of erasing program storage; And by the reserved area content replication of program storage to program area.
Preferably, reserved area external data piecemeal being copied to program storage comprises: a part for external data is read into internal memory; By the reserved area of the data Replica in internal memory to program storage; And repeat to read in step and copy step, until external data all copies to the reserved area of program storage.
Preferably, by data from after internal memory write-in program storer, also comprise: system re-powers, or run reset routine in the cache, make system to perform the program of new upgrading.
Preferably, the data in described internal memory be upgrade file at least partially, and, described driver for upgrading driver.
According to the processor system of above-described embodiment, wherein adopt the mode of operation of storage control device configuration interface controller, in CPU control model, automatically data buffer storage is carried out between cache memory and program storage, in register control model, central processing unit can read and write and erase operation program storage.
Because the program storage interface of processor system can realize PLC technology, thus the application flexibility of processor system increases, and is not limited only to provide upgradeable system, and can provides memory expansion function.
According to the processor system of above-described embodiment, increase hardware path, the control path of program storage is added, achieves free switching channel in program operation process, make it possible to the function realizing program upgrade.
In a preferred embodiment, interface controller first works in CPU control model, by performing the first reproducer, driver can be transported in high-speed cache.Then lock drive program, runs driver, makes interface controller work in register control model, data to be upgraded are written to reserved area.
This preferred embodiment has the following advantages:
In register control model, perform driver, the carrier of a part of region of high-speed cache as ROMPaq is used, is placed on cache locking region by ROMPaq, have shared program memory resource, saved hardware resource.
This processor system is a kind of programmable from upgrade-system.Store the first reproducer, upgrading driver and the second reproducer in the program area of program storage, utilize self program can realize upgrading.In contrast, in the upgrading scheme of prior art, the upgrade file of peripheral apparatus needs to provide the first reproducer and upgrading driver, otherwise upgrading just cannot realize.Of the present inventionly need not open up memory block of newly upgrading in addition, save memory headroom.Because processor system self comprises ROMPaq, the compatibility of ROMPaq therefore can be improved.
Accompanying drawing explanation
By referring to the description of accompanying drawing to the embodiment of the present invention, above-mentioned and other objects of the present invention, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1 illustrates the schematic block diagram of the processor system according to prior art;
Fig. 2 illustrates the schematic block diagram of the processor system according to the first embodiment of the present invention;
Fig. 3 illustrates the schematic block diagram of Fig. 2 Program storage control device;
Fig. 4 illustrates the schematic block diagram of processor system according to a second embodiment of the present invention;
Fig. 5 illustrates the process flow diagram of processor system program upgrade according to the third embodiment of the invention;
Fig. 6 illustrates the process flow diagram of upgrade file write operation in Fig. 5;
Fig. 7 to 9 illustrates the storage operation schematic block diagram of different step; And
Figure 10 illustrates the schematic block diagram of program storage and the multiplexing storage operation of data-carrier store.
Embodiment
Hereinafter with reference to accompanying drawing, various embodiment of the present invention is described in more detail.In various figures, identical element adopts same or similar Reference numeral to represent.For the sake of clarity, the various piece in accompanying drawing is not drawn in proportion.
The present invention can present in a variety of manners, below will describe some of them example.
Fig. 2 illustrates the schematic block diagram of the processor system according to the first embodiment of the present invention.This processor system comprises SOC (system on a chip) (SoC) 100 and program storage 200.Described SOC (system on a chip) 100 comprises central processing unit (CPU) 101, cache memory (CACHE) 102, interface controller 103 and internal memory 105 (such as, ROM (read-only memory), i.e. RAM).
In processor system, central processing unit 101 is for performing instruction.Cache memory 102 is connected with central processing unit 101, for the instruction needed for buffer memory central processing unit 101 and/or operand.Cache memory 102 is connected to program storage 200 via interface controller 103.Such as, peripheral apparatus 300 stores upgrade file.After peripheral apparatus 300 is connected to SOC (system on a chip) 100, upgrade file is read in internal memory 105 from peripheral apparatus 300.
In the duty of system, a part of data of program storage 200 are called in cache memory 102 by interface controller 103.The instruction of CPU and operand or obtained by cache memory 102, or obtain from program storage 200 via interface controller 103.Data needed for central processing unit 101 are stored and can in reliably access situation when cache memory 102, central processing unit 101 directly can obtain corresponding data from cache memory 102, this situation is called speed buffering hit (CACHEHIT).On the other hand, the situation of data when the address not storing accessed request in cache memory 102 is called speed buffering miss (CACHEMISS).In this case, need the data of requested access to be transferred to cache memory 102 from program storage 200 via interface controller 103.
Different from the processor system of the prior art described in Fig. 1, in processor system according to an embodiment of the invention, SOC (system on a chip) 100 also comprises program storage control device 104.
Program storage control device 104 comprises the first to the 3rd port be connected with central processing unit 101, cache memory 102, interface controller 103 respectively.Such as, between program storage control device 104 and central processing unit 101, register read-write bus is adopted to be connected via the first port.Between program storage control device 104 and cache memory 102, via the second port transfer control signal.3rd port of program storage control device 104 is divided into the 3rd control port and the 3rd FPDP.Between program storage control device 104 and interface controller 103, via the 3rd control port transfer control signal, and via the 3rd FPDP data signal.
Program storage control device 104 provides the routing function of control signal.In this embodiment, control signal is such as the read-write of program storage 200, data-signal be such as central processing unit 101 executive routine operation needed for instruction and/or operand.As can be seen from Figure 2, the direct control signal path between cache memory 102 and interface controller 103, has been revised as the first control signal path selected via program storage control device 104.In addition, program storage control device 104 can also select the second control signal path between central processing unit 101 and interface controller 103.
Central processing unit 101 adopts the mode switching operation of program storage control device 104 executive's interface controller 103, makes interface controller 103 can be in one of following first and second kinds of patterns.First mode and CPU control model, wherein between cache memory 102 and program storage 200, carry out data buffer storage automatically.Second pattern and register control model, wherein central processing unit 101 can read and write and erase operation program storage 200.Such as, in a second mode, central processing unit 101 reads internal memory 105, obtains upgrade file by its write-in program storer 200, thus realizes the upgrading of program storage 200.
Central processing unit 101 not only can via cache memory 102 and interface controller 103 access program storer 200, can also via program storage control device 104 and interface controller 103 access program storer 200.
Adopt the processor system of this framework can make the program storage interface of system except instruction, can also support that program storage is upgraded.The program can compatible original processor system, and provides what's new at low cost.
In a preferred embodiment, the interface of program storage 200 is multiplexing interface able to programme.Therefore, program storage 200 reusable is data-carrier store.Program storage can be multiplexed with data-carrier store, and program storage interface can be multiplexed with the control bus of some standard, and systematic difference dirigibility is increased.
Fig. 3 illustrates the schematic block diagram of program storage control device according to an embodiment of the invention, wherein adopts the module of the program storage control device outside that is indicated by the dashed box, so that describe the relation between program storage control device and external module.Program storage control device 104 comprises control register 1041 and selector switch 1042.
Control register 1041 comprises bus port and FPDP, respectively as the first port and the 3rd FPDP of program storage control device 104, is connected with interface controller 103 with central processing unit 101.Such as, the bus port of control register 1041 is read and write bus with the register of standard and is connected.Control register 1041 also comprises selection port, be connected, thus latter provides selection signal with the selection port of selector switch 1042.
Selector switch 1042 also comprises the first to the 3rd control port.First control port of selector switch 1042, as the second port of program storage control device 104, is connected with cache memory 102.Second control port of selector switch 1042 is connected with control register 1041.3rd control port of selector switch 1042, as the 3rd control port of program storage control device 104, is connected with interface controller 103.
According to the selection signal Spimux of the selection port of control register 1041, one of first and second control ports are connected with the 3rd control port by selector switch 1042, select above-mentioned one of the first control signal path and the second control signal path, thus realize the routing function of control signal.When selection the first signal path, interface controller 103 is CPU control model.When selecting secondary signal path, interface controller 103 is register control model.
Because the FPDP of control register 1041 is connected with interface controller 103, therefore, in register control model, central processing unit 101 can transmit upgrade file via the FPDP of control register 1041, thus under the control of interface controller 103, by upgrade file write-in program storer 200.
Fig. 4 illustrates the schematic block diagram of processor system according to a second embodiment of the present invention.SOC (system on a chip) (SoC) 100, SPIFLASH210 and SPI interfacing equipment 220 is comprised according to the SOC (system on a chip) of the second embodiment.The SOC (system on a chip) 100 adopted in a second embodiment is identical with the structure of the SOC (system on a chip) 100 adopted in a first embodiment, thus omits its details.
Interface between SOC (system on a chip) 100 and SPIFLASH210 and SPI interfacing equipment 220 adopts public SPI (SerialPeripheralInterface, i.e. Serial Peripheral Interface (SPI)) bus system.This bus system is a kind of synchronous serial Peripheral Interface, makes processor can carry out in a serial fashion communicating to exchange information with various peripherals.
In a second embodiment, the example of program storage is SPIFLASH210.Because SOC (system on a chip) 100 is connected with adopting spi bus between program storage, therefore, this processor system can compatible SPI interfacing equipment 220.By the Time-sharing control of chip selection signal CS1 and CS2, realize the multiplexing control of SPIFLASH210 and SPI interfacing equipment 220.
Fig. 5 is the process flow diagram of program storage upgrade method according to an embodiment of the invention, and Fig. 7 to 9 illustrates the storage operation schematic block diagram of different step.Described program storage upgrade method comprises following multiple step.
The memory block of program storage 200 can be divided into different regions, i.e. program area and reserved area.Program area is the addressing space of central processing unit 101, schematically can be divided into A, B, C tri-pieces, as shown in Figure 7 according to function.The first reproducer, upgrading driver and the second reproducer is stored respectively in region A, B, C of program storage 200.
In the step s 100, at the first mode of interface controller, upgrading driver is copied in cache memory.The CPU control model of first mode and interface controller, wherein between cache memory 102 and program storage 200, carries out data buffer storage automatically.
Upgrading driver for performing the various operations of upgrading hour hands docking port controller 103, such as, comprises the control program such as Interface status changeover program and read-write erasing.In a preferred embodiment, after copying upgrading driver, carry out address locking, upgrading driver is in the address space of cache memory locking.
Fig. 7 illustrates the storage operation schematic block diagram of step S100, wherein, be expressed as A program, and driver self of upgrading is expressed as B program for the first reproducer performing the replicate run of upgrading driver.
In step s 200, central processing unit 101 executive's interface state changeover program, switches to the second pattern by interface controller from first mode.The register control model of the second pattern and interface controller.
As mentioned above, only have the interface controller 103 when program storage 200 to be switched to register control model, could carry out reading and writing and the operation such as erasing by docking port, otherwise can conflict with central processing unit 101 interface.
In step S300, in the second pattern of interface controller, by upgrade file write-in program storer 200.If data-carrier store can not the situation of disposable reading upgrade file time, then piecemeal reads upgrade file.Composition graphs 6 further describes by this upgrade file write step.
In a preferred embodiment, after step S300, system re-powers, or runs reset routine in the cache, makes system to perform the program of new upgrading.
Fig. 6 illustrates the process flow diagram of upgrade file write step in Fig. 5.In order to perform the step S300 in Fig. 5, following multiple step can be performed.
In step S301, central processing unit 101 performs the upgrading driver in cache memory 102, carries out erase operation to program storage 200, thus the reserved area of erasing program storage 200, prepare the write of next step upgrade file data.
In step s 302, judge whether upgrade file is greater than memory headroom.
If upgrade file is less than memory headroom, then perform step S303 to S305.
In step S303, the second reproducer in central processing unit 101 executive memory 200, is all read into internal memory by the upgrade file in peripheral apparatus.
In step s 304, central processing unit 101 performs the upgrading driver in cache memory 102, carries out erase operation to program storage 200, thus the program area of erasing program storage.
In step S305, central processing unit 101 performs the upgrading driver in cache memory 102, carries out write operation, thus internal storage data is written to the program area of program storage to program storage 200.
If upgrade file is greater than memory headroom, then perform step S306 to S311.
In step S306, the second reproducer in central processing unit 101 executive memory 200, is read into internal memory by a part for the upgrade file in peripheral apparatus.
In step S307, central processing unit 101 performs the upgrading driver in cache memory 102, carries out write operation, thus internal storage data is written to the reserved area of program storage to program storage 200.
In step S308, judge whether to copy whole upgrade file.If do not copy whole upgrade file, then repeat step S306 to S308.By repeatedly circulating, until whole upgrade file to be copied to the reserved area of program storage, perform step S309 to 311 further.
Fig. 8 illustrates the storage operation schematic block diagram of step S306 to S308, and wherein, c program comprises the second reproducer for performing upgrade file replicate run, and driver self of upgrading is expressed as B program.
In step S309, central processing unit 101 performs the upgrading driver in cache memory 102, carries out erase operation to program storage 200, thus the program area of erasing program storage 200.This step erases region A, B, C of program storage 200, and such system code life stops at this point.
In step S310, central processing unit 101 performs the upgrading driver in cache memory 102, reads and write operation program storage 200, by the reserved area content replication of program storage 200 to program area.
Fig. 9 illustrates the storage operation schematic block diagram of step S309 to S310, and wherein, upgrading driver self is expressed as B program.
Figure 10 illustrates the schematic block diagram of program storage and the multiplexing storage operation of data-carrier store.As shown in Figure 10, reserved area can be used as data-carrier store to use.Can the data field of expanding system, some fixing data can be deposited in reserved area, when system needs to use, run driver at cache memory lock address, read-write operation is carried out to reserved area and realizes data communication to the reserved area of program storage 200 from internal memory 105.
According to the processor system of above-described embodiment, wherein adopt the mode of operation of storage control device configuration interface controller, in CPU control model, automatically data buffer storage is carried out between cache memory and program storage, in register control model, central processing unit can read and write and erase operation program storage.
In a preferred embodiment, cache memory has address lock function, in advance driver being copied in cache memory and after locking, and the just mode of operation of switching interface controller.
The advantage of above-mentioned processor system is that upgrading is convenient, is applicable to the communication interface of any mode, wired or wireless can.Run because upgrading driver is moved in cache memory, because cache memory is the requisite module of system, so additionally do not increase hardware resource, cost-saving.Utilize the reserved area of program storage temporarily to be preserved by upgrade file, as long as make system open up a smaller internal memory, have reference significance for lower cost solution.
Due to can in the mode of operation of the running status switching interface controller of system, the application flexibility of above-mentioned processor system increases, and is not limited only to provide upgradeable system, and can provides memory expansion function.Such as, memory is multiplexed with data-carrier store, thus the data field of expanding system.
According to embodiments of the invention as described above, these embodiments do not have all details of detailed descriptionthe, do not limit the specific embodiment that this invention is only described yet.Obviously, according to above description, can make many modifications and variations.This instructions is chosen and is specifically described these embodiments, is to explain principle of the present invention and practical application better, thus makes art technician that the present invention and the amendment on basis of the present invention can be utilized well to use.The scope that protection scope of the present invention should define with the claims in the present invention is as the criterion.
Claims (24)
1. a program storage control device, comprising:
First port, for being connected with processor;
Second port, for being connected with cache memory; And
3rd port, for being connected with interface controller,
Wherein, described program storage control device provides the routing function of control signal, and the first control signal path between the second port with the 3rd port or the second control signal path between the first port with the 3rd port are communicated with.
2. program storage control device according to claim 1, wherein said 3rd port comprises the 3rd control port and the 3rd FPDP, and described program storage control device also comprises:
Control register, is connected with processor via the first port respectively, and is connected with interface controller via the 3rd FPDP; And
Selector switch, is connected with cache memory via the second port respectively, and the 4th port via inside is connected with control register, and is connected with interface controller via the 3rd control port,
Wherein, described selector switch also comprises selection port, described control register provides selection signal to the selection port of described selector switch, and the second port is communicated with the 3rd control port with one of the 4th port, thus selects one of the first control signal path and the second control signal path.
3. a processor system, comprising:
Program storage, for program data;
Interface controller, is connected with program storage, and management is for the access of program storage;
Cache memory, is connected with interface controller, for obtaining routine data via interface controller from program storage, to provide instruction needed for processor and operand; Processor, is connected with cache memory, for obtaining instruction and operand from cache memory; And
Program storage control device, comprises the first port, for being connected with processor; Second port, for being connected with cache memory; And the 3rd port, for being connected with interface controller,
Wherein, described program storage control device provides the routing function of control signal, and the first control signal path between the second port with the 3rd port or the second control signal path between the first port with the 3rd port are communicated with,
When the first control signal path is communicated with, described interface controller works in CPU control model, wherein, between cache memory and program storage, automatically carries out data buffer storage,
Second control signal path be communicated with time, described interface controller works in register control model, wherein processor program storage is read and write and in erase operation at least one operation.
4. processor system according to claim 3, wherein said 3rd port comprises the 3rd control port and the 3rd FPDP, and described program storage control device also comprises:
Control register, is connected with processor via the first port respectively, and is connected with interface controller via the 3rd FPDP; And
Selector switch, is connected with cache memory via the second port respectively, and the 4th port via inside is connected with control register, and is connected with interface controller via the 3rd control port,
Wherein, described selector switch also comprises selection port, described control register provides selection signal to the selection port of described selector switch, and the second port is communicated with the 3rd control port with one of the 4th port, thus selects one of the first control signal path and the second control signal path.
5. processor system according to claim 3, wherein processor is the internal processor in SOC (system on a chip).
6. processor system according to claim 3, wherein in CPU control model, processor, via cache memory and interface controller, obtains instruction and/or operand from program storage.
7. processor system according to claim 3, also comprise internal memory, described Memory linkage is between processor and peripheral apparatus, for storing the data read from peripheral apparatus, wherein, in register control model, processor reads the data of internal memory, and via program storage control device and interface controller write-in program storer.
8. processor system according to claim 7, wherein the data of internal memory be upgrade file at least partially.
9. processor system according to claim 3, wherein cache memory has address lock function, in advance driver being copied in cache memory and after locking, the driver just in execution cache memory, the mode of operation of switching interface controller.
10. processor system according to claim 3, wherein the interface of program storage is multiplexing interface able to programme.
11. processor systems according to claim 3, described program storage is SPIFLASH, and described processor system also comprises SPI interfacing equipment, and described SPIFLASH and described SPI equipment are connected to interface controller via public spi bus.
12. processor systems according to claim 11, wherein, by the Time-sharing control of chip selection signal, realize the multiplexing control of SPIFLASH and SPI interfacing equipment.
The control method of 13. 1 kinds of program storages, comprising:
At the first mode of interface controller, driver is copied in cache memory;
Interface controller is switched to the second pattern from first mode; And
In the second pattern of interface controller, adopt driver by data from internal memory write-in program storer,
Wherein, first mode is the CPU control model of interface controller, wherein between cache memory and program storage, automatically carries out data buffer storage,
Second pattern is the register control model of interface controller, wherein processor program storage is read and write and in erase operation at least one operation.
14. control methods according to claim 13, wherein, described program storage comprises program area and reserved area, and wherein, program area stores the first reproducer, upgrading driver and the second reproducer.
15. control methods according to claim 14, wherein, the step copied to by driver in cache memory comprises: perform the first reproducer and copy in cache memory by driver,
Wherein, in advance driver being copied in cache memory and after locking, the driver just in execution cache memory, the mode of operation of switching interface controller, described cache memory has address lock function.
Data wherein, were also comprised by 16. control methods according to claim 14 before the step of internal memory write-in program storer: perform the second reproducer and the file in peripheral apparatus is read in internal memory.
17. control methods according to claim 13, wherein, provide the routing function of control signal by program storage control device, make interface controller work in one of first mode and the second pattern.
18. control methods according to claim 17, wherein, program storage control device comprises the first to the 3rd port be connected with processor, cache memory, interface controller respectively, and program storage control device, according to selection signal, makes the first control signal path between the second port with the 3rd port or the second control signal path between the first port with the 3rd port be communicated with.
Data wherein, are comprised from internal memory write-in program storer by 19. control methods according to claim 13:
The reserved area of erasing program storage;
Judge whether external data is greater than memory headroom; And
According to judged result, by external data one-time write program storage, or piecemeal write-in program storer,
Wherein, if external data is less than or equal to memory headroom, then by external data one-time write program storage, if external data is greater than memory headroom, then by external data piecemeal write-in program storer.
20. control methods according to claim 19, wherein, before by external data one-time write program storage, also comprise:
External data is all read in internal memory; And
The program area of erasing program storage.
21. control methods according to claim 20, wherein, comprise external data piecemeal write-in program storer:
External data piecemeal is copied to the reserved area of program storage;
The program area of erasing program storage; And
By the reserved area content replication of program storage to program area.
22. control methods according to claim 21, wherein, comprise the reserved area that external data piecemeal copies to program storage:
A part for external data is read into internal memory;
By the reserved area of the data Replica in internal memory to program storage; And
Repeat to read in step and copy step, until external data all copies to the reserved area of program storage.
23. control methods according to claim 13, by data from after internal memory write-in program storer, also comprise:
System re-powers, or runs reset routine in the cache, makes system to perform the program of new upgrading.
24. control methods according to claim 13, the data in wherein said internal memory be upgrade file at least partially, and, described driver for upgrading driver.
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