CN202956753U - Programming device and programming system of flash memory chip in embedded system - Google Patents
Programming device and programming system of flash memory chip in embedded system Download PDFInfo
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- CN202956753U CN202956753U CN 201220578124 CN201220578124U CN202956753U CN 202956753 U CN202956753 U CN 202956753U CN 201220578124 CN201220578124 CN 201220578124 CN 201220578124 U CN201220578124 U CN 201220578124U CN 202956753 U CN202956753 U CN 202956753U
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Abstract
The utility model is suitable for the field of programmer design of a flash memory chip, and provides a programming device and a programming system of a flash memory chip in an embedded system. According to the programming device and the programming system of the flash memory chip in the embedded system, a lower computer is controlled by an upper computer through a serial port interface to complete program writing of the flash memory chip with a single program initiation (SPI) interface. Compared with an existing mode that a burner is used for downloading, cost is low, moreover the flash memory chip does not need to be taken out of a circuit board, and cockamamie operation brought by burning or updating of a program is avoided. Compared with an existing mode that a joint test action group (JTAG) interface is used for downloading, the hardware is simple in design, low in cost and high in writing speed. In addition, due to the fact that operation is directly carried on the flash memory chip and independent of a main control chip in the embedded system, the compatibility with the embedded system is good.
Description
Technical field
The utility model belongs to the programmable device design field of flash chip, relates in particular to programmer and the system of flash chip in a kind of embedded system.
Background technology
Known ground, in embedded system, flash memory (Flash) chip is generally as the booting ROM of main control chip in embedded system.In prior art, start-up routine is burnt to flash chip mainly contains dual mode:
One, the mode of utilizing cd-rom recorder to download.Under this kind mode, utilize special-purpose cd-rom recorder to complete writing of start-up routine, and the cost of cd-rom recorder itself is higher; And write fashionable, flash chip to be written must be disassembled from circuit board, after start-up routine writes, again flash chip is welded on circuit board, complex operation, be unfavorable for the upgrade maintenance of system, and easily cause hardware effort unstable or reduce storage life from circuit board dismounting flash chip frequently.
Two, the mode of utilizing jtag interface to download.This kind mode has been utilized the main control chip of embedded system itself, and main control chip connects host computer by USB interface or network interface, and main control chip has jtag interface, and connects flash chip to be written by jtag interface.When the write-enable program, main control chip is from the host computer receive data, and by jtag interface, data write in flash chip.This kind mode hardware design is complicated, cost is high, writing speed is slow, and can cause the difference of operational order due to the difference of main control chip, and therefore, this kind downloading mode generally adopts the specific download device, with the poor compatibility of other embedded system.
The utility model content
The purpose of this utility model is to provide the programmer of flash chip in a kind of embedded system, be intended to solve in prior art, if utilize the mode of cd-rom recorder download to the flash chip burning program, the problem of high, the complex operation of cost, if utilize the mode of jtag interface download to the flash chip burning program, cost is high, writing speed slow and the problem of poor compatibility.
The utility model is achieved in that the programmer of flash chip in a kind of embedded system, and described device comprises:
Slave computer, the SPI interface that it connects a host computer and connect flash chip by serial interface obtains data to be written and by described SPI interface, described data to be written is write described flash chip from described host computer via described serial interface.
Wherein, described slave computer can comprise:
One single-chip microcomputer, it obtains described data to be written and by described SPI interface, described data to be written is write described flash chip from described host computer via described serial interface by the SPI interface that described serial interface connects described host computer and connects described flash chip.
Further, described slave computer can also comprise:
One random access memory connects described single-chip microcomputer, and the data described to be written that described single-chip microcomputer obtains are carried out buffer memory.
Further, described slave computer can also comprise:
Level shifting circuit, described single-chip microcomputer connects described flash chip by described level shifting circuit.
In said apparatus, described single-chip microcomputer can be the single-chip microcomputer that is integrated with the SPI controller, and the SPI interface of described single-chip microcomputer connects the described SPI interface of described flash chip.
Another purpose of the present utility model is to provide the programing system of flash chip in a kind of embedded system, and described system comprises:
Host computer;
Slave computer, the SPI interface that it connects described host computer and connect flash chip by serial interface obtains data to be written and by described SPI interface, described data to be written is write described flash chip from described host computer via described serial interface.
Further, described slave computer can comprise:
One single-chip microcomputer, SPI interface that it connects described host computer and connect described flash chip by described serial interface obtains described data to be written and by described SPI interface, described data to be written is write described flash chip from described host computer via described serial interface.
Further, described slave computer can also comprise:
One random access memory, it connects described single-chip microcomputer, and the data described to be written that described single-chip microcomputer obtains are carried out buffer memory.
Further, described slave computer can also comprise:
Level shifting circuit, described single-chip microcomputer connects described flash chip by described level shifting circuit.
In said system, described single-chip microcomputer can be the single-chip microcomputer that is integrated with the SPI controller, and the SPI interface of described single-chip microcomputer connects the described SPI interface of described flash chip.
In the embedded system that the utility model provides, in the programing system of flash chip and device, host computer is controlled slave computer by serial interface and is write completing program with the flash chip of SPI interface.With respect to the existing mode of utilizing cd-rom recorder to download, cost is low and need not flash chip is taken out from circuit board, has avoided the troublesome operation of bringing because of burning program or upgrading; With respect to the existing mode of utilizing jtag interface to download, hardware design is simple, cost is low, writing speed is fast, and owing to being directly flash chip to be operated, and with embedded system in main control chip irrelevant, therefore compatible good with embedded system.
Description of drawings
Fig. 1 is the structural drawing of the programing system of flash chip in the embedded system that provides of the utility model;
Fig. 2 is a kind of structural drawing of slave computer in Fig. 1;
Fig. 3 is the another kind of structural drawing of slave computer in Fig. 1;
Fig. 4 is another structural drawing of slave computer in Fig. 1.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the utility model, and be not used in restriction the utility model.
Problem for the prior art existence, in the utility model, utilize slave computer 12 to obtain data to be written from host computer 11, and Serial Peripheral Interface (SPI) (the Serial Peripheral Interface by flash chip, SPI) interface writes flash chip with data to be written.
Fig. 1 shows the structure of the programing system of flash chip in the embedded system that the utility model provides, and for convenience of explanation, only shows the part relevant to the utility model.
In the embedded system that the utility model provides, the programing system of flash chip comprises: host computer 11; Connect host computer 11 and connect the SPI interface of flash chip by serial interface, obtain data to be written and by the SPI interface, data to be written are write the slave computer 12 of flash chip from host computer 11 via serial interface.
In the embedded system that the utility model provides in the programing system of flash chip, host computer 11 is controlled 12 pairs of flash chips with the SPI interface of slave computer by serial interface and is completed program and write.With respect to the existing mode of utilizing cd-rom recorder to download, cost is low and need not flash chip is taken out from circuit board, has avoided the troublesome operation of bringing because of burning program or upgrading; With respect to the existing mode of utilizing jtag interface to download, hardware design is simple, cost is low, writing speed is fast, and owing to being directly flash chip to be operated, and with embedded system in main control chip irrelevant, therefore compatible good with embedded system.
Fig. 2 shows a kind of structure of slave computer 12 in Fig. 1.
Particularly, slave computer 12 comprises: connect the SPI interface of host computer 11 and connection flash chip by serial interface, obtain data to be written and by the SPI interface, data to be written are write the single-chip microcomputer 121 of flash chip from host computer 11 via serial interface.
In the utility model, single-chip microcomputer 121 can use the communication control MSComm of Microsoft Visual C++ when carrying out serial communication with host computer 11, perhaps utilize Windows API communication functions; Perhaps utilize VC standard traffic function _ inp, _ inpw, _ inpd, _ outp, _ outpw, _ outpd etc. directly operates serial interface, perhaps utilizes the communication class program that the third party writes to realize serial communication.
Fig. 3 shows the another kind of structure of slave computer 12 in Fig. 1.
From shown in Figure 2 different, at this moment, slave computer 12 can also comprise: connect single-chip microcomputer 121, the data to be written that single-chip microcomputer 121 is obtained are carried out the random access memory 122 of buffer memory, and to satisfy the transmission of mass data, it improves the writing speed of system.
Fig. 4 shows another structure of slave computer 12 in Fig. 1.
From Fig. 1 to shown in Figure 3 different, if single-chip microcomputer 121 working powers are 3V or below 3V, slave computer 12 also comprises: be connected to the level shifting circuit 123 between single-chip microcomputer 121 and flash chip.And if single-chip microcomputer 121 working powers are 5V, adopt Fig. 1 to get final product to mode shown in Figure 3.
In addition, in the utility model, if single-chip microcomputer 121 is the single-chip microcomputers that are integrated with the SPI controller, the SPI interface of single-chip microcomputer 121 connects the SPI interface of flash chip; If single-chip microcomputer 121 is not the single-chip microcomputer that is integrated with the SPI controller, the Simulation with I of single-chip microcomputer 121/O interface connects the SPI interface of flash chip, at this moment, can utilize this Simulation with I/O interface simulation SPI sequential, flash chip is carried out data write.
The utility model also provides the programmer of flash chip in a kind of embedded system, this device comprises: connect a host computer and connect the SPI interface of flash chip by serial interface, obtain data to be written and by the SPI interface, data to be written are write the slave computer of flash chip from host computer via serial interface.The structure of this slave computer such as Fig. 2 are not repeated herein to shown in Figure 4.
In the embedded system that the utility model provides, in the programing system of flash chip and device, host computer 11 is controlled 12 pairs of flash chips with the SPI interface of slave computer by serial interface and is completed program and write.With respect to the existing mode of utilizing cd-rom recorder to download, cost is low and need not flash chip is taken out from circuit board, has avoided the troublesome operation of bringing because of burning program or upgrading; With respect to the existing mode of utilizing jtag interface to download, hardware design is simple, cost is low, writing speed is fast, and owing to being directly flash chip to be operated, and with embedded system in main control chip irrelevant, therefore compatible good with embedded system.
The above is only preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection domain of the present utility model.
Claims (10)
1. the programmer of flash chip in an embedded system, is characterized in that, described device comprises:
Slave computer, the SPI interface that it connects a host computer and connect flash chip by serial interface obtains data to be written and by described SPI interface, described data to be written is write described flash chip from described host computer via described serial interface.
2. the programmer of flash chip in embedded system as claimed in claim 1, is characterized in that, described slave computer comprises:
One single-chip microcomputer, it obtains described data to be written and by described SPI interface, described data to be written is write described flash chip from described host computer via described serial interface by the SPI interface that described serial interface connects described host computer and connects described flash chip.
3. the programmer of flash chip in embedded system as claimed in claim 2, is characterized in that, described slave computer also comprises:
One random access memory connects described single-chip microcomputer, and the data described to be written that described single-chip microcomputer obtains are carried out buffer memory.
4. the programmer of flash chip in embedded system as claimed in claim 3, is characterized in that, described slave computer also comprises:
Level shifting circuit, described single-chip microcomputer connects described flash chip by described level shifting circuit.
5. the programmer of flash chip in embedded system as described in claim 1 to 4 any one, is characterized in that, described single-chip microcomputer is the single-chip microcomputer that is integrated with the SPI controller, and the SPI interface of described single-chip microcomputer connects the described SPI interface of described flash chip.
6. the programing system of flash chip in an embedded system, is characterized in that, described system comprises:
Host computer;
Slave computer, the SPI interface that it connects described host computer and connect flash chip by serial interface obtains data to be written and by described SPI interface, described data to be written is write described flash chip from described host computer via described serial interface.
7. the programing system of flash chip in embedded system as claimed in claim 6, is characterized in that, described slave computer comprises:
One single-chip microcomputer, SPI interface that it connects described host computer and connect described flash chip by described serial interface obtains described data to be written and by described SPI interface, described data to be written is write described flash chip from described host computer via described serial interface.
8. the programing system of flash chip in embedded system as claimed in claim 7, is characterized in that, described slave computer also comprises:
One random access memory, it connects described single-chip microcomputer, and the data described to be written that described single-chip microcomputer obtains are carried out buffer memory.
9. the programing system of flash chip in embedded system as claimed in claim 8, is characterized in that, described slave computer also comprises:
Level shifting circuit, described single-chip microcomputer connects described flash chip by described level shifting circuit.
10. the programing system of flash chip in embedded system as described in claim 6 to 9 any one, is characterized in that, described single-chip microcomputer is the single-chip microcomputer that is integrated with the SPI controller, and the SPI interface of described single-chip microcomputer connects the described SPI interface of described flash chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220578124 CN202956753U (en) | 2012-11-05 | 2012-11-05 | Programming device and programming system of flash memory chip in embedded system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220578124 CN202956753U (en) | 2012-11-05 | 2012-11-05 | Programming device and programming system of flash memory chip in embedded system |
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| CN202956753U true CN202956753U (en) | 2013-05-29 |
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| CN 201220578124 Expired - Fee Related CN202956753U (en) | 2012-11-05 | 2012-11-05 | Programming device and programming system of flash memory chip in embedded system |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104063249A (en) * | 2014-06-30 | 2014-09-24 | 南通国芯微电子有限公司 | Off-line downloading device for program and downloading method thereof |
| CN104679569A (en) * | 2015-03-20 | 2015-06-03 | 南通国芯微电子有限公司 | Programming method |
| CN104679559A (en) * | 2015-02-11 | 2015-06-03 | 北京配天技术有限公司 | Single chip microcomputer on-line programming method |
| CN105630541A (en) * | 2015-12-18 | 2016-06-01 | 杭州士兰微电子股份有限公司 | Programmer and programming method thereof |
| CN108021385A (en) * | 2017-12-29 | 2018-05-11 | 北京神州龙芯集成电路设计有限公司 | A kind of programming system and method for onboard SPI Flash |
| CN109614118A (en) * | 2018-11-23 | 2019-04-12 | 信利光电股份有限公司 | A kind of SPI Flash firmware burning method and device |
| CN109710277A (en) * | 2018-12-21 | 2019-05-03 | 深圳开阳电子股份有限公司 | A kind of programming method and system of onboard SPI flash storage |
| CN110413550A (en) * | 2018-04-27 | 2019-11-05 | 北京天诚同创电气有限公司 | A kind of chip serial ports program downloading control circuit |
| CN111078261A (en) * | 2019-11-13 | 2020-04-28 | 汉纳森（厦门）数据股份有限公司 | Flash memory upgrading device and vehicle |
| CN112214428A (en) * | 2020-10-26 | 2021-01-12 | 中国兵器工业集团第二一四研究所苏州研发中心 | Control method of embedded flash memory |
| CN113037516A (en) * | 2021-04-06 | 2021-06-25 | 北京集创北方科技股份有限公司 | Communication method, device and system |
| CN116259347A (en) * | 2023-05-16 | 2023-06-13 | 上海灵动微电子股份有限公司 | Programming device of embedded flash memory based on SPI protocol |
-
2012
- 2012-11-05 CN CN 201220578124 patent/CN202956753U/en not_active Expired - Fee Related
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104063249A (en) * | 2014-06-30 | 2014-09-24 | 南通国芯微电子有限公司 | Off-line downloading device for program and downloading method thereof |
| CN104679559B (en) * | 2015-02-11 | 2019-06-18 | 北京配天技术有限公司 | The method of single-chip microcontroller online programming |
| CN104679559A (en) * | 2015-02-11 | 2015-06-03 | 北京配天技术有限公司 | Single chip microcomputer on-line programming method |
| CN104679569A (en) * | 2015-03-20 | 2015-06-03 | 南通国芯微电子有限公司 | Programming method |
| CN105630541A (en) * | 2015-12-18 | 2016-06-01 | 杭州士兰微电子股份有限公司 | Programmer and programming method thereof |
| CN105630541B (en) * | 2015-12-18 | 2019-12-10 | 杭州士兰微电子股份有限公司 | Programmer and programming method thereof |
| CN108021385A (en) * | 2017-12-29 | 2018-05-11 | 北京神州龙芯集成电路设计有限公司 | A kind of programming system and method for onboard SPI Flash |
| CN110413550A (en) * | 2018-04-27 | 2019-11-05 | 北京天诚同创电气有限公司 | A kind of chip serial ports program downloading control circuit |
| CN109614118A (en) * | 2018-11-23 | 2019-04-12 | 信利光电股份有限公司 | A kind of SPI Flash firmware burning method and device |
| CN109614118B (en) * | 2018-11-23 | 2022-05-06 | 信利光电股份有限公司 | SPI Flash firmware burning method and device |
| CN109710277A (en) * | 2018-12-21 | 2019-05-03 | 深圳开阳电子股份有限公司 | A kind of programming method and system of onboard SPI flash storage |
| CN109710277B (en) * | 2018-12-21 | 2022-04-01 | 深圳开阳电子股份有限公司 | Burning method and system for onboard SPI Flash memory |
| CN111078261A (en) * | 2019-11-13 | 2020-04-28 | 汉纳森（厦门）数据股份有限公司 | Flash memory upgrading device and vehicle |
| CN112214428A (en) * | 2020-10-26 | 2021-01-12 | 中国兵器工业集团第二一四研究所苏州研发中心 | Control method of embedded flash memory |
| CN113037516A (en) * | 2021-04-06 | 2021-06-25 | 北京集创北方科技股份有限公司 | Communication method, device and system |
| CN113037516B (en) * | 2021-04-06 | 2022-07-22 | 北京集创北方科技股份有限公司 | Communication method, device and system |
| CN116259347A (en) * | 2023-05-16 | 2023-06-13 | 上海灵动微电子股份有限公司 | Programming device of embedded flash memory based on SPI protocol |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130529 Termination date: 20171105 |