CN113377450A - Remote loading system based on FPGA and downloading configuration method thereof - Google Patents

Abstract

The invention discloses a remote loading system based on an FPGA and a downloading configuration method thereof, wherein the remote loading system comprises a PC, the FPGA, a DDR and a FLASH, and the FPGA is respectively communicated with the PC, the DDR and the FLAASH for mutual data interaction; the FPGA comprises a UDP _ ctrl module, a DDR _ ctrl module, a FLASH _ ctrl module and an ICAP _ ctrl module. When downloading and configuring a loading system, firstly, packaging a bit stream file generated by engineering into a bin file; then writing the bin file data into the FPGA through an Ethernet UDP protocol, writing the data into the DDR through the FPGA, and performing data caching on the DDR; then, the FPGA reads out the configuration data in the DDR and writes the configuration data into the FLASH, and the FLASH is erased before the configuration data is written; and finally, the FPGA actively reads the configuration data in the FLASH through the ICAP primitive to complete the reconfiguration of the FPGA.

Description

Remote loading system based on FPGA and downloading configuration method thereof

Technical Field

The invention belongs to the field of communication, and particularly relates to a remote loading system based on an FPGA and a downloading configuration method thereof.

Background

The current configuration modes of the FPGA can be divided into three types: active configuration, passive configuration, and JTAG configuration. In general, JTAG is commonly used to update FPGA configuration, because JTAG configuration is very fast and convenient, and the integrated design tools of large vendors provide corresponding JTAG configuration channels. However, JTAG configuration is only a configuration method generally used in a debugging stage, and is not suitable for application to a corresponding product after the FPGA engineering verification is finished, because many products do not provide a JTAG interface due to the bulkiness of the JTAG interface, the requirement of product packaging, and the like when being released, a remote loading scheme is an inevitable choice for these products.

Abandoning the JTAG configuration mode, and enabling a user to select an active configuration mode and a passive configuration mode, wherein the two modes are realized without separating an off-chip memory, and the active mode refers to reading configuration of the off-chip memory from an FPGA (field programmable gate array) actively; passive configuration typically implements FPGA configuration by a coprocessor writing configuration data in off-chip memory to the FPGA. In the two configuration methods, passive configuration requires the participation of a coprocessor, and is more complex and costly in hardware architecture, while active configuration does not require more changes to the hardware architecture, which is easy to implement and low in cost.

Object of the Invention

The invention aims to solve the problems of heavy products, complex architecture and high cost in the prior art, and provides a remote loading system based on an FPGA and a configuration method thereof.

Disclosure of Invention

According to one aspect of the invention, the invention provides a remote loading system based on an FPGA, which comprises a PC, the FPGA, a DDR and a FLASH, wherein the FPGA is respectively communicated with the PC, the DDR and the FLAASH for mutual data interaction; the mutual communication between the PC and the FPGA realizes that the configuration file is downloaded to the FPGA by the PC, and the communication mode is one of Ethernet, PCIE, USB and optical fiber; the mutual communication between the FPGA and the DDR realizes the data caching of the configuration file; the interactive communication between the FPGA and the FLASH comprises two processes: (1) the FPGA solidifies the configuration data to the FLASH; (2) the FPGA reads the configuration data in the FLASH through ICAP primitives, so that the reconfiguration of the FPGA is realized;

the FPGA comprises a UDP _ ctrl module, a DDR _ ctrl module, a FLASH _ ctrl module and an ICAP _ ctrl module; the UDP _ ctrl module is responsible for communicating with an upper computer at the PC end, and the UDP protocol is adopted for communication, and FPGA configuration data and related configuration commands are analyzed according to datagram definitions; the DDR _ ctrl module is responsible for communicating with the DDR, and controls the read-write of the DDR; the FLASH _ ctrl module is responsible for communicating with FLASH and controlling erasing, downloading and checking of FLASH; the ICAP _ ctrl module is responsible for controlling ICAP primitives, an IPROG instruction sequence is sent to the ICAP through a state machine, and configuration data of a specified address is automatically loaded after the ICAP primitives receive the IPROG instruction sequence, so that the reconfiguration of the FPGA is realized.

Preferably, the DDR _ ctrl module uses a MIG core of a xilinx DDR controller, and the controlling read and write of DDR is to control read and write of the MIG core.

According to another aspect of the present invention, a configuration method of the remote loading system of the FPGA is provided, which includes the following steps:

step 1, encapsulating the bit stream file generated by the engineering into a bin file, wherein the bin file can be solidified into FLASH; the packaging uses a packaging approach provided by vivado or self-writes a script program according to a script file provided by xilinx;

step 2, writing the bin file data into the FPGA through an Ethernet UDP protocol, writing the data into the DDR through the FPGA, and caching the data in the DDR;

step 3, the FPGA reads out the configuration data in the DDR and writes the configuration data into FLASH, and FLASH erasing operation is required to be carried out before the configuration data is written into the FLASH;

step 4, the FPGA actively reads the configuration data in the FLASH through ICAP primitives to complete the reconfiguration of the FPGA; the selection of the use of the ICAP primitive is obtained by referring to a data manual.

Drawings

Fig. 1 is a framework diagram of the FPGA-based remote loading system according to the present invention.

Detailed Description

The invention is explained in detail below with reference to the drawings. It should be noted that the detailed description is given for illustrative purposes only and should not be taken as limiting the scope of the present invention, and it will be apparent to those skilled in the art that variations and modifications can be made without departing from the spirit of the invention.

Fig. 1 is a framework diagram of the FPGA-based remote loading system according to the present invention. The remote loading system based on the FPGA comprises a PC, the FPGA, a DDR and a FLASH, wherein the FPGA is respectively communicated with the PC, the DDR and the FLAASH for data interaction; each hardware data interaction can be divided into the following processes:

the PC communicates with the FPGA, mainly realizes that the configuration file is downloaded to the FPGA from the PC, the communication mode can be Ethernet, PCIE, USB, optical fiber and the like, and the embodiment takes the communication of an Ethernet UDP protocol as an example.

The FPGA is communicated with the DDR, the FPGA and the DDR are mainly used for realizing data caching of the configuration files, the configuration files of the FPGA are generally large after format conversion processing, and the FPGA is not suitable for caching large data volume due to limited RAM resources, so the DDR is used for caching the data.

The FPGA is communicated with the FLASH, the FPGA and the FLASH are communicated into two processes, one process is that the FPGA solidifies the configuration data to the FLASH, and the other process is that the FPGA reads the configuration data in the FLASH through ICAP primitives, so that the reconfiguration of the FPGA is realized.

The FPGA comprises a UDP _ ctrl module, a DDR _ ctrl module, a FLASH _ ctrl module and an ICAP _ ctrl module, the four modules are divided into work to make the FPGA functional frame clear, and the functions of the modules are as follows:

(1) UDP _ ctrl module

The module is completely responsible for communication with an upper computer at a PC end, the functional content of the module is mainly UDP protocol communication, and FPGA configuration data and related configuration commands are analyzed according to datagram definitions.

(2) DDR _ ctrl module

The module is completely responsible for communication with DDR, the functional content of the module is read-write control of DDR, the module instantiates a MIG core of a xilinx DDR controller, and therefore the logical content is actually read-write control of the MIG core.

(3) FLASH _ ctrl module

The module is completely responsible for communication with FLASH, and the functional content of the module is erasing, downloading and checking of FLASH.

(4) ICAP _ ctrl module

The module is responsible for controlling ICAP primitive, the module sends IPROG instruction sequence to ICAP through a state machine, and the ICAP primitive automatically loads configuration data of a specified address after receiving the sequence, thereby realizing the reconfiguration of FPGA. The content details of the IPROG instruction sequence can be viewed in a related data manual.

The download configuration method of the FPGA remote loading system comprises the following steps:

step 1, encapsulating the bit stream file generated by the engineering into a bin file, wherein the bin file can be solidified into FLASH; the packaging uses a packaging approach provided by vivado or self-writes a script program according to a script file provided by xilinx;

step 2, writing the bin file data into the FPGA through an Ethernet UDP protocol, writing the data into the DDR through the FPGA, and caching the data in the DDR;

step 3, the FPGA reads out the configuration data in the DDR and writes the configuration data into FLASH, and FLASH erasing operation is required to be carried out before the configuration data is written into the FLASH;

step 4, the FPGA actively reads the configuration data in the FLASH through ICAP primitives to complete the reconfiguration of the FPGA; the selection of the use of the ICAP primitive is obtained by referring to a data manual.

In summary, the download configuration of the remote loading system of the present invention completely breaks away from the JTAG interface, which can simplify the cumbersome interface reservation when the product is online, and unlike other schemes requiring the participation of the coprocessor, the remote loading system of the present invention has a simple structure, and can realize the remote loading of the FPGA chip configuration without changing the complexity of the hardware structure. The invention develops description around ICAP primitives in FLASH and XilinxFPGA, and the main idea is that the configuration file of FPGA is downloaded to FPGA by PC, then is cached by DDR, is written into FLASH under the control of FPGA, and finally realizes the on-line reconfiguration of FPGA by ICAP primitives, thereby completing the remote loading process of FPGA.

Claims (3)

1. A remote loading system based on FPGA is characterized by comprising: PC, FPGA, DDR and FLASH;

the FPGA is communicated with a PC, a DDR and a FlaSH to exchange data with each other respectively;

the mutual communication between the PC and the FPGA realizes that the configuration file is downloaded to the FPGA by the PC, and the communication mode is one of Ethernet, PCIE, USB and optical fiber;

the mutual communication between the FPGA and the DDR realizes the data caching of the configuration file;

the interactive communication between the FPGA and the FLASH comprises two processes: (1) the FPGA solidifies the configuration data to the FLASH; (2) the FPGA reads the configuration data in the FLASH through ICAP primitives, so that the reconfiguration of the FPGA is realized;

the FPGA comprises a UDP _ ctrl module, a DDR _ ctrl module, a FLASH _ ctrl module and an ICAP _ ctrl module;

the UDP _ ctrl module is responsible for communicating with an upper computer at a PC end, and the UDP protocol is adopted for communication, and FPGA configuration data and related configuration commands are analyzed according to datagram definitions;

the DDR _ ctrl module is responsible for communicating with the DDR, and controls the read-write of the DDR;

the FLASH _ ctrl module is responsible for communicating with FLASH and controlling erasing, downloading and checking of FLASH;

the ICAP _ ctrl module is responsible for controlling ICAP primitives, an IPROG instruction sequence is sent to the ICAP through a state machine, and configuration data of a specified address is automatically loaded after the ICAP primitives receive the IPROG instruction sequence, so that the reconfiguration of the FPGA is realized.

2. The remote loading system according to claim 1, wherein the DDR _ ctrl module employs a xilinx MIG core of a DDR controller, and the controlling read and write of DDR is to control read and write of the MIG core.

3. The download configuration method of the remote loading system according to any of claims 1-2, comprising the steps of:

step 1, encapsulating the bit stream file generated by the engineering into a bin file, wherein the bin file can be solidified into FLASH; the packaging uses a packaging approach provided by vivado or self-writes a script program according to a script file provided by xilinx;

step 2, writing the bin file data into the FPGA through an Ethernet UDP protocol, writing the data into the DDR through the FPGA, and caching the data in the DDR;

step 3, the FPGA reads out the configuration data in the DDR and writes the configuration data into FLASH, and FLASH erasing operation is required to be carried out before the configuration data is written into the FLASH;

step 4, the FPGA actively reads the configuration data in the FLASH through ICAP primitives to complete the reconfiguration of the FPGA; the selection of the use of the ICAP primitive is obtained by referring to a data manual.

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