WO2021164170A1

WO2021164170A1 - Multi-path high-speed protocol interface dynamic reconfiguration system and implementation method therefor

Info

Publication number: WO2021164170A1
Application number: PCT/CN2020/098652
Authority: WO
Inventors: 王培培; 滕达; 张明瑞; 牛晓威; 王果山
Original assignee: 山东超越数控电子股份有限公司
Priority date: 2020-02-21
Filing date: 2020-06-29
Publication date: 2021-08-26
Also published as: CN111274183A

Abstract

In light of the fact that high-speed protocol interfaces commonly used in fields such as current communication systems, radar systems, general purpose computer systems and storage systems are not sufficiently uniform, the present invention provides a multi-path high-speed protocol interface dynamic reconfiguration system and an implementation method therefor, which mainly solve the problem that a same interface may be configured into various high-speed protocol interfaces. The system comprises a reconfiguration control module, a high-speed protocol interface dynamic reconfiguration module, a non-volatile memory and a system main machine. The reconfiguration control module receives a remote or local reconfiguration command, reads a configuration file corresponding to the reconfiguration command, and transmits to the high-speed protocol interface dynamic reconfiguration module. The high-speed protocol interface dynamic reconfiguration module receives the configuration file sent by the reconfiguration control module, completes a reconfiguration operation, and reconfigures a protocol type of a high-speed interface. The non-volatile memory is used for caching important data in an intermediate state before the reconfiguration. The system main machine is connected to the high-speed protocol interface dynamic reconfiguration module via the high-speed interface.

Description

Multi-channel high-speed protocol interface dynamic reconfigurable system and realization method

Technical field

The invention relates to a multi-channel high-speed protocol interface dynamic reconfigurable system and implementation method, belonging to the field of FPGA dynamic reconfigurable technology.

Background technique

With the development of science and technology, the amount of data generated is increasing exponentially, and the use of high-speed interfaces is becoming more and more common. However, there are many standard high-speed interfaces on the market, and the main high-speed protocol interfaces used in various fields are not unified enough, such as the common network protocol for high-speed interfaces in communication systems, the SRIO protocol for high-speed interfaces in radar systems, and the PCIe protocol for high-speed interfaces in general computer systems. , And high-speed interfaces of mass storage devices often use PCIe protocol and NVMe protocol.

Summary of the invention

Aiming at the situation that the commonly used high-speed protocol interfaces in the current communication systems, radar systems, general-purpose computer systems, storage systems and other fields are not uniform enough, the present invention provides a multi-channel high-speed protocol interface dynamic reconfigurable system and implementation method.

In order to achieve the above objectives, the present invention is achieved through the following technical solutions:

A multi-channel high-speed protocol interface dynamic reconfigurable system, including a reconfiguration control module, a high-speed protocol interface dynamic reconfigurable module, a non-volatile memory and a system host, in which:

The reconstruction control module receives the external reconstruction command, reads the configuration file corresponding to the reconstruction command, and transmits it to the high-speed protocol interface dynamic reconfigurable module;

The high-speed protocol interface dynamically reconfigurable module receives the configuration file sent by the reconfiguration control module to complete its own reconfiguration work; non-volatile memory is used to cache important data in the intermediate state before reconfiguration;

The system host is connected to the dynamic reconfigurable module through the high-speed interface and the high-speed protocol interface, and is connected to the configuration file storage through the network to upgrade the local configuration file online.

Based on the above-mentioned multi-channel high-speed protocol interface dynamic reconfigurable system, the high-speed protocol interface dynamic reconfigurable module is an FPGA chip, including a high-speed protocol interface analysis module, a data processing module and a SelectMAP interface. The SelectMAP interface is connected to the reconstruction control module and data processing The module realizes the data transmission and processing functions of the high-speed protocol interface dynamically reconfigurable module. The high-speed protocol interface analysis module includes SRIO analysis module, PCIe analysis module and NVMe analysis module.

Based on the above-mentioned multi-channel high-speed protocol interface dynamic reconfigurable system, the reconstruction control module is an FPGA chip, including configure FSM module, network analysis module, reconstruction command control module and local serial port command analysis module. The system host inputs the reconstruction command The reconstruction instruction control module analyzes and outputs the reconstruction instruction data through the network analysis module. The reconstruction instruction module performs instruction identification, and completes the corresponding reconstruction work according to the corresponding instruction. The configure FSM module writes the corresponding configuration file in the configuration file memory Enter the high-speed protocol interface dynamic reconfigurable module; the serial port command outputs the reconstruction instruction through the local serial port command parsing module, specifies it to read the corresponding configuration file in the configuration file memory, and transmits it to the high-speed protocol interface dynamic reconfigurable module through the SelectMAP interface.

A method for dynamically reconfigurable multi-channel high-speed protocol interface includes the following steps:

S1. The board is in normal working condition;

S2. Waiting to receive the local serial port control reconstruction command or the network signal reconstruction command of the system host;

S3. After receiving the reconstruction command, the reconstruction control module parses the reconstruction command;

S4. Send a stop working instruction to the high-speed protocol dynamic reconfigurable module, and the high-speed protocol dynamic reconfigurable module stops working and packs the current important data;

S5. The packaged important data is cached to the non-volatile memory;

S6. Confirm whether the data caching is completed, if it is completed, proceed to step S7, if it is not completed, proceed to step S5;

S7. The reconstruction control module reads the configuration file and transmits it to the high-speed protocol dynamic reconfigurable module;

S8. Confirm whether the reconstruction is completed, if it is completed, proceed to step S9, if it is not completed, proceed to step S7;

S9. The high-speed interface link re-establishes the connection;

S10. Confirm whether the high-speed interface establishes a connection;

S11. If the connection is established, step S1 to step S10 are executed again, and if the connection is not established, step S9 is executed.

The advantages of the present invention are: the present invention can realize the dynamic reconfiguration of multiple high-speed protocol interfaces under different application scenarios, and effectively solves the time-sharing multiplexing problems of multiple high-speed protocol interfaces, online upgrade of configuration file versions, and real-time fault maintenance. Problems, etc., achieved the effect of "one machine with multiple uses", increased the flexibility of the storage device, greatly reduced the resource overhead of the FPGA, and lowered the material cost of the device.

Description of the drawings

The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention, and do not constitute a limitation to the present invention.

Fig. 1 is a schematic diagram of a dynamic reconfigurable system for multiple high-speed protocol interfaces of the present invention.

Figure 2 is a classification diagram of FPGA reconfigurable technology.

Figure 3 is the implementation block diagram of the slave selectMap configuration module.

Figure 4 is the implementation diagram of the configure module.

Figure 5 is a block diagram of the remote control reconstruction mode.

Figure 6 Block diagram of local control reconstruction mode implementation.

Figure 7 is a block diagram of the realization method of dynamic reconfigurable multi-channel high-speed protocol interface.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

Referring to Figure 1, a multi-channel high-speed protocol interface dynamic reconfigurable system, including a reconfiguration control module, a high-speed protocol interface dynamic reconfigurable module, a non-volatile memory, and a system host, in which:

The reconstruction control module receives the external reconstruction command, reads the configuration file corresponding to the reconstruction command, and transmits it to the high-speed protocol interface dynamic reconfigurable module to assist in the completion of the reconstruction work, and can also upgrade the version of the configuration file online;

In this embodiment, the reconfiguration control module and the high-speed protocol interface dynamic reconfigurable module are all implemented by the FPGA chip. At present, FPGA mainly has three programming techniques: based on SRAM structure, based on Flash structure, and based on antifuse structure. Among them, the FPGA based on the SRAM structure should write the configuration data into its on-chip random access memory (RAM) when it is initialized and powered on. After the initial configuration of the FPGA is completed, it can start to work normally, but when the FPGA is powered off, it is stored in the on-chip RAM The configuration data in will be lost immediately. The FPGA based on the SRAM structure supports repeated programming, which is the basis for realizing reconfigurable technology. The FPGA based on the SRAM structure supports repeated programming, and the erasing speed is fast. Therefore, the FPGA reconfigurable technologies involved in the present invention are all carried out for FPGAs based on the SRAM structure.

As shown in Figure 2, the reconfigurable technology of FPGA is divided into static reconstruction and dynamic reconstruction. According to the different reconstruction area, dynamic reconstruction can be divided into dynamic global reconstruction and dynamic local reconstruction. The main object that needs to be reconfigurable in the present invention is the high-speed interface analysis module. The high-speed interface analysis module mainly includes the physical layer, link layer, protocol layer, etc. The physical layer uses FPGA hardware structure high-speed serial controller (Tranceiver), only It can be dynamically configured and cannot be defined by software, nor can it be reconfigured dynamically. The link layer and protocol layer are defined by software and can be dynamically reconfigured. Because the physical layer and the link layer and the protocol layer are in close proximity during the layout of the internal units of the FPGA, and the shortest path can realize the high-speed transmission of the high-speed protocol, it is difficult to divide the local reconfigurable area. The present invention proposes a software-defined global dynamic reconfigurable mode, that is, before reconfiguration, the configuration files supporting various high-speed protocols are stored in the peripheral configuration file memory. When the reconfiguration command is received, the reconfiguration control module will The corresponding configuration file is unloaded to the high-speed protocol dynamic reconfigurable module to complete the reconfiguration of the high-speed storage interface.

Table 1 Configuration bandwidth of FPGA configuration mode

Table 1 shows the configuration bandwidth of the FPGA configuration mode. The same configuration file uses different configuration methods, and the configuration time is very different. Among them, the Slave SelectMAP configuration interface provides 8-bit, 16-bit, and 32-bit bidirectional data bus interfaces, which can be used to configure and read back the FPGA. The fastest SelectMAP configuration clock is 100MHz. If the data width is 32 bits, the maximum bandwidth is 3.2Gb/s, and it supports data compression and supports the dynamic reconstruction function of parallel configuration. Therefore, the present invention selects the Slave SelectMAP configuration mode as reconstruction FPGA configuration mode.

The high-speed protocol interface dynamic reconfigurable module is an FPGA chip, including the high-speed protocol interface analysis module, data processing module and SelectMAP interface. The SelectMAP interface is connected to the reconstruction control module. The data processing module realizes the data transmission and data transmission of the high-speed protocol interface dynamic reconfigurable module Processing function, high-speed protocol interface analysis module includes SRIO analysis module, PCIe analysis module and NVMe analysis module and other high-speed protocol analysis modules, which effectively solves the problem of time-sharing multiplexing of high-speed protocols such as SRIO, PCIe, NVMe, and online upgrade of configuration file versions , Real-time fault maintenance issues, etc., to achieve the effect of "one machine with multiple uses", increase the flexibility of storage devices, greatly reduce FPGA resource overhead, and reduce the material cost of storage devices.

The reconstruction control module includes the configure FSM module, the network analysis module, the reconstruction command control module and the local serial command analysis module. The system host inputs the reconstruction command to the reconstruction command control module, and analyzes and outputs the reconstruction command data through the network analysis module. The configuration instruction module performs instruction recognition, and completes the corresponding reconstruction work according to the corresponding instruction. The configure FSM module writes the corresponding configuration file in the configuration file memory to the dynamic reconfigurable module of the high-speed protocol interface; the serial port command passes through the local serial port command analysis module Output the number of reconstruction instructions, specify it to read the corresponding configuration file in the configuration file memory, and transmit it to the high-speed protocol interface dynamic reconfigurable module through the SelectMAP interface. Figure 3 is the connection diagram of the reconfiguration control module for power-on configuration and version update of the high-speed protocol dynamic reconfigurable module through the slave selectMap interface. The high-speed protocol dynamic reconfigurable module is the slave device, and the configuration logic is controlled by the reconfiguration The module is complete. The specific implementation process is: the reconstruction control module receives local or remote reconstruction instructions, reads the configuration file from the corresponding location of the configuration file memory, and implements the configuration of the dynamic reconfigurable module through the slaveSelectMAP interface. The specific operation steps are shown in Figure 4.

Two reconfiguration control modes are proposed in the present invention, which are divided into a local control mode and a remote control mode. The remote reconfiguration mode can also realize the online upgrade function of the configuration file version.

Figure 5 shows the block diagram of the remote control reconstruction mode. The system host can realize the remote reconstruction control of the reconstruction control module and the online upgrade of the configuration file through the Gigabit Ethernet interface. The system host sends the reconstruction command or the updated version of the configuration file to the reconstruction control module through the Gigabit Ethernet. The network parses the command, that is, SGMII IP core analysis, outputs the reconstruction instruction data, and then passes the reconstruction instruction control module for instruction recognition , According to the corresponding instructions, complete the corresponding reconstruction work. When it is a reconstruction command, start the Configure FSM module, write the corresponding configuration file in the configuration file memory into the dynamic reconfigurable hardware acceleration controller, and reconstruct the high-speed interface protocol. When it is a new version of the configuration file, it is written into the corresponding address in the configuration file storage to replace the previous version of the file. By remotely controlling the reconstruction mode, the high-speed interface protocol can be reconstructed in real time, and the version of the configuration file can be upgraded online, which is an effective method to realize safe fault maintenance.

Figure 6 shows the block diagram of the local control reconstruction mode. Under the condition that the system host does not have custom software to remotely control the reconfiguration command, the local control mode can be used to realize the reconfiguration of the high-speed interface. The local operation can be completed through the serial port, through the serial port command, specify it to read the corresponding configuration file in the configuration file memory, and transmit it to the reconfigurable high-speed protocol controller through the SelectMAP interface.

When performing global dynamic reconstruction, load the global bitstream configuration file of a specific high-speed interface into the dynamic reconfigurable hardware acceleration controller. All logic of the FPGA logic resources before reconstruction is erased, so some status indications and calculations Important data such as the intermediate results of the software need to be saved in a certain storage area before reconstruction.

In summary, the reconstruction control module of the present invention can accept the local serial port control reconstruction command or the network signal reconstruction command of the system host, and write the corresponding configuration file in the configuration file memory into the high-speed interface dynamic reconfigurable module. Realize the reconfigurable function of high-speed interface. The system host can upgrade the local configuration file online through the network port to realize the software version upgrade and fault maintenance functions. The non-volatile memory caches the state and intermediate results before the reconfiguration configuration, so that the system can perform data backup for multiple reconfiguration tasks and facilitate the system to perform redundant upgrades.

Referring to Fig. 7, a method for dynamically reconfigurable multi-channel high-speed protocol interface includes the following steps:

S1. The board is in normal working condition;

S5. The packaged important data is cached to the non-volatile memory;

S9. The high-speed interface link re-establishes the connection;

S10. Confirm whether the high-speed interface establishes a connection;

Finally, it should be noted that the above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, it is still for those skilled in the art. The technical solutions described in the foregoing embodiments may be modified, or some of the technical features may be equivalently replaced. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

A multi-channel high-speed protocol interface dynamic reconfigurable system, which is characterized in that it includes a reconfiguration control module, a high-speed protocol interface dynamic reconfigurable module, a non-volatile memory and a system host, wherein:

The reconstruction control module receives the external reconstruction command, reads the configuration file corresponding to the reconstruction command, and transmits it to the high-speed protocol interface dynamic reconfigurable module;

The high-speed protocol interface dynamically reconfigurable module receives the configuration file sent by the reconstruction control module, completes its own reconstruction work, and reconfigures the protocol type of the high-speed interface;

Non-volatile memory, used to cache important data in the intermediate state before reconstruction;

The system host is connected to the dynamic reconfigurable module through the high-speed interface and the high-speed protocol interface, and is connected to the configuration file storage through the network to upgrade the local configuration file online.
The multi-channel high-speed protocol interface dynamic reconfigurable system according to claim 1, characterized in that: the high-speed protocol interface dynamic reconfigurable module is an FPGA chip, including a high-speed protocol interface analysis module, a data processing module and a SelectMAP interface, and the SelectMAP interface is connected The reconfiguration control module, the data processing module realizes the data transmission and processing functions of the high-speed protocol interface dynamically reconfigurable module. The high-speed protocol interface analysis module includes the SRIO analysis module, the PCIe analysis module and the NVMe analysis module.
The multi-channel high-speed protocol interface dynamic reconfigurable system according to claim 1, wherein the reconfiguration control module is an FPGA chip, including a configure FSM module, a network analysis module, a reconfiguration instruction control module and a local serial port command analysis module, The system host inputs the reconstruction instruction to the reconstruction instruction control module, and analyzes the reconstruction instruction data through the network analysis module. The reconstruction instruction module performs instruction recognition, and completes the corresponding reconstruction work according to the corresponding instruction. The configure FSM module configures the file The corresponding configuration file in the memory is written into the dynamic reconfigurable module of the high-speed protocol interface; the serial port command outputs the reconstruction instruction through the local serial port command parsing module, specifies it to read the corresponding configuration file in the configuration file memory, and transmits it to the high-speed protocol through the SelectMAP interface Dynamically reconfigurable interface module.
A method for dynamically reconfigurable multi-channel high-speed protocol interface is characterized in that it comprises the following steps:

S1. The board is in normal working condition;

S2. Waiting to receive the local serial port control reconstruction command or the network signal reconstruction command of the system host;

S3. After receiving the reconstruction command, the reconstruction control module parses the reconstruction command;

S4. Send a stop working instruction to the high-speed protocol dynamic reconfigurable module, and the high-speed protocol dynamic reconfigurable module stops working and packs the current important data;

S5. The packaged important data is cached to the non-volatile memory;

S6. Confirm whether the data caching is completed, if it is completed, proceed to step S7, if it is not completed, proceed to step S5;

S7. The reconstruction control module reads the configuration file and transmits it to the high-speed protocol dynamic reconfigurable module;

S8. Confirm whether the reconstruction is completed, if it is completed, proceed to step S9, if it is not completed, proceed to step S7;

S9. The high-speed interface link re-establishes the connection;

S10. Confirm whether the high-speed interface establishes a connection;

S11. If the connection is established, step S1 to step S10 are executed again, and if the connection is not established, step S9 is executed.