CN112000360A

CN112000360A - FPGA (field programmable Gate array) online upgrading method based on dynamic local reconstruction

Info

Publication number: CN112000360A
Application number: CN202010863401.5A
Authority: CN
Inventors: 张明瑞; 王培培; 吴之光; 牛晓威
Original assignee: Shandong Chaoyue CNC Electronics Co Ltd
Current assignee: Shandong Chaoyue CNC Electronics Co Ltd
Priority date: 2020-08-25
Filing date: 2020-08-25
Publication date: 2020-11-27

Abstract

The invention particularly relates to an FPGA (field programmable gate array) online upgrading method based on dynamic local reconstruction. According to the FPGA online upgrading method based on dynamic local reconstruction, a system host is connected with an FPGA chip through an Ethernet interface, a command and a configuration file needing to be upgraded are sent to the FPGA chip, and the FPGA chip carries out protocol analysis on the configuration file and then stores the configuration file into a Flash memory. The FPGA online upgrading method based on dynamic local reconstruction can ensure online real-time updating of the configuration file, and the FPGA can be automatically upgraded online without additionally introducing other control devices, so that the cost is saved, and the overall power consumption of the system is favorably controlled.

Description

FPGA (field programmable Gate array) online upgrading method based on dynamic local reconstruction

Technical Field

The invention relates to the technical field of computer application, in particular to an FPGA (field programmable gate array) online upgrading method based on dynamic local reconstruction.

Background

An FPGA (Field-Programmable Gate Array), i.e. a Field-Programmable Gate Array, is a product of further development on the basis of Programmable devices such as PAL, GAL, CPLD, etc. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.

The FPGA adopts a Logic Cell array (lca) concept, and includes three parts, namely a configurable Logic module clb (configurable Logic block), an input Output module iob (input Output block), and an internal connection (Interconnect). A Field Programmable Gate Array (FPGA) is a programmable device that has a different structure than traditional logic circuits and gate arrays (such as PAL, GAL and CPLD devices). The FPGA utilizes small lookup tables (16 × 1RAM) to realize combinational logic, each lookup table is connected to the input end of a D flip-flop, and the flip-flops drive other logic circuits or drive I/O (input/output) circuits, so that basic logic unit modules capable of realizing both combinational logic functions and sequential logic functions are formed, and the modules are connected with each other or connected to an I/O (input/output) module by utilizing metal connecting wires. The logic of the FPGA is implemented by loading programming data into the internal static memory cells, the values stored in the memory cells determine the logic function of the logic cells and the way of the connections between the modules or between the modules and the I/O and finally the functions that can be implemented by the FPGA, which allows an unlimited number of programming.

With the development of scientific technology, the generated data volume is increased explosively, which puts demands on rapidity and real-time performance for data processing, and the FPGA is widely applied in different application scenes due to the characteristic of data parallel processing.

1) An ASIC circuit (application specific integrated circuit) is designed by adopting FPGA, and a user can obtain a usable chip without sheet production.

2) The FPGA can be used as a master sample for other fully-or semi-custom ASIC circuits.

3) The FPGA is provided with abundant triggers and I/O pins inside.

4) The FPGA is one of the devices with the shortest design period, the lowest development cost and the smallest risk in an ASIC circuit.

5) The FPGA adopts a high-speed CMOS process, has low power consumption and can be compatible with CMOS and TTL levels.

The FPGA chip is one of the best choices for improving the integration level and the reliability of a small-batch system.

The FPGA sets the working state of the FPGA by a program stored in an on-chip RAM, so the on-chip RAM needs to be programmed during working. The user can adopt different programming modes according to different configuration modes.

When the power is on, the FPGA chip reads the data in the EPROM into the on-chip programming RAM, and after the configuration is finished, the FPGA enters a working state. After power failure, the FPGA is recovered to be a white chip, and the internal logic relation disappears, so that the FPGA can be repeatedly used. The programming of the FPGA does not need a special FPGA programmer, and only needs a universal EPROM and a PROM programmer. When the FPGA function needs to be modified, only the data of the EPROM needs to be updated. Thus, different circuit functions can be generated by the same FPGA and different programming data. Thus, the use of FPGAs is very flexible.

The online upgrade refers to that a system host can upgrade the configuration file of the FPGA online through a network port to realize the functions of software version upgrade and fault maintenance. At present, more products with the FPGA cannot realize online upgrade, and the use efficiency of the FPGA is influenced. In addition, most of the common methods for upgrading the FPGA online are to use an ARM, a DSP, or an additional FPGA to control the target FPGA to upgrade the configuration file online, and this method of adding an additional control device not only increases the cost, but also affects the power consumption of the system. How to better realize the online upgrade of the FPGA is a problem to be solved urgently.

Based on the situation, the invention provides an FPGA online upgrading method based on dynamic local reconstruction.

Disclosure of Invention

In order to make up for the defects of the prior art, the invention provides a simple and efficient FPGA online upgrading method based on dynamic local reconstruction.

The invention is realized by the following technical scheme:

an FPGA online upgrading method based on dynamic local reconstruction is characterized in that: the system host is connected with the FPGA chip through an Ethernet interface, a command and a configuration file needing to be upgraded are sent to the FPGA chip, and the FPGA chip carries out protocol analysis on the configuration file and then stores the configuration file into a Flash memory.

The FPGA chip is also connected with a reserved USB interface; when online upgrading can not be carried out through the Ethernet, a storage device of the USB interface is inserted, and the FPGA chip automatically reads the configuration file stored in the storage device and stores the configuration file into the Flash memory after analysis.

The loading mode of the FPGA chip is an active mode (AS); under an active mode (AS), PR (partial reconfiguration) partitioning is carried out on the FPGA chip, and the FPGA chip is divided into a reconfigurable control area and a reconfigurable area.

The reconfigurable area is responsible for realizing the logic function of a system or a product, and the reconfigurable control area receives and analyzes the configuration file.

And loading data to the reconfigurable area through an internal bus macro module of the FPGA chip, and realizing online upgrade of the configuration file by utilizing dynamic reconfiguration.

And the reconfiguration control area stores the configuration file into a Flash memory.

After the FPGA chip is powered off and restarted, the reconstruction control area actively reads data from the Flash memory and issues the configuration file to the reconstruction area.

The utility model provides a FPGA online upgrade structure based on developments local reconstruction which characterized in that: the system comprises an FPGA chip, a system host, a Flash memory and a reserved USB interface, wherein the system host, the Flash memory and the reserved USB interface are all connected with the FPGA chip; the Flash memory is used for storing configuration files needing to be upgraded.

The invention has the beneficial effects that: the FPGA online upgrading method based on dynamic local reconstruction can ensure online real-time updating of the configuration file, and the FPGA can be automatically upgraded online without additionally introducing other control devices, so that the cost is saved, and the overall power consumption of the system is favorably controlled.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of an FPGA online upgrade structure based on dynamic local reconfiguration.

FIG. 2 is a schematic diagram of the FPGA online upgrade method based on dynamic local reconfiguration.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the embodiment of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

According to the FPGA online upgrading method based on dynamic local reconstruction, a system host is connected with an FPGA chip through an Ethernet interface, a command and a configuration file needing to be upgraded are sent to the FPGA chip, and the FPGA chip carries out protocol analysis on the configuration file and then stores the configuration file into a Flash memory.

The loading modes of the FPGA mainly include an active mode (AS), a passive mode (PS), and a JTAG mode.

A commonly used method for upgrading an FPGA online is to set the FPGA to a PS mode, and an external computer or a controller (such as an ARM, a DSP, or an additional FPGA, an enhanced configuration device (EPC16, EPC8), etc.) controls a configuration process to download data into the FPGA, thereby increasing cost and power consumption. With the development of the technology, a method for controlling data configuration by using an FPGA internal soft core to build a microcontroller appears, but the method still belongs to the field of FPGA passive configuration.

The FPGA online upgrading structure based on dynamic local reconstruction comprises an FPGA chip, a system host, a Flash memory and a reserved USB interface, wherein the system host, the Flash memory and the reserved USB interface are all connected with the FPGA chip; the Flash memory is used for storing configuration files needing to be upgraded.

Compared with the prior art, the FPGA online upgrading method based on dynamic local reconstruction has the following characteristics:

first, real-time of online upgrade

And the on-line real-time updating of the configuration file is ensured based on the dynamic local reconstruction of the FPGA.

Secondly, cost saving and power consumption control

The FPGA is automatically upgraded on line, other control devices are not additionally introduced, and the cost is saved while the whole power consumption of the system is favorably controlled.

The above provides a detailed description of an FPGA online upgrade method based on dynamic local reconfiguration in the embodiment of the present invention. While the present invention has been described with reference to specific examples, which are provided to assist in understanding the core concepts of the present invention, it is intended that all other embodiments that can be obtained by those skilled in the art without departing from the spirit of the present invention shall fall within the scope of the present invention.

Claims

1. An FPGA online upgrading method based on dynamic local reconstruction is characterized in that: the system host is connected with the FPGA chip through an Ethernet interface, a command and a configuration file needing to be upgraded are sent to the FPGA chip, and the FPGA chip carries out protocol analysis on the configuration file and then stores the configuration file into a Flash memory.

2. The FPGA online upgrading method based on dynamic local reconstruction as claimed in claim 1, characterized in that: the FPGA chip is also connected with a reserved USB interface; when online upgrading can not be carried out through the Ethernet, a storage device of the USB interface is inserted, and the FPGA chip automatically reads the configuration file stored in the storage device and stores the configuration file into the Flash memory after analysis.

3. The FPGA online upgrading method based on dynamic local reconstruction as claimed in claim 1 or 2, characterized in that: the loading mode of the FPGA chip is an active mode; and in the active mode, PR partition is carried out on the FPGA chip and is divided into a reconfigurable control area and a reconfigurable area.

4. The FPGA online upgrading method based on dynamic local reconstruction as claimed in claim 3, wherein: the reconfigurable area is responsible for realizing the logic function of a system or a product, and the reconfigurable control area receives and analyzes the configuration file.

5. The FPGA online upgrading method based on dynamic local reconstruction as claimed in claim 4, wherein: and loading data to the reconfigurable area through an internal bus macro module of the FPGA chip, and realizing online upgrade of the configuration file by utilizing dynamic reconfiguration.

6. The FPGA online upgrading method based on dynamic local reconstruction as claimed in claim 4 or 5, wherein: and the reconfiguration control area stores the configuration file into a Flash memory.

7. The FPGA online upgrading method based on dynamic local reconstruction as claimed in claim 6, wherein: after the FPGA chip is powered off and restarted, the reconstruction control area actively reads data from the Flash memory and issues the configuration file to the reconstruction area.

8. The utility model provides a FPGA online upgrade structure based on developments local reconstruction which characterized in that: the system comprises an FPGA chip, a system host, a Flash memory and a reserved USB interface, wherein the system host, the Flash memory and the reserved USB interface are all connected with the FPGA chip; the Flash memory is used for storing configuration files needing to be upgraded.