CN205176829U - Multiple communications protocol's of test configuration system on a chip's test system - Google Patents
Multiple communications protocol's of test configuration system on a chip's test system Download PDFInfo
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- CN205176829U CN205176829U CN201320449278.8U CN201320449278U CN205176829U CN 205176829 U CN205176829 U CN 205176829U CN 201320449278 U CN201320449278 U CN 201320449278U CN 205176829 U CN205176829 U CN 205176829U
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Abstract
The utility model discloses a multiple communications protocol's of test configuration system on a chip's test system, test young the card including test vector production board and polylith, each is tested young the card and is connected with test vector production board. The utility model discloses utilize test vector production board and the sub - card of polylith test effectively to solve the not enough problem of chip test equipment peripheral interface resource, be suitable for different kinds of chip testing, can effectual function of testing communication class and class of algorithms chip. Every chip testing card and test vector board can separate, can design according to the practical application demand antithetical phrase card at scene and need not produce the integrated circuit board to the test vector and change, have high flexibility and scalability. Chip testing card and test vector produce and to adopt multiple bus mode to carry out the communication between the integrated circuit board, can carry out communication, the different kinds of chip of while testing multi -disc to polylith card simultaneously. The efficiency of system testing is improved.
Description
Technical field
The utility model belongs to chip design art, is specifically related to a kind of test macro of the multiple configurable communications protocol for System on Chip/SoC.
Background technology
Along with developing rapidly of IC industry, the characteristic dimension of chip is more and more less, and integrated scale is increasing, and the function of realization also becomes increasingly complex, and is widely used in industry-by-industry, becomes a part indispensable in human lives.But with the fast development of chip industry unlike, the development of the method for testing of chip does not obtain due progress along with the lifting of the complexity of chip.In the face of the chip that function constantly increases, framework is day by day complicated, the function how had for chip carries out the problem that comprehensive, correct test has become industry growing interest.The method of testing of traditional chip and proving installation have become the bottleneck place of restriction IC industry development.
Traditional method of testing is mainly according to the function that chip has, adopt single circuit respectively to the test that various functions carries out one by one, test circuit often adopts CPU as test and excitation source, carries out communication, test chip by periphery communication interface and chip under test.This method is often subject to cpu peripheral interface and limits, test is needed when chip under test has multiple kinds interface, and the interface resource of CPU is when can not meet chip testing needs, just need change more senior CPU or increase extra test board, virtually add complexity and the cost of system.
Therefore, need to design a kind of highly versatile, that realize multiple kinds ability, full test can be carried out to difference in functionality chip test vector generation circuit can be had, meet and also there is certain extended capability to the test request of sophisticated functions chip.
Utility model content
For the problem that conventional test methodologies test resource is limited, the utility model provides a kind of chip test system, and this system test configurations can have the test chip of different communications protocol, does not need to change test and excitation source during test, can testing efficiency be improved, reduce testing cost.
The technical solution of the utility model is;
A test macro for the System on Chip/SoC of test configurations multiple kinds, comprise a test vector and produce plate and polylith test subcard, each test subcard produces plate with test vector and is connected.Test vector produces plate and produces test vector, send test vector to test the chip under test that is connected of subcard and receive test result.
Each test subcard and test vector are produced plate and are connected by expansion interface.
Described test vector produces plate and comprises processor, SDRAM, FLASH chip and configurable communications protocol generation module, processor is connected by internal bus with configurable communications protocol generation module, configurable communications protocol generation module is connected with test subcard by multiple communication bus, and SDRAM is connected with processor respectively by internal bus with FLASH chip.Processor sends test command to configurable communications protocol generation module, and configurable communications protocol generation module meets the Packet Generation of corresponding communications protocol to test subcard according to test command generation.SDRAM for the treatment of device Program running space; FLASH is for the treatment of the storage space of device Program.
Described test vector produces plate and also comprises configuring chip, and configuring chip is connected with configurable communications protocol generation module.Configuring chip carries out the configuration of communications protocol.
Described test vector produces on plate and arranges peripheral interface module, and peripheral interface module is connected by multiple communication bus with configurable communications protocol generation module.
Described test vector produces on plate and also arranges clock generating module, and clock generating module is connected with processor.Clock generating module provides major clock and high-speed interface clock to processor.
Described clock generating module has outside SPI interface.Can be programmed to it by outside SPI interface.
Described test vector produces on plate and also arranges power module.For test macro is powered.Power module is independent module, for whole system is powered.
Described configurable communications protocol generation module is a large-scale F PGA.
Described configurable communications protocol generation module comprises clock synchronization module, data store RAM module, protocol configuration module, Logic control module, serioparallel exchange module and communications protocol generation module, protocol configuration module is connected with processor carries out communications protocol configuration according to the test command of processor to data, protocol configuration module is connected with communications protocol generation module, deploy content is sent to communications protocol generation module, communications protocol generation module produces the packet of corresponding communications protocol according to deploy content, communications protocol generation module and serioparallel exchange model calling, by Packet Generation to serioparallel exchange module, serioparallel exchange module is carried out after the conversion of serial data and parallel data to outer transmission packet, clock synchronization module and protocol configuration module, Logic control module, serioparallel exchange module is connected respectively with communications protocol generation module, by each module of Ti Gong Give after external clock, Logic control module for coordinating each module is connected with protocol configuration module and communications protocol generation module, data store RAM module and are connected with communications protocol generation module, the feedback data of memory communicating agreement generation module decoding.
Described test subcard comprises socket and the communication interface circuit of grafting chip under test, and the peripheral interface module that communication interface circuit produces on plate with test vector is connected by communication bus, and communication interface circuit is connected with socket.Test vector produces plate and produces test vector is sent to grafting chip under test socket by communication interface circuit, and chip under test receives and produces feedback.
Described test subcard comprises FPGA or CPLD, FPGA or CPLD is connected with socket and communication interface circuit.Some test vector can be converted to the agreement meeting chip relevant criterion by FPGA or CPLD, or carries out level conversion etc., strengthens the function of test and a series of subsidiary function such as to show test results.
The beneficial effects of the utility model:
The utility model by one can run multiple kinds, configurable test vector produce Circuits System realize, the processor chips or interface chip be mainly used in having different communications protocol are tested, ensure that its communication function is correctly reliable, be particularly useful for the test of the chip simultaneously with multiple kinds.
The utility model utilizes test vector to produce plate and polylith tests the problem that subcard efficiently solves chip testing devices peripheral interface inadequate resource, is suitable for dissimilar chip testing, effectively can tests the function of communication class and class of algorithms chip.
Each chip testing subcard can be separated with test vector plate, can carry out designing according to the practical application request antithetical phrase card at scene and need not produce board to test vector and change, and has dirigibility and the extensibility of height.
Chip testing subcard and test vector produce between board and multiple bus mode can be adopted to carry out communication, can carry out communication to polylith subcard simultaneously, test the dissimilar chip of multi-disc simultaneously.Improve the testing efficiency of system.
Accompanying drawing explanation
Fig. 1 is test macro Organization Chart of the present utility model;
Fig. 2 is that test vector of the present utility model produces plate structure schematic diagram;
Fig. 3 is the configurable communications protocol generation module structural representation in Fig. 2;
Fig. 4 is the test flow chart adopting the utility model to carry out chip testing.
Embodiment
The test macro of test configurations multiple kinds chip of the present utility model, adopts master card-subcard mode to form, namely comprises one piece of motherboard and polylith daughter board, specifically, as shown in Figure 1, tests subcard 2 form by one block of test vector generation plate 1 and polylith.Test vector produces between plate 1 and test subcard 2 and adopts general expansion interface to connect, and connects as adopted XMC standard sockets or PMC standard interface.Wherein test vector produces board 1 as system board, is responsible for the generation of test vector and the collection work of test result; Test subcard 2, as system subcard, receives the test and excitation of motherboard and produces corresponding test response.Test vector produces on plate 1 and test subcard 2 separately independently communication interface circuit, can carry out corresponding communication level conversion.
Test vector produces plate 1 and is responsible for producing test vector according to different chip testing demand, calls corresponding communications protocol and sends test vector and receive test result, and whether the function of inspection chip under test 3 is correct.Every block test subcard 2 all comprises the socket of one or more standard packaging or special package, and this socket customizes according to the pin of chip under test 3, and every block test subcard 2 tests a kind of specific chip.
Respectively test vector generation plate and chip testing subcard will be illustrated respectively below.
(1) test vector produces plate 1
Test vector produces plate 1 and mainly comprises processor, configurable communications protocol generation module, clock generating module, peripheral interface module and power module composition.The block diagram of test vector plate as shown in Figure 2, core component is processor and configurable communications protocol generation module, therebetween internal bus is adopted, such as EMIF bus and SRIO bus carry out data interaction, processor according to chip 3 to be measured treat brake formulate Test Strategy, produce test vector, send to configurable communications protocol generation module in the mode of Frame, be used for being configured communications protocol, sending test command and test vector.Configurable communications protocol generation module receives the packet that processor sends, and packet is carried out decoding process, according to the corresponding communication protocol control of the content configuration of packet, test vector is sent to test subcard 2 by peripheral interface module.When testing subcard 2 and returning test data, configurable communications protocol generation module is to this decoding data, and by the test data that obtains stored in internal RAM, and produce an interruption to processor, notification processor takes data away.The mode such as EMIF bus, I2C, SPI and SRIO is adopted to carry out communication between processor and configurable communications protocol generation module, processor is configured configurable communications protocol generation module, determines which kind of communications protocol FPGA adopts carry out data interaction with test subcard.The test data conversion that processor is sent by configurable communications protocol generation module is the packet meeting corresponding communications protocol, send it to chip under test 3 and also receive the test data returned, leave in after decoding in internal RAM, read for processor and compare, obtain test result.
Configurable communications protocol generation module is connected with peripheral interface module, externally data are sent by this module, the data interaction of implementation and testing subcard 2, peripheral interface module adopts the general-purpose interface such as XMC standard interface or PMC standard interface, support multiple high speed communication agreement, the expansion that test vector produces the test daughter board 2 of plate 1 and difference in functionality can be realized.
Multiple clock required for clock generating module primary responsibility generation system, and distribute subsystems on each plate by multipath clock.The effect of power module is to provide the different voltages on test vector generation plate 1 required for each components and parts, and the components and parts for whole plate provide guarantee of powering reliably.
To be introduced respectively modules below.
A. processor
Processor can adopt TITMS320C6678 polycaryon processor as process core, this chip has 8 physics kernels, have monokaryon 64KB level cache and monokaryon 512KB L2 cache, frequency of operation can reach 1.25GHz, and floating-point operation ability is up to monokaryon 20GFLPOS.This processor and 1GBDDR3 internal memory and 16MBNORFLASH form minimum system, are responsible for controlling whole plate, produce corresponding test command.Processor accesses outside DDR3 internal memory by built-in DDR Memory Controller Hub, and on sheet, 16MBFLASH is distributed to, as storage program in the CE0 subspace of EMIF.Processor external reception processor has the parallel EMIF bus of 16bit width, and this bus directly accesses in the I/O interface of fpga chip, and CPU is configured and data transmission configurable communications protocol generation module by this bus.
B. configurable communications protocol generation module.
Configurable communications protocol generation module adopts one piece of large-scale F PGA chip to realize, concrete framework as shown in Figure 3, inside contains following module: clock synchronization module, data store RAM module, protocol configuration module, Logic control module, serioparallel exchange module and communications protocol generation module, conversion and the data transmit-receive of multiple serial or parallel communications protocol can be carried out, support isa bus, SRIO, PCI-E, I2C, SPI and UART communications protocol.The major function of FPGA carries out the conversion of various communications protocol, and inside is integrated with multiple bus controller, comprises UART, SPI, I2C, SRIO, PCI-E and ISA etc.This fpga chip can adopt the VIRTEX6 family chip of XILINX company, and this chip has the logical block up to 310,000,720 road configurable I/Os, has the external interface that PCI-E, SRIO, I2C, SPI etc. are abundant.
Protocol configuration module is connected with processor carries out communications protocol configuration according to the test command of processor to data, protocol configuration module is connected with communications protocol generation module, deploy content is sent to communications protocol generation module, communications protocol generation module produces the packet of corresponding communications protocol according to deploy content, communications protocol generation module and serioparallel exchange model calling, by Packet Generation to serioparallel exchange module, serioparallel exchange module is carried out after the conversion of serial data and parallel data to outer transmission packet, clock synchronization module and protocol configuration module, Logic control module, serioparallel exchange module is connected respectively with communications protocol generation module, by each module of Ti Gong Give after external clock, Logic control module for coordinating each module is connected with protocol configuration module and communications protocol generation module, data store RAM module and are connected with communications protocol generation module, the feedback data of memory communicating agreement generation module decoding.The function of concrete each module is as follows:
The function of clock synchronization module is the clock that in system, modules needs by the clock synchronous of outside, and be assigned in modules.
It is the data that communications protocol generation module produces stored that data store RAM functions of modules, is taken out by CPU by external bus.
The function of protocol configuration module receives the packet that processor subsystem sends, and packet carried out decoding process.
The function of Logic control module is the collaborative work of each submodule of inside coordinating the configurable communications protocol generation module of the right fruit.
Serioparallel exchange functions of modules transfers serial data transmission to by passing the parallel data of coming.
Communications protocol generation module function is the packet producing corresponding communications protocol according to the configuration of outside.
Data transmission relations are: external data sends to protocol configuration module, carry out data unpack by it, and according to deploy content, communications protocol generation module is configured to the packet producing and meet respective protocol, packet is sent by serioparallel exchange module.
When testing subcard and returning test data, communications protocol generation module is to this decoding data, and by the test data that obtains stored in internal RAM, and produce an interruption to processor subsystem, notification processor subsystem takes data away.
Logic control module is responsible for the United Dispatching between each submodule.
C. clock generating module
Clock generating module is made up of one piece of configurable clock generating module CDCE62005 and peripheral crystal oscillator, this module can be programmed to it by outside SPI interface, export 4 road differential clocks, as the reference clock of the High-speed I/O of processor subsystem and configurable communications protocol generation module.
D. peripheral interface module
Peripheral interface module comprises level transferring chip that on plate, various bus is corresponding and the plate connector between motherboard and daughter board, adopt the connector meeting XMC standard or PMC standard to be connected between motherboard with daughter board, between all plates, data interaction is transmitted by this connector.
E. power module
Power module is used as whole system and powers, and adopts multiple power sources chip, converts 12V standard input to varying level required for chip on board.
(2) subcard 2 is tested
Test subcard 2 comprises socket and the communication interface circuit of grafting chip under test, and the peripheral interface module that communication interface circuit produces on plate with test vector is connected by communication bus, and communication interface circuit is connected with socket.Test vector produces plate and produces test vector is sent to grafting chip under test socket by communication interface circuit, and chip under test receives and produces feedback.
Test subcard comprises FPGA or CPLD, FPGA or CPLD is connected with socket and communication interface circuit.Some test vector can be converted to the agreement meeting chip relevant criterion by FPGA or CPLD, or carries out level conversion etc., strengthens the function of test and a series of subsidiary function such as to show test results.
Test subcard 2 carries out the design of corresponding test circuit according to the function of the chip that will test, all designs to meet following some:
1) interface standard will meet XMC standard or PMC standard, and signal location definition will to produce plate interface standard consistent with test vector.
2) there is the communication interface circuit that test needs.
3) possess test and excitation to receive and feedback function, for receiving the test and excitation of motherboard and carrying out result feedback.If chip under test does not possess this function, can be realized by outside CPLD or FPGA.
Each test subcard receives test vector and produces the test vector that transmits of board, is sent to chip under test, and chip is exported data feedback produces board to test vector.The CPU produced on board by test vector carries out aggregation of data analysis and decision.Test subcard can increase and decrease easily according to the difference of the function of test chip and encapsulation and on other subsystems without impact, be that system has good dirigibility and extensibility.
Test macro of the present utility model is used to carry out the flow process of chip testing
System testing flow process as shown in Figure 4, specifically describes as follows:
A. after system electrification, first processor loads test procedure, is configured, under making configurable communications protocol generation module be in corresponding mode of operation according to the communications protocol that test needs to configurable communications protocol generation module.
B. continuity testing is carried out, stuck fault whether is had between test macro bus, CPU is to configurable communications protocol generation module write full 0 or complete 1 two kinds of data, configurable communications protocol generation module sends to test daughter board by needing the interface of test, do not deal with direct passback to data after the FPGA of test daughter board receives data, the configurable communications protocol generation module of motherboard receives data test, and whether it has reachability problem.
C.CPU carries out communications protocol test by configurable communications protocol generation module and test daughter board, CPU is to configurable communications protocol generation module write fc-specific test FC data, configurable communications protocol generation module sends to test daughter board according to corresponding communications protocol, returned by data acquisition parallel bus after decoding data after the FPGA of test daughter board receives data, the configurable communications protocol generation module of motherboard receives data test, and whether it has communications protocol problem.
D. chip functions test is carried out, test vector is transmitted to test daughter board by configurable communications protocol generation module according to the function of required test by CPU, chip under test on test daughter board receives test vector and produces corresponding test result, CPLD or FPGA on test results daughter board sends it back the configurable communications protocol generation module on test vector generation plate, configurable communications protocol generation module is decoded according to corresponding communications protocol, and by deposit data in specific internal RAM, and an interruption is produced to CPU, notice CPU takes data away.Test data and expected results compare by CPU, judge that whether chip functions is correct.
Claims (9)
1. the test macro of the System on Chip/SoC of a test configurations multiple kinds, it is characterized in that, comprise a test vector and produce plate and polylith test subcard, each test subcard and test vector produce plate and are connected, described test vector produces plate and comprises processor, SDRAM, FLASH chip and configurable communications protocol generation module, processor is connected by internal bus with configurable communications protocol generation module, configurable communications protocol generation module is connected with test subcard by multiple communication bus, and SDRAM is connected with processor respectively by internal bus with FLASH chip.
2. the test macro of the System on Chip/SoC of test configurations multiple kinds as claimed in claim 1, is characterized in that, each test subcard is produced plate with test vector and is connected by expansion interface.
3. the test macro of the System on Chip/SoC of test configurations multiple kinds as claimed in claim 1, is characterized in that, described test vector produces plate and also comprises configuring chip, and configuring chip is connected with configurable communications protocol generation module.
4. the test macro of the System on Chip/SoC of test configurations multiple kinds as claimed in claim 1, it is characterized in that, described test vector produces on plate and arranges peripheral interface module, and peripheral interface module is connected by multiple communication bus with configurable communications protocol generation module.
5. the test macro of the System on Chip/SoC of test configurations multiple kinds as claimed in claim 1, is characterized in that, described test vector produces on plate and also arranges clock generating module, and clock generating module is connected with processor.
6. the test macro of the System on Chip/SoC of the test configurations multiple kinds as described in any one of claim 1-5, is characterized in that, described configurable communications protocol generation module is a large-scale F PGA.
7. the test macro of the System on Chip/SoC of the test configurations multiple kinds as described in any one of claim 1-5, it is characterized in that, described configurable communications protocol generation module comprises clock synchronization module, data store RAM module, protocol configuration module, Logic control module, serioparallel exchange module and communications protocol generation module, protocol configuration module is connected with processor carries out communications protocol configuration according to the test command of processor to data, protocol configuration module is connected with communications protocol generation module, deploy content is sent to communications protocol generation module, communications protocol generation module produces the packet of corresponding communications protocol according to deploy content, communications protocol generation module and serioparallel exchange model calling, by Packet Generation to serioparallel exchange module, serioparallel exchange module is carried out after the conversion of serial data and parallel data to outer transmission packet, clock synchronization module and protocol configuration module, Logic control module, serioparallel exchange module is connected respectively with communications protocol generation module, by each module of Ti Gong Give after external clock, Logic control module for coordinating each module is connected with protocol configuration module and communications protocol generation module, data store RAM module and are connected with communications protocol generation module, the feedback data of memory communicating agreement generation module decoding.
8. the test macro of the System on Chip/SoC of test configurations multiple kinds as claimed in claim 1, described test subcard comprises socket and the communication interface circuit of grafting chip under test, the peripheral interface module that communication interface circuit produces on plate with test vector is connected by communication bus, and communication interface circuit is connected with socket.
9. the test macro of the System on Chip/SoC of test configurations multiple kinds as claimed in claim 8, described test subcard comprises FPGA or CPLD, FPGA or CPLD is connected with socket and communication interface circuit.
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