CN203761518U - FPGA-based Camera Link interface experiment and development system - Google Patents
FPGA-based Camera Link interface experiment and development system Download PDFInfo
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Abstract
The utility model relates to an FPGA-based Camera Link interface experiment and development system and belongs to the digital logic design and high speed data transmission technology field. The system comprise an FPGA-based Camera Link interface experiment and development circuit board that includes an FPGA device, an FPGA periphery circuit, a Camera Link circuit, an interboard I/O interface circuit and a stabilized power supply circuit. The system can be connected with a computer through a Camera Link interface cable to serve as an experiment platform for studying an embedded system of FPGA-based Camera Link camera control and Channel Link high speed data transmission or serve as a development board for studying an actual CCD camera system. The system also can be connected with a computer via a USB download cable to serve as an experiment circuit board for studying FPGA programming and application technology or serve as a development board for studying an actual FPGA application system.
Description
Technical field
The utility model relates to a kind of Camera Link interface experiment and development system based on FPGA, is especially applicable to Camera Link interface experiment and application and development based on FPGA, belongs to Logical Design and Highspeed Data Transmission Technology field.
Background technology
Camera Link is a kind of high speed image data host-host protocol, is by NI, picture pick-up device supplier and some IMAQ companies, in the beginning of this century, to be combined the communication interface technical standard of a kind of machine vision applications of proposition.Use this agreement can simplified image acquisition interface, make between camera and data collecting card be connected more convenient.Camera Link interface is to develop on the basis of Channel Link transmission technology.Channel Link technology is a kind of technology of Low Voltage Differential Signal (LVDS) exploitation of National Semiconductor based in physical layer, and this technology is just expanded after being born, and is used as new video data transmitting utilization.Camera Link agreement, after being suggested in October, 2000, is widely adopted by image pick-up card and camera manufacturer.
Field programmable logic device FPGA is a kind of more novel digital logic device growing up the nearly more than ten years, is the basic device of design of modern complex digital electronic system.FPGA (Field Programmable Gate Array) Embedded System Design technology has become one of the most popular technology of information industry, and range of application spreads all over many popular domains such as Aeronautics and Astronautics, mechano-electronic, medical treatment, communication, automobile.FPGA design is conventionally based on a kind of hardware description language (as VHDL or Verilog), and exercise and grasp FPGA method for designing and hardware description language are associated electrical engineers and technicians' important learning contents.
Due to ease for use and the advantage of low cost of FPGA, the application in image transmitting and data communication field is very wide at present.As previously mentioned, adopt the high speed camera system of Camera Link agreement also a lot.So the combination of FPGA and Camera Link is very natural thing namely.Electronic engineering technical staff is increasing gradually to the requirement of interest, study and the real training of FPGA and Camera Link application technology.But also do not take into account in the market the study product of FPGA and Camera Link technology simultaneously.Therefore, be necessary to design a kind of Camera Link interface experiment and development system based on FPGA, both can meet related personnel's study requirement, also can be used as a simple and practical development system, among the research and development for the small-sized engineering project based on flush bonding processor.
Summary of the invention
The problem that the utility model solves is: a kind of Camera Link interface experiment and development system based on FPGA is provided, so that for electronic engineering those skilled in the art provide the experiment porch of a kind of FPGA of study designing technique and Camera Link Highspeed Data Transmission Technology, meanwhile, take circuit board that this circuit makes as basis can be directly used in the Application and Development system of FPGA or Camera Link.
Technical solutions of the utility model are: a kind of Camera Link interface experiment and development system based on FPGA, comprise Camera Link interface experiment and a development board based on FPGA, described Camera Link interface experiment and development board based on FPGA comprises I/O interface circuit, Camera Link circuit and voltage-stabilized power supply circuit between FPGA device, FPGA peripheral circuit, plate; The described Camera Link interface experiment based on FPGA is connected with outside+5V DC power supply with the voltage-stabilized power supply circuit in development board, jtag interface in FPGA peripheral circuit and AS interface are connected to the USB interface of external computer system by USB download cable, Camera Link circuit is connected to the Camera Link image pick-up card in external computer system by Camera Link cable, and between plate, I/O interface circuit is connected to outside experiment and control system.The jtag interface that computer user can connect by USB download cable carries out online programming and debugging to FPGA, and the AS interface that also can connect by USB download cable is by the firmware downloads of having debugged and be saved in Flash memory; Meanwhile, can also carry out data communication by the Camera Link interface of RS232 interface and the Nios II CPU of FPGA inside of the asynchronous serial communication in Camera Link agreement; In addition, because I/O interface circuit between the plate of this circuit board is connected to, test outside and the I/O interface of control system, facilitates user to carry out the control of signal testing or outside experimental circuit.
Described FPGA device adopts the EP3C16Q240 of the Cyclone III series that altera corp produces, and FPGA device inside circuit comprises on SOC (system on a chip) management and control circuit, sheet PIO circuit on Programmable Logic Device, Nios II CPU, sheet; SOC (system on a chip) management is connected with FPGA peripheral circuit with control circuit, be connected with Nios II CPU with Programmable Logic Device on sheet simultaneously, on sheet, Programmable Logic Device is connected with PIO circuit on Nios II CPU and sheet respectively, on sheet PIO circuit respectively with plate between I/O interface circuit, Camera Link circuit be connected.SOC (system on a chip) management comprises Clock management circuit, power distribution circuit, configuration circuit, guiding logical circuit and JTAG debug circuit with control circuit.
Described FPGA peripheral circuit comprises SRAM circuit, clock driving and cpu reset circuit, Flash memory, AS interface circuit, jtag interface circuit, SRAM circuit consists of 1 or 2 16 SRAM, and SRAM is connected with Avalon data/address bus, address bus and the control bus of the Nios II CPU of FPGA device inside, clock drives and 4 tunnel clock signals of cpu reset circuit output and 1 cpu reset signal are connected to 5 clock input pins of FPGA device, clock driver circuit is linked in sequence and is formed by crystal oscillator and clock driver, clock driver adopts the PI49FCT3805DQE device of IDT company, and only use 4 clock signals in the 1:5 fan-out that wherein A organizes, this 4 tunnel clock signal is connected to 4 clock input pin (CLK0 of FPGA device, CLK4, CLK11, CLK15), cpu reset circuit is comprised of a push-button switch and a triode, collector electrode output cpu reset signal from triode, this reset signal is connected to 1 clock input pin CLK2 of FPGA device, after being connected with AS interface circuit, Flash memory is connected with the configuration circuit pin in control circuit with the SOC (system on a chip) management of FPGA device again, Flash memory adopts a slice EPCS4SI8 device, AS interface circuit comprises the socket of 10 pins, configure indicating circuit and reshuffle button, JTAG debug circuit in the SOC (system on a chip) management that jtag interface circuit is connected to FPGA device and control circuit, jtag interface circuit comprises the amplitude limiter circuit of the socket of 10 pins, simple resistance and Schottky diode formation.
Between described plate, I/O interface circuit comprises I/O connector between plate, output buffer and out connector; Between plate, I/O connector is connected with PIO circuit on sheet on FPGA device, the data input pin of output buffer and passage Enable Pin are connected to the output pin of PIO circuit on sheet, output and the out connector of output buffer are linked in sequence, between plate, I/O connector is all connected with control system with outside experiment with out connector, between plate, I/O interface circuit can facilitate user to carry out the test of the logical signal of FPGA generation, can be directly used in signal access or the output of outside experimental circuit and control system simultaneously.
Described Camera Link circuit comprises CL clock selection circuit, data buffer and Camera Link interface circuit; The input of CL clock selection circuit is connected with the output of PIO circuit on sheet on FPGA device, and the output of CL clock selection circuit is connected to clock input pin TxCLKIn and the power remove of the Channel Link driver in Camera Link interface circuit and controls pin PWRDWN; The data input pin of data buffer and passage Enable Pin are connected with the output of PIO circuit on sheet on FPGA device, and the output of data buffer is connected with the data input pin of Channel Link driver in Camera Link interface circuit; Camera Link interface circuit comprises Low Voltage Differential Signal (LVDS) transceiving device of Channel Link driver, camera control (CC) signal and general serial asynchronous communication (UART) signal, the Channel Link driver that view data is uploaded adopts DS90CR287, LVDS transceiving device adopts DS90LV048 and DS90LV047, and Channel Link driver is connected with the Camera Link image pick-up card in external computer system by Camera Link cable with LVDS transceiving device.
Described voltage-stabilized power supply circuit comprises 3.3V voltage-stabilized power supply circuit, 2.5V voltage-stabilized power supply circuit and 1.2V voltage-stabilized power supply circuit and filter circuit, the output of the input termination 3.3V voltage-stabilized power supply circuit of 1.2V voltage-stabilized power supply circuit, the output of input termination outside+5V DC power supply of 2.5V voltage-stabilized power supply circuit; The output of 3.3V voltage-stabilized power supply circuit is connected to respectively SRAM circuit in FPGA peripheral circuit, clock drives and the power end of cpu reset circuit, Flash memory and AS interface circuit, jtag interface circuit, plate between power end, the data buffer in Camera Link circuit of output buffer in I/O interface circuit, the power end of Camera Link interface circuit; 3.3V, 2.5V and 1.2V voltage stabilizing circuit are the power supply of FPGA device simultaneously, 3.3V voltage-stabilized power supply circuit output is also connected to the 3.3V power pins of FPGA device, the output of 2.5V voltage-stabilized power supply circuit is connected to the power pins of the clock phase-locked loop loop circuit of FPGA device through a LC filter circuit, the output of 1.2V voltage-stabilized power supply circuit is connected to the 1.2V power pins of FPGA device.
Described Camera Link interface experiment and the components and parts in development board based on FPGA are removed outside signal input-output socket and power supply base, and other components and parts are all selected the components and parts of Surface Mount encapsulation.
In the utility model, the effect of each circuit module is: the SOC (system on a chip) management in FPGA device comprises Clock management circuit, power distribution circuit, configuration circuit, guiding logical circuit and JTAG debug circuit with control circuit, the effect of each parallel circuit is: on sheet, Clock management circuit is mainly used in the access of device work master clock and auxiliary clock signal and the distribution of clock and management, user can, by its inner pll parameter is set, regulate the operating frequency of Programmable Logic Device; (3.3V, 2.5V, the 1.2V) access of power supply of all kinds of varying levels and the distribution of power supply and management when on-chip power supply distributor circuit is mainly used in device work FPGA work; On sheet, configuration circuit carries out circuit reconstruct according to compiled firmware scene to the configurable gate array logic of FPGA, forms the logical circuit that user needs; The coordination and control of the key signals such as clock signal, firmware configuration signal, AS interface configuration signal, JTAG download and the debug signal after guiding logical circuit mainly to complete on sheet to power on or during cpu reset, cpu reset signal.On sheet in FPGA device, Programmable Logic Device is the spendable program logic circuit of user, can be by user's oneself requirement, in the scope allowing in FPGA gate array logic unit number, realize combinational logic circuit, the sequential logical circuit of different scales, or the two hybrid circuit, the sequential requiring with completing user and the input and output of logical signal.To be user require to customize according to external system Nios II CPU in FPGA device based on bus-structured 32 flush bonding processors of Altera Avalon, instruction transmitting-receiving, various command parsing be can complete and processing, mathematical operation and data communication etc. carried out, interrupt, can be connected with user-programmable logical circuit easily and reciprocation, complete the task more complicated than conventional CPU.If PIO main circuit guiding external logic signal enters FPGA inside on sheet, drive the inner output logic signal of FPGA to external pin simultaneously, thereby realize the handshaking between FPGA and external circuit.
In FPGA peripheral circuit module, SRAM circuit enters internal circuit by the I/O pin of FPGA, and is connected with Nios II CPU by Altera Avalon bus, and SRAM is as the program of Nios II CPU work and the memory of data.Clock driver circuit mainly produces needed 4 input clock signals of FPGA device work station, and cpu reset circuit produces the reset signal of Nios II CPU.AS interface circuit is mainly used in outer computer, with active serial mode, the firmware after compiling is downloaded to Flash memory by Altera specific download cable, configuration indicating circuit is when FPGA carries out firmware configuration formation user logic circuit, LED light is glittering, press and reshuffle button, force FPGA to carry out rearranging logic circuit.Jtag interface circuit is mainly used in outer computer, by Altera specific download cable, FPGA device is carried out to online firmware downloads and configuration, and the on-line debugging of whole embedded system.
Between the plate between plate in I/O interface module, I/O connector is directly introduced into input pin on FPGA sheet by the output signal of external circuit or system, directly the logic OR clock signal of FPGA output pin output is outputed to external circuit or system simultaneously, owing to being that on FPGA sheet, PIO circuit directly drives, its driving force is less.The main purpose of output buffer is the driving force that increases a part of FPGA output signal.
The output of the CL clock selection circuit in Camera Link circuit is connected to clock input pin TxCLKIn and the power remove of the Channel Link driver in Camera Link interface circuit and controls pin PWRDWN, can be according to the needs of experimental system, Channel Link driver is controlled, started or stoped driver, change Camera Link message transmission rate.Data buffer provides the high-speed data that comes from FPGA for Camera Link interface circuit.Camera Link interface circuit converts parallel view data to high-speed serial signals and goes out by Double-strand transmission with LVDS form, and message transmission rate is high, good in anti-interference performance.On the one hand, conversion and driving from FPGA through the data image signal process driver chip DS90CR287 of data buffer output, by connector MDR26 and Camera Link cable, be transferred in the corresponding receiving circuit of the Camera Link image pick-up card in image workstation (or PC), image pick-up card also extracts LVAD, FVAD, DVAD signal from this cable, the synchronizing signal while recovering as high speed image data.On the other hand, general serial asynchronous communication (UART) circuit in Camera Link interface circuit provides the both-way communication service of RS232 standard for the Nios II CPU in FPGA and image workstation; In addition, from 4 camera controls (CC) signal of image workstation, by LVDS receiver, convert TTL signal to, by PIO circuit on sheet, enter FPGA inside, can be used as camera control and use, also can be used as other control signal and use.
3.3V in voltage-stabilized power supply circuit is 1.2V voltage-stabilized power supply circuit, SRAM circuit, clock drives and cpu reset circuit, Flash memory and AS interface circuit, jtag interface circuit, output buffer, data buffer and the power supply of Camera Link interface circuit.3.3V, 2.5V and 1.2V voltage stabilizing circuit are the power supply of FPGA device jointly.
The specific implementation of a kind of Camera Link interface experiment based on FPGA and development system is as follows:
NiosⅡCPU。The FPGA embedded software core processor Nios II of Altera is Camera Link interface experiment based on FPGA and the core controller of development system.Externally under the Altera Quartus II development environment of computer, use SOPC Builder to set up 32 soft nucleus CPUs based on Avalon bus, add the necessary IP kernel such as SRAM, UART, be articulated in Avalon bus, compile afterwards and generate Nios II CPU.In Altera Quartus II, call Nios II CPU, can, with Programmable Logic Device on sheet together with chip external memory, form a powerful Digital Logic treatment system.
Programmable Logic Device on sheet.User is according to the requirement of oneself, under Altera Quartus II development environment, with any one HDL language (as VHDL or Verilog), write after the logical circuit needing, compile and generate the firmware of the logical circuit of user design, by jtag interface, download to and in FPGA, carry out on-line debugging.Firmware after debugging is passed through, can download and be saved in Flash memory by AS interface, and after FPGA powers on like this, system configures automatically, forms the Programmable Logic Device of user's design.Owing to being that user is self-designed, can realize the function that user needs, as read the input signal of outside experimental circuit, output logic or clock signal go to control outside experimental circuit or system, also can control easily Camera Link circuit, function is controlled in the imaging of simulation Camera Link camera, or is directly designed to CCD timing sequencer, realize the imaging of CCD camera and control, can also realize communication and high speed data transfer with external computer system.
SRAM circuit.1 or 2 16 SRAM, consist of, SRAM is connected with Avalon data/address bus, address bus and the control bus of the Nios II CPU of FPGA device inside.If use 2 16 SRAM, as long as they are combined into the form of 32 SRAM of a slice, directly articulate with the Avalon data/address bus of 32.If but adopted 1 16 SRAM, would need to design the SRAM IP kernel of the data/address bus of 16 bit widths, and when design Nios II CPU, this SRAM IP kernel of 16 is articulated in Avalon bus.
Camera Link interface circuit.This transmission interface circuit can convert parallel view data to high-speed serial signals and go out by twisted-pair feeder high-speed transfer with LVDS form.From the high-speed data process data buffer of FPGA output and conversion and the driving of DS90CR287 chip, by connector MDR26 and Camera Link cable, be transferred in the corresponding receiving circuit of the Camera Link image pick-up card in image workstation (or PC), image pick-up card also extracts LVAD, FVAD, DVAD signal from this cable, the synchronizing signal while recovering as high-speed data.The UART interface circuit articulating with soft nucleus CPU due to the serial asynchronous communication circuit in Camera Link interface circuit is connected, and external computer system just can carry out data communication by UART and the Nios II CPU of RS232 standard like this.External computer system also can directly be controlled Programmable Logic Device on the sheet of FPGA by 4 camera controls (CC) signal.
Voltage-stabilized power supply circuit.This circuit adopts the direct input power of outside one+5V, use a 3.3V, 2.5V and 1.2V the fixedly three terminal integrated voltage stabilizer of totally three low voltage differences and the electric source filter circuit that some magnetic beads, inductor and capacitor form form, for the whole circuit in this circuit provide stable and low noise electric energy.
The beneficial effects of the utility model are: a kind of Camera Link interface experiment and development system based on FPGA, can directly by Camera Link interface cable, be connected with external computer system, Camera Link camera control as study based on FPGA and the experiment porch of embedded system or the development board of actual CCD camera system of Channel Link high speed data transfer, can also directly by USB download cable, be connected with outer computer, as study FPGA programming and the breakboard construction of application technology or the development board of actual FPGA application system.
Accompanying drawing explanation
Fig. 1 is the utility model system construction drawing;
Fig. 2 is module connection layout of the present utility model;
Fig. 3 is the module connection layout of the utility model embodiment 2;
Fig. 4 is the module connection layout of the utility model embodiment 3.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.
Embodiment 1: as shown in Figure 1-2, a kind of Camera Link interface experiment and development system based on FPGA, comprise Camera Link interface experiment and a development board based on FPGA, described Camera Link interface experiment and development board based on FPGA comprises I/O interface circuit, Camera Link circuit and voltage-stabilized power supply circuit between FPGA device, FPGA peripheral circuit, plate; The described Camera Link interface experiment based on FPGA is connected with outside+5V DC power supply with the voltage-stabilized power supply circuit in development board, jtag interface in FPGA peripheral circuit and AS interface are connected to the USB interface of external computer system by USB download cable, Camera Link circuit is connected to the Camera Link image pick-up card in external computer system by Camera Link cable, and between plate, I/O interface circuit is connected to outside experiment and control system.
Described FPGA device inside circuit comprises on SOC (system on a chip) management and control circuit, sheet PIO circuit on Programmable Logic Device, Nios II CPU, sheet; SOC (system on a chip) management is connected with FPGA peripheral circuit with control circuit, be connected with Nios II CPU with Programmable Logic Device on sheet simultaneously, on sheet, Programmable Logic Device is connected with PIO circuit on Nios II CPU and sheet respectively, on sheet PIO circuit respectively with plate between I/O interface circuit, Camera Link circuit be connected.
Described FPGA peripheral circuit comprises SRAM circuit, clock driving and cpu reset circuit, Flash memory, AS interface circuit, jtag interface circuit; SRAM circuit consists of 1 or 2 16 SRAM, and SRAM is connected with Avalon data/address bus, address bus and the control bus of the Nios II CPU of FPGA device inside; Clock drives and 4 tunnel clock signals of cpu reset circuit output and 1 cpu reset signal are connected to 5 clock input pins of FPGA device; After being connected with AS interface circuit, Flash memory is connected with the configuration circuit pin in control circuit with the SOC (system on a chip) management of FPGA device again, Flash memory adopts a slice EPCS4SI8 device, AS interface circuit comprise 10 pins socket, configure indicating circuit and reshuffle button; JTAG debug circuit in the SOC (system on a chip) management that jtag interface circuit is connected to FPGA device and control circuit, jtag interface circuit comprises the amplitude limiter circuit of the socket of 10 pins, simple resistance and Schottky diode formation.
Between described plate, I/O interface circuit comprises I/O connector between plate, output buffer and out connector; Between plate, I/O connector is connected with PIO circuit on sheet on FPGA device, the data input pin of output buffer and passage Enable Pin are connected to the output pin of PIO circuit on sheet, output and the out connector of output buffer are linked in sequence, and between plate, I/O connector is all connected with control system with outside experiment with out connector.
Described Camera Link circuit comprises CL clock selection circuit, data buffer and Camera Link interface circuit; The input of CL clock selection circuit is connected with the output of PIO circuit on sheet on FPGA device, and the output of CL clock selection circuit is connected to clock input pin and the power remove of the Channel Link driver in Camera Link interface circuit and controls pin; The data input pin of data buffer and passage Enable Pin are connected with the output of PIO circuit on sheet on FPGA device, and the output of data buffer is connected with the data input pin of Channel Link driver in Camera Link interface circuit; Camera Link interface circuit comprises Channel Link driver, Low Voltage Differential Signal LVDS transceiving device, the Channel Link driver that view data is uploaded adopts DS90CR287, LVDS transceiving device adopts DS90LV048 and DS90LV047, and Channel Link driver is connected with the Camera Link image pick-up card in external computer system by Camera Link cable with LVDS transceiving device.
Described voltage-stabilized power supply circuit comprises 3.3V voltage-stabilized power supply circuit, 2.5V voltage-stabilized power supply circuit and 1.2V voltage-stabilized power supply circuit and filter circuit, the output of the input termination 3.3V voltage-stabilized power supply circuit of 1.2V voltage-stabilized power supply circuit, the output of input termination outside+5V DC power supply of 2.5V voltage-stabilized power supply circuit; The output of 3.3V voltage-stabilized power supply circuit is connected to respectively SRAM circuit in FPGA peripheral circuit, clock drives and the power end of cpu reset circuit, Flash memory and AS interface circuit, jtag interface circuit, plate between power end, the data buffer in Camera Link circuit of output buffer in I/O interface circuit, the power end of Camera Link interface circuit; 3.3V voltage-stabilized power supply circuit output is also connected to the 3.3V power pins of FPGA device, the output of 2.5V voltage-stabilized power supply circuit is connected to the power pins of the clock phase-locked loop loop circuit of FPGA device through a LC filter circuit, the output of 1.2V voltage-stabilized power supply circuit is connected to the 1.2V power pins of FPGA device.
Described Camera Link interface experiment and the components and parts in development board based on FPGA are removed outside signal input-output socket and power supply base, and other components and parts are all selected the components and parts of Surface Mount encapsulation.
This embodiment is applicable to that Camera Link interface is used as to a pure Channel Link high speed data transfer passage to carry out among the specific embedded data system development of mass data high-speed uploading, is also suitable among some exploitations that need the embedded digital logic systems that outer computer (host computer) controls.
Embodiment 2: as shown in Fig. 1 Fig. 3, a kind of Camera Link interface experiment and development system based on FPGA, comprise Camera Link interface experiment and a development board based on FPGA, described Camera Link interface experiment and development board based on FPGA comprises I/O interface circuit, Camera Link circuit and voltage-stabilized power supply circuit between FPGA device, FPGA peripheral circuit, plate; The described Camera Link interface experiment based on FPGA is connected with outside+5V DC power supply with the voltage-stabilized power supply circuit in development board, jtag interface in FPGA peripheral circuit and AS interface are connected to the USB interface of external computer system by USB download cable, Camera Link circuit is connected to the Camera Link image pick-up card in external computer system by Camera Link cable, and between plate, I/O interface circuit is connected to outside CCD camera control system.
Described FPGA device inside circuit comprises on SOC (system on a chip) management and control circuit, sheet PIO circuit on Programmable Logic Device, Nios II CPU, sheet; SOC (system on a chip) management is connected with FPGA peripheral circuit with control circuit, be connected with Nios II CPU with Programmable Logic Device on sheet simultaneously, on sheet, CCD timing sequencer is connected with PIO circuit on Nios II CPU and sheet respectively, on sheet PIO circuit respectively with plate between I/O interface circuit, Camera Link circuit be connected.On sheet, CCD timing sequencer is the Programmable Logic Device that user adopts HDL language design and generates according to outside CCD camera control system requirements.
Described FPGA peripheral circuit comprises SRAM circuit, clock driving and cpu reset circuit, Flash memory, AS interface circuit, jtag interface circuit; SRAM circuit consists of 1 or 2 16 SRAM, and SRAM is connected with Avalon data/address bus, address bus and the control bus of the Nios II CPU of FPGA device inside; Clock drives and 4 tunnel clock signals of cpu reset circuit output and 1 cpu reset signal are connected to 5 clock input pins of FPGA device; After being connected with AS interface circuit, Flash memory is connected with the configuration circuit pin in control circuit with the SOC (system on a chip) management of FPGA device again, Flash memory adopts a slice EPCS4SI8 device, AS interface circuit comprise 10 pins socket, configure indicating circuit and reshuffle button; JTAG debug circuit in the SOC (system on a chip) management that jtag interface circuit is connected to FPGA device and control circuit, jtag interface circuit comprises the amplitude limiter circuit of the socket of 10 pins, simple resistance and Schottky diode formation.
Between described plate, I/O interface circuit comprises I/O connector between plate, output buffer and out connector; Between plate, I/O connector is connected with PIO circuit on sheet on FPGA device, the data input pin of output buffer and passage Enable Pin are connected to the output pin of PIO circuit on sheet, output and the out connector of output buffer are linked in sequence, between plate I/O connector and out connector all with outside CCD camera control system.CCD clock signal and other control signal that output buffer and out connector produce CCD timing sequencer output to outside CCD camera control system, and I/O connector is inputted the ccd image data of external camera system.
Described Camera Link circuit comprises CL clock selection circuit, data buffer and Camera Link interface circuit; The input of CL clock selection circuit is connected with the output of PIO circuit on sheet on FPGA device, and the output of CL clock selection circuit is connected to clock input pin and the power remove of the Channel Link driver in Camera Link interface circuit and controls pin; The data input pin of data buffer and passage Enable Pin are connected with the output of PIO circuit on sheet on FPGA device, and the output of data buffer is connected with the data input pin of Channel Link driver in Camera Link interface circuit; Camera Link interface circuit comprises Channel Link driver, Low Voltage Differential Signal LVDS transceiving device, the Channel Link driver that view data is uploaded adopts DS90CR287, LVDS transceiving device adopts DS90LV048 and DS90LV047, and Channel Link driver is connected with the Camera Link image pick-up card in external computer system by Camera Link cable with LVDS transceiving device.
Described voltage-stabilized power supply circuit comprises 3.3V voltage-stabilized power supply circuit, 2.5V voltage-stabilized power supply circuit and 1.2V voltage-stabilized power supply circuit and filter circuit, the output of the input termination 3.3V voltage-stabilized power supply circuit of 1.2V voltage-stabilized power supply circuit, the output of input termination outside+5V DC power supply of 2.5V voltage-stabilized power supply circuit; The output of 3.3V voltage-stabilized power supply circuit is connected to respectively SRAM circuit in FPGA peripheral circuit, clock drives and the power end of cpu reset circuit, Flash memory and AS interface circuit, jtag interface circuit, plate between power end, the data buffer in Camera Link circuit of output buffer in I/O interface circuit, the power end of Camera Link interface circuit; 3.3V voltage-stabilized power supply circuit output is also connected to the 3.3V power pins of FPGA device, the output of 2.5V voltage-stabilized power supply circuit is connected to the power pins of the clock phase-locked loop loop circuit of FPGA device through a LC filter circuit, the output of 1.2V voltage-stabilized power supply circuit is connected to the 1.2V power pins of FPGA device.
Described Camera Link interface experiment and the components and parts in development board based on FPGA are removed outside signal input-output socket and power supply base, and other components and parts are all selected the components and parts of Surface Mount encapsulation.
This embodiment is suitable for the experiment porch of Camera Link camera or the development board of actual CCD camera system that this system is controlled as study FPGA, is also suitable as the hardware experiment platform of study Camera Link agreement.
Embodiment 3: as shown in Figure 4 and 1, a kind of Camera Link interface experiment and development system based on FPGA, comprise Camera Link interface experiment and a development board based on FPGA, described Camera Link interface experiment and development board based on FPGA comprises I/O interface circuit and voltage-stabilized power supply circuit between FPGA device, FPGA peripheral circuit, plate; The described Camera Link interface experiment based on FPGA is connected with outside+5V DC power supply with the voltage-stabilized power supply circuit in development board, jtag interface in FPGA peripheral circuit and AS interface are connected to the USB interface of external computer system by USB download cable, between plate, I/O interface circuit is connected to outside experiment and control system.
Described FPGA device inside circuit comprises on SOC (system on a chip) management and control circuit, sheet PIO circuit on Programmable Logic Device, Nios II CPU, sheet; SOC (system on a chip) management is connected with FPGA peripheral circuit with control circuit, is connected with Programmable Logic Device on sheet with Nios II CPU simultaneously; On sheet, Programmable Logic Device is connected with PIO circuit on Nios II CPU and sheet respectively, and on sheet, between PIO circuit and plate, I/O interface circuit is connected.
Described FPGA peripheral circuit comprises SRAM circuit, clock driving and cpu reset circuit, Flash memory, AS interface circuit, jtag interface circuit; SRAM circuit consists of 1 or 2 16 SRAM, and SRAM is connected with Avalon data/address bus, address bus and the control bus of the Nios II CPU of FPGA device inside; Clock drives and 4 tunnel clock signals of cpu reset circuit output and 1 cpu reset signal are connected to 5 clock input pins of FPGA device; After being connected with AS interface circuit, Flash memory is connected with the configuration circuit pin in control circuit with the SOC (system on a chip) management of FPGA device again, Flash memory adopts a slice EPCS4SI8 device, AS interface circuit comprise 10 pins socket, configure indicating circuit and reshuffle button; JTAG debug circuit in the SOC (system on a chip) management that jtag interface circuit is connected to FPGA device and control circuit, jtag interface circuit comprises the amplitude limiter circuit of the socket of 10 pins, simple resistance and Schottky diode formation.
Between described plate, I/O interface circuit comprises I/O connector between plate, output buffer and out connector; Between plate, I/O connector is connected with PIO circuit on sheet on FPGA device, the data input pin of output buffer and passage Enable Pin are connected to the output pin of PIO circuit on sheet, output and the out connector of output buffer are linked in sequence, and between plate, I/O connector is all connected with control system with outside experiment with out connector.
Described voltage-stabilized power supply circuit comprises 3.3V voltage-stabilized power supply circuit, 2.5V voltage-stabilized power supply circuit and 1.2V voltage-stabilized power supply circuit and filter circuit, the output of the input termination 3.3V voltage-stabilized power supply circuit of 1.2V voltage-stabilized power supply circuit, the output of input termination outside+5V DC power supply of 2.5V voltage-stabilized power supply circuit; The output of 3.3V voltage-stabilized power supply circuit is connected to respectively SRAM circuit in FPGA peripheral circuit, clock drives and the power end of cpu reset circuit, Flash memory and AS interface circuit, jtag interface circuit, plate between the power end of output buffer in I/O interface circuit; 3.3V voltage-stabilized power supply circuit output is also connected to the 3.3V power pins of FPGA device, the output of 2.5V voltage-stabilized power supply circuit is connected to the power pins of the clock phase-locked loop loop circuit of FPGA device through a LC filter circuit, the output of 1.2V voltage-stabilized power supply circuit is connected to the 1.2V power pins of FPGA device.
Described Camera Link interface experiment and the components and parts in development board based on FPGA are removed outside signal input-output socket and power supply base, and other components and parts are all selected the components and parts of Surface Mount encapsulation.
This embodiment is suitable for the hardware experiment platform as study FPGA programming technique, and being also suitable for some does not need among the embedded system development with the utonomous working of upper machine communication.
By reference to the accompanying drawings specific embodiment of the utility model is explained in detail above, but the utility model is not limited to above-described embodiment, in the ken possessing those of ordinary skills, can also under the prerequisite that does not depart from the utility model aim, make various variations.
Claims (6)
1. Camera Link interface experiment and the development system based on FPGA, it is characterized in that: comprise Camera Link interface experiment and a development board based on FPGA, described Camera Link interface experiment and development board based on FPGA comprises I/O interface circuit, Camera Link circuit and voltage-stabilized power supply circuit between FPGA device, FPGA peripheral circuit, plate; The described Camera Link interface experiment based on FPGA is connected with outside+5V DC power supply with the voltage-stabilized power supply circuit in development board, jtag interface in FPGA peripheral circuit and AS interface are connected to the USB interface of external computer system by USB download cable, Camera Link circuit is connected to the Camera Link image pick-up card in external computer system by Camera Link cable, and between plate, I/O interface circuit is connected to outside experiment and control system.
2. a kind of Camera Link interface experiment and development system based on FPGA according to claim 1, is characterized in that: described FPGA device inside circuit comprises on SOC (system on a chip) management and control circuit, sheet PIO circuit on Programmable Logic Device, Nios II CPU, sheet; SOC (system on a chip) management is connected with FPGA peripheral circuit with control circuit, be connected with Nios II CPU with Programmable Logic Device on sheet simultaneously, on sheet, Programmable Logic Device is connected with PIO circuit on Nios II CPU and sheet respectively, on sheet PIO circuit respectively with plate between I/O interface circuit, Camera Link circuit be connected.
3. a kind of Camera Link interface experiment and development system based on FPGA according to claim 1, is characterized in that: described FPGA peripheral circuit comprises SRAM circuit, clock driving and cpu reset circuit, Flash memory, AS interface circuit, jtag interface circuit; SRAM circuit consists of 1 or 2 16 SRAM, and SRAM is connected with Avalon data/address bus, address bus and the control bus of the Nios II CPU of FPGA device inside; Clock drives and 4 tunnel clock signals of cpu reset circuit output and 1 cpu reset signal are connected to 5 clock input pins of FPGA device; After being connected with AS interface circuit, Flash memory is connected with the configuration circuit pin in control circuit with the SOC (system on a chip) management of FPGA device again, Flash memory adopts a slice EPCS4SI8 device, AS interface circuit comprise 10 pins socket, configure indicating circuit and reshuffle button; JTAG debug circuit in the SOC (system on a chip) management that jtag interface circuit is connected to FPGA device and control circuit, jtag interface circuit comprises the amplitude limiter circuit of the socket of 10 pins, simple resistance and Schottky diode formation.
4. a kind of Camera Link interface experiment and development system based on FPGA according to claim 1, is characterized in that: between described plate, I/O interface circuit comprises I/O connector between plate, output buffer and out connector; Between plate, I/O connector is connected with PIO circuit on sheet on FPGA device, the data input pin of output buffer and passage Enable Pin are connected to the output pin of PIO circuit on sheet, output and the out connector of output buffer are linked in sequence, and between plate, I/O connector is all connected with control system with outside experiment with out connector.
5. a kind of Camera Link interface experiment and development system based on FPGA according to claim 1, is characterized in that: described Camera Link circuit comprises CL clock selection circuit, data buffer and Camera Link interface circuit; The input of CL clock selection circuit is connected with the output of PIO circuit on sheet on FPGA device, and the output of CL clock selection circuit is connected to clock input pin and the power remove of the Channel Link driver in Camera Link interface circuit and controls pin; The data input pin of data buffer and passage Enable Pin are connected with the output of PIO circuit on sheet on FPGA device, and the output of data buffer is connected with the data input pin of Channel Link driver in Camera Link interface circuit; Camera Link interface circuit comprises Channel Link driver, Low Voltage Differential Signal LVDS transceiving device, the Channel Link driver that view data is uploaded adopts DS90CR287, LVDS transceiving device adopts DS90LV048 and DS90LV047, and Channel Link driver is connected with the Camera Link image pick-up card in external computer system by Camera Link cable with LVDS transceiving device.
6. a kind of Camera Link interface experiment and development system based on FPGA according to claim 1, it is characterized in that: described voltage-stabilized power supply circuit comprises 3.3V voltage-stabilized power supply circuit, 2.5V voltage-stabilized power supply circuit and 1.2V voltage-stabilized power supply circuit and filter circuit, the output of the input termination 3.3V voltage-stabilized power supply circuit of 1.2V voltage-stabilized power supply circuit, the output of input termination outside+5V DC power supply of 2.5V voltage-stabilized power supply circuit; The output of 3.3V voltage-stabilized power supply circuit is connected to respectively SRAM circuit in FPGA peripheral circuit, clock drives and the power end of cpu reset circuit, Flash memory and AS interface circuit, jtag interface circuit, plate between power end, the data buffer in Camera Link circuit of output buffer in I/O interface circuit, the power end of Camera Link interface circuit; 3.3V voltage-stabilized power supply circuit output is also connected to the 3.3V power pins of FPGA device, the output of 2.5V voltage-stabilized power supply circuit is connected to the power pins of the clock phase-locked loop loop circuit of FPGA device through a LC filter circuit, the output of 1.2V voltage-stabilized power supply circuit is connected to the 1.2V power pins of FPGA device.
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| CN201420018844.4U CN203761518U (en) | 2014-01-13 | 2014-01-13 | FPGA-based Camera Link interface experiment and development system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104267638A (en) * | 2014-09-19 | 2015-01-07 | 北京空间机电研究所 | Serializer/deserializer clock source based on clock managers and FPGA |
| CN107426551A (en) * | 2016-05-24 | 2017-12-01 | 中国科学院长春光学精密机械与物理研究所 | A kind of syntype Cameralink digital picture optical transmitter and receiver receiving terminals and transmitting terminal based on FPGA |
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2014
- 2014-01-13 CN CN201420018844.4U patent/CN203761518U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104267638A (en) * | 2014-09-19 | 2015-01-07 | 北京空间机电研究所 | Serializer/deserializer clock source based on clock managers and FPGA |
| CN104267638B (en) * | 2014-09-19 | 2017-01-25 | 北京空间机电研究所 | Serializer/deserializer clock source based on clock managers and FPGA |
| CN107426551A (en) * | 2016-05-24 | 2017-12-01 | 中国科学院长春光学精密机械与物理研究所 | A kind of syntype Cameralink digital picture optical transmitter and receiver receiving terminals and transmitting terminal based on FPGA |
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