CN109408435A - A kind of enhanced jtag interface based on DSP - Google Patents
A kind of enhanced jtag interface based on DSP Download PDFInfo
- Publication number
- CN109408435A CN109408435A CN201811221241.3A CN201811221241A CN109408435A CN 109408435 A CN109408435 A CN 109408435A CN 201811221241 A CN201811221241 A CN 201811221241A CN 109408435 A CN109408435 A CN 109408435A
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- Prior art keywords
- jtag interface
- dsp
- circuit
- pull
- typical
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
Abstract
The invention discloses a kind of enhanced jtag interface based on DSP, the enhanced jtag interface include: dsp chip, typical jtag interface, pull-up circuit, external clock, driving enhancing circuit；Wherein, dsp chip is connect with typical jtag interface, the end TCK-RET of dsp chip is connected with external clock, the end TMS of typical jtag interface, the end TDI, the end EMU0, the end EMU1 is equipped with pull-up circuit, voltage on signal wire is pulled up, the end TDI and TMS of typical jtag interface, the end TDO of dsp chip is equipped with driving enhancing circuit, driving along signal transmission direction is carried out to corresponding signal, solve original dsp chip and the remote procedure simulation of typical jtag interface and programming problem, it is improved by the peripheral circuit to dsp chip to jtag interface, strengthen the driving capability of jtag interface, jtag interface to the cable of emulator can be supported to reach 120cm, meet complicated use environment demand.
Description
Technical field
The present invention relates to circuit design fields, and in particular, to a kind of enhanced jtag interface based on DSP.
Background technique
JTAG is a kind of boundary scan agreement as defined in IEEE1149.1, for the external interface bus state during IC
It is scanned.In recent years, with the development of microprocessor, more and more microprocessors using jtag interface as its kernel with
The intermediary of PC machine communication, realizes the in-circuit emulation of processor, such as DSP, FPGA, is provided with and connects dedicated for the JTAG of emulation
Mouthful.The series DSP chip produced by TI company, can be with jtag interface to its in-circuit emulation.
According to the dsp chip technical specification that TI company provides, the peripheral circuit by dsp chip to jtag interface is designed,
The length of cable of supported jtag interface to emulator is usually no more than 20cm, is unable to satisfy increasingly sophisticated debugging enironment.
The reason is that: dsp chip is light current chip, and the driving capability of pin is all weaker, and the communication of plate grade is out of question, but long distance transmission line
Path loss consumption is excessive, and pin driving capability is insufficient, therefore emulator cable half is no more than 20cm.
Summary of the invention
The present invention provides a kind of enhanced jtag interface based on DSP, solves original dsp chip and typical case JTAG connects
The remote procedure simulation of mouth and programming problem, are improved by the peripheral circuit to dsp chip to jtag interface, strengthen JTAG
The driving capability of interface can support jtag interface to the cable of emulator up to 120cm, meet complicated use environment demand.
For achieving the above object, this application provides a kind of enhanced jtag interface based on DSP, it is described enhanced
Jtag interface includes:
Dsp chip, typical jtag interface, pull-up circuit, external clock, driving enhancing circuit；Wherein, dsp chip and allusion quotation
The connection of type jtag interface, the end TCK-RET of dsp chip are connected with external clock, the end TMS of typical jtag interface, the end TDI,
The end EMU0, the end EMU1 are equipped with pull-up circuit, pull up to the voltage on signal wire, the TDI and TMS of typical jtag interface
End, dsp chip the end TDO be equipped with driving enhancing circuit, to corresponding signal carry out along signal transmission direction driving.
Further, pull-up circuit includes pull-up circuit power supply VCC and pull-up resistor R, pull-up circuit power supply VCC and pull-up
It is connected after resistance R series connection with the corresponding port signal line for needing to pull up.
Further, the pull-up circuit carries out the voltage on signal wire to be pulled to 3.3V.
Further, outer clock circuit is crystal oscillating circuit.
Further, driving enhancing circuit is transistor circuit.
Further, typical jtag interface provide altogether 9 signals include: EMU0, EMU1, VDD, TCK, TCK_RET, TDI,
TDO、TMS、TRST。
Further, dsp chip is connect with typical jtag interface specifically: the port of dsp chip or pin and typical case
The corresponding ports or pin of jtag interface connect.
Further, for EMU0 and EMU1 for emulating to the Target Board of multiprocessor, VDD is the function of level verification
Can, TCK is the clock signal that emulator issues Target Board；TCK_RET is the clock signal that Target Board returns to emulator, and TDI is
Data input, data are transmitted to DSP by typical jtag interface, and TDO is data output, and the end PC is read by jtag interface and comes from DSP
Data；TMS is test pattern selection, and signal is initiated by emulator, and Target Board is receiving end；TRST is initiated by emulator
The signal resetted for JTAG simulation model.
One or more technical solution provided by the present application, has at least the following technical effects or advantages:
The present invention carries out extension signal by pulling up to TMS, TDI, EMU0, EMU1 signal, to TMS, TDI, TDO signal
The transmittability of signal wire can be enhanced in the driving in direction in this way, transmission range is improved, by dsp chip to jtag interface
Peripheral circuit improve, strengthen the driving capability of jtag interface, jtag interface can be supported to the cable of emulator up to 120cm.
Detailed description of the invention
Attached drawing described herein is used to provide to further understand the embodiment of the present invention, constitutes one of the application
Point, do not constitute the restriction to the embodiment of the present invention；
Fig. 1 is the connection schematic diagram of traditional jtag interface and dsp chip；
Fig. 2 is the connection schematic diagram of enhanced jtag interface and dsp chip.
Specific embodiment
To better understand the objects, features and advantages of the present invention, with reference to the accompanying drawing and specific real
Applying mode, the present invention is further described in detail.It should be noted that in the case where not conflicting mutually, the application's
Feature in embodiment and embodiment can be combined with each other.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, still, the present invention may be used also
Implemented with being different from the other modes being described herein in range using other, therefore, protection scope of the present invention is not by under
The limitation of specific embodiment disclosed in face.
Enhanced jtag interface of the present invention based on dsp system solves remote procedure simulation and programming is difficult
Topic, it is described based on the enhanced jtag interface of dsp system include dsp chip, typical jtag interface, pull-up circuit, external clock,
Driving enhancing circuit.
Referring to FIG. 1, Fig. 1 is the connection schematic diagram of dsp chip and typical jtag interface, typical jtag interface includes 1-14
A port, middle port 1 are the end TMS, and port 2 is the end TRST, and port 3 is the end TDI, and port 4 is GND ground terminal, and port 5 is electricity
Source vdd terminal, port 6 are the end NC, and port 7 is the end TDO, and port 8,10,12 is GND ground terminal, and 9 be the end TCK_RET, and 11 are
The end TCK, 13 be the end EMU0, and 14 be the end EMU1.
Dsp chip includes: the end EMU1, the end EMU0, the end TRST, the end TMS, the end TDI, the end TDO, the end TCK, the end TCK_RET；
The port of dsp chip or pin are connect with the corresponding ports of typical jtag interface or pin, and the interface of the two in correspondence with each other, is pressed
It is attached according to the corresponding title of interface or serial number.
Referring to FIG. 2, enhanced jtag interface concrete methods of realizing of the present invention is as follows:
A) voltage on TMS, TDI, EMU0, EMU1 signal wire is drawn to 3.3V.
B) using the TCK-RET of the external clock synchronization DS P set；
C) to TDI, TDO, tms signal does the driving along signal transmission direction.
Pull-up circuit includes: VCC power supply, and 10k resistance, external clock is crystal oscillator, and driving enhancing circuit is triode, wherein
VCC indicates that pull-up circuit power supply, 10K indicate pull-up resistor, external clock, that is, crystal oscillator, and the driving along signal transmission direction enhances electricity
Road, that is, triode is directed toward transmission direction.
Jtag interface provides 9 signals, i.e. EMU0, EMU1, VDD, TCK, TCK_RET, TDI, TDO, TMS and TRST altogether.
For EMU0 and EMU1 for emulating to the Target Board of multiprocessor, the present invention is pulled upward to 3.3V, enhances the drive of its output
Kinetic force；VDD is the function of level verification, and in the present invention, VDD is 5V, i.e., other signals are using 5V level as reference signal；
TCK is the clock signal that emulator issues Target Board；TCK_RET is the clock signal that Target Board returns to emulator, with setting
External clock synchronize the clock of jtag interface, play a correction；TDI is data input, and data are by jtag interface
It is transmitted to DSP, the present invention is pulled upward to 3.3V, while enhancing the driving capability of its output；TDO is data output, and the end PC passes through
Jtag interface reads the data from DSP；TMS is test pattern selection, and signal is initiated by emulator, and Target Board is receiving end,
The present invention is pulled upward to 3.3V, enhances the driving capability of its output；TRST is initiated by emulator for JTAG emulation mould
The signal that formula resets.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (8)
1. a kind of enhanced jtag interface based on DSP, which is characterized in that the enhanced jtag interface includes:
Dsp chip, typical jtag interface, pull-up circuit, external clock, driving enhancing circuit；Wherein, dsp chip and typical case
Jtag interface connection, the end TCK-RET of dsp chip is connected with external clock, the end TMS, the end TDI, EMU0 of typical jtag interface
End, the end EMU1 are equipped with pull-up circuit, pull up to the voltage on signal wire, the end TDI and TMS of typical jtag interface, DSP
The end TDO of chip is equipped with driving enhancing circuit, carries out the driving along signal transmission direction to corresponding signal.
2. the enhanced jtag interface according to claim 1 based on DSP, which is characterized in that pull-up circuit includes pull-up
The port that circuit power VCC and pull-up resistor R, pull-up circuit power supply VCC are pulled up after connecting with pull-up resistor R with corresponding needs
Signal wire connection.
3. the enhanced jtag interface according to claim 1 based on DSP, which is characterized in that the pull-up circuit is to letter
Voltage on number line carries out being pulled to 3.3V.
4. the enhanced jtag interface according to claim 1 based on DSP, which is characterized in that outer clock circuit is crystalline substance
Shake circuit.
5. the enhanced jtag interface according to claim 1 based on DSP, which is characterized in that driving enhancing circuit is three
Pole pipe circuit.
6. the enhanced jtag interface according to claim 1 based on DSP, which is characterized in that typical jtag interface mentions altogether
It include: EMU0, EMU1, VDD, TCK, TCK_RET, TDI, TDO, TMS, TRST for 9 signals.
7. the enhanced jtag interface according to claim 1 based on DSP, which is characterized in that dsp chip and typical case JTAG
Interface connection specifically: the port of dsp chip or pin are connect with the corresponding ports of typical jtag interface or pin.
8. the enhanced jtag interface according to claim 6 based on DSP, which is characterized in that EMU0 and EMU1 for pair
The Target Board of multiprocessor is emulated, and VDD is the function of level verification, and TCK is the clock signal that emulator issues Target Board；
TCK_RET is the clock signal that Target Board returns to emulator, and TDI is data input, and data are transmitted to DSP by typical jtag interface,
TDO is data output, and the data from DSP are read by jtag interface in the end PC；TMS is test pattern selection, and signal is by emulating
Device is initiated, and Target Board is receiving end；TRST is the signal resetted for JTAG simulation model initiated by emulator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811221241.3A CN109408435A (en) | 2018-10-19 | 2018-10-19 | A kind of enhanced jtag interface based on DSP |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811221241.3A CN109408435A (en) | 2018-10-19 | 2018-10-19 | A kind of enhanced jtag interface based on DSP |
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| CN109408435A true CN109408435A (en) | 2019-03-01 |
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| CN201811221241.3A Pending CN109408435A (en) | 2018-10-19 | 2018-10-19 | A kind of enhanced jtag interface based on DSP |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111221767A (en) * | 2020-01-16 | 2020-06-02 | 合肥磐芯电子有限公司 | FLASH interface circuit |
| CN114157339A (en) * | 2021-11-09 | 2022-03-08 | 浙江时空道宇科技有限公司 | Star affair computer and satellite system |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1996274A (en) * | 2006-12-25 | 2007-07-11 | 中国科学院安徽光学精密机械研究所 | JTAG simulation signal intensifier circuit based on high-speed processor |
-
2018
- 2018-10-19 CN CN201811221241.3A patent/CN109408435A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1996274A (en) * | 2006-12-25 | 2007-07-11 | 中国科学院安徽光学精密机械研究所 | JTAG simulation signal intensifier circuit based on high-speed processor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111221767A (en) * | 2020-01-16 | 2020-06-02 | 合肥磐芯电子有限公司 | FLASH interface circuit |
| CN111221767B (en) * | 2020-01-16 | 2021-08-03 | 合肥磐芯电子有限公司 | FLASH interface circuit |
| CN114157339A (en) * | 2021-11-09 | 2022-03-08 | 浙江时空道宇科技有限公司 | Star affair computer and satellite system |
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Application publication date: 20190301 |
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