CN109765482A - A kind of high speed interconnecting test method between multi-chip - Google Patents
A kind of high speed interconnecting test method between multi-chip Download PDFInfo
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- CN109765482A CN109765482A CN201910180305.8A CN201910180305A CN109765482A CN 109765482 A CN109765482 A CN 109765482A CN 201910180305 A CN201910180305 A CN 201910180305A CN 109765482 A CN109765482 A CN 109765482A
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Abstract
The invention discloses a kind of high speed interconnecting test methods between multi-chip to be introduced into mbio_test_top module and be inserted into circuit in the DFT design for Measurability stage;According to circuit diagram, chip is manufactured;Chip is placed on above the board of test machine later, connects the probe above board with chip;Test machine tests chip according to the test vector that outside provides, and carries out loopback test and chip chamber external loopback in chip to chip and tests, and test clock is introduced by PLL, by controlling mbio_test_top module, to control the interconnection communication of chip chamber;Can be with high speed test, the flexibility of test vector is high, can be tested by test machine, and test mode is not limited to, and test process is simple and convenient, flexible, is easy to use and promotes.
Description
Technical field
The present invention relates to a kind of high speed interconnecting test method between multichip interconnection the field of test technology more particularly to multi-chip.
Background technique
With the high speed development of IC design level and technique, the circuit requirement integrated to multi-chip is higher and higher;
In DFT design, the interconnecting test of chip chamber is also an indispensable one side having to take into account that.
Currently popular chip interconnecting test is mainly the mode for using JTAG, is developed based on the agreements such as 1149.1;It lacks
Point be can only low speed test, within usual 50MHz;The flexibility of test vector is poor.It must be produced according to agreement with eda tool
It is raw.
Summary of the invention
The purpose of the present invention is to solve the problems of the prior art, and the mutual tie-in of high speed between a kind of multi-chip proposed
Method for testing.
To achieve the goals above, present invention employs following technical solutions:
A kind of high speed interconnecting test method between multi-chip, specific step is as follows for high speed interconnecting test between the multi-chip:
(1) it in the DFT design for Measurability stage, is introduced into mbio_test_top module and is inserted into circuit;
(2) according to circuit diagram, chip is manufactured, it is spare;
(3) chip is placed on above the board of test machine, connects the probe above board with chip;
(4) test machine tests chip according to the test vector that outside provides, to chip carry out in chip loopback test and
The test of chip chamber external loopback, and test clock is introduced by PLL, by controlling mbio_test_top module, to control chip chamber
Interconnection communication.
It preferably, can be by write circuit rtl code in step (1) when being inserted into mbio_test_top module
When and circuit function function finish writing together insertion circuit in, or function rtl code logic integrate patrolled
After collecting netlist (netlist), it is added in circuit by eda tool or by writing command order.
Preferably, the port fast_clk pin of mbio_test_top module is connected to the output end of PLL in step (1),
The port Tck, rst, cfg_en, tdi, tdo and tx_valid of mbio_test_top module is connected to corresponding outside port
(GPIO) on;The port Ctl_i_* of mbio_test_top module is connected in corresponding high speed I O port.
Preferably, in step (4), in the chip in loopback test, PLL sends test clock signal, mbio_
Test_top module sends data, behind the port IO PAD of chip, and returns in mbio_test_top module, carries out
Observe data.
Preferably, in step (4), in the chip chamber external loopback test, a chip passes through mbio_test_top
PRBS generator in module sends data, and the end IO PAD of another chip is connected to by the port IO PAD of chip
Mouthful, the PRBS checker in the mbio_test_top module of this chip receives data.
Beneficial effects of the present invention: the present invention provides a kind of high speed interconnecting test methods between multi-chip, can survey at a high speed
Examination, the flexibility of test vector is high, can be tested by test machine, and test mode is not limited to, test process is simple and convenient,
Flexibly, it is easy to use and promotes.
It is not directed to part in the device to be the same as those in the prior art or can be realized by using the prior art, structure of the invention
Simply, easy to operate.
Detailed description of the invention
Fig. 1 is the circuit diagram of the detection circuit of high speed interconnecting test method between a kind of multi-chip proposed by the present invention;
Fig. 2 is the mbio_test_top modular circuit of high speed interconnecting test method between a kind of multi-chip proposed by the present invention
Figure;
Fig. 3 is loopback test circuit diagram in the chip of high speed interconnecting test method between a kind of multi-chip proposed by the present invention;
Fig. 4 is the chip chamber external loopback test circuit of high speed interconnecting test method between a kind of multi-chip proposed by the present invention
Figure.
Specific embodiment
To be easy to understand the technical means, the creative features, the aims and the efficiencies achieved by the present invention, below with reference to
Specific embodiment, the present invention is further explained.
Embodiment 1
As shown in Figs. 1-2, a kind of high speed interconnecting test method between multi-chip, the specific step of high speed interconnecting test between multi-chip
It is rapid as follows:
(1) it in the DFT design for Measurability stage, is introduced into mbio_test_top module and is inserted into circuit;
(2) according to circuit diagram, chip is manufactured, it is spare;
(3) chip is placed on above the board of test machine, connects the probe above board with chip;
(4) test machine tests chip according to the test vector that outside provides, to chip carry out in chip loopback test and
The test of chip chamber external loopback, and test clock is introduced by PLL, by controlling mbio_test_top module, to control chip chamber
Interconnection communication.
In step (1) when being inserted into mbio_test_top module, can by when write circuit rtl code and
Circuit function function is finished writing together in insertion circuit, or function rtl code logic synthesis is obtained logic netlist
(netlist) it after, is added in circuit by eda tool or by writing command order.
The port fast_clk pin of mbio_test_top module is connected to the output end of PLL, mbio_ in step (1)
The port Tck, rst, cfg_en, tdi, tdo and tx_valid of test_top module is connected to corresponding outside port (GPIO)
On;The port Ctl_i_* of mbio_test_top module is connected in corresponding high speed I O port.
In step (4), in chip in loopback test, PLL sends test clock signal, mbio_test_top module hair
Data are sent, behind the port IO PAD of chip, and returns in mbio_test_top module, is observed data, such as Fig. 3
It is shown.
In step (4), in the test of chip chamber external loopback, a chip passes through in mbio_test_top module
PRBS generator sends data, and the port IO PAD of another chip, this core are connected to by the port IO PAD of chip
PRBS checker in the mbio_test_top module of piece receives data, as shown in Figure 4.
It should be noted that can be surveyed the present invention provides a kind of high speed interconnecting test method between multi-chip with high speed test
The flexibility for trying vector is high, can be tested by test machine, and test mode is not limited to, and test process is simple and convenient, flexible,
It is easy to use and promotes.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
Anyone skilled in the art in the technical scope disclosed by the present invention, according to the technique and scheme of the present invention and its
Inventive concept is subject to equivalent substitution or change, should be covered by the protection scope of the present invention.
Claims (5)
1. a kind of high speed interconnecting test method between multi-chip, which is characterized in that high speed interconnecting test is specific between the multi-chip
Steps are as follows:
(1) it in the DFT design for Measurability stage, is introduced into mbio_test_top module and is inserted into circuit;
(2) according to circuit diagram, chip is manufactured, it is spare;
(3) chip is placed on above the board of test machine, connects the probe above board with chip;
(4) test machine tests chip according to the test vector that outside provides, and carries out loopback test and chip in chip to chip
Between external loopback test, and test clock is introduced by PLL, by controlling mbio_test_top module, to control the mutual of chip chamber
Connection letter.
2. high speed interconnecting test method between a kind of multi-chip according to claim 1, which is characterized in that in step (1)
When being inserted into mbio_test_top module, can by when write circuit rtl code and circuit function function together
Finish writing insertion circuit in, or function rtl code logic integrate obtain logic netlist (netlist) after, pass through EDA
Tool is added in circuit by writing command order.
3. high speed interconnecting test method between a kind of multi-chip according to claim 1, which is characterized in that in step (1)
The port fast_clk pin of mbio_test_top module is connected to the output end of PLL, the Tck of mbio_test_top module,
The port rst, cfg_en, tdi, tdo and tx_valid is connected on corresponding outside port (GPIO);Mbio_test_top mould
The port Ctl_i_* of block is connected in corresponding high speed I O port.
4. high speed interconnecting test method between a kind of multi-chip according to claim 1, which is characterized in that in step (4),
In the chip in loopback test, PLL sends test clock signal, and mbio_test_top module sends data, passes through chip
It behind the port IO PAD, and returns in mbio_test_top module, is observed data.
5. high speed interconnecting test method between a kind of multi-chip according to claim 1, which is characterized in that in step (4),
In the chip chamber external loopback test, a chip is sent by the PRBS generator in mbio_test_top module
Data are connected to the port IO PAD of another chip, the mbio_test_top mould of this chip by the port IO PAD of chip
PRBS checker in block receives data.
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112748326A (en) * | 2020-12-30 | 2021-05-04 | 上海捷策创电子科技有限公司 | Chip test circuit, device and system |
CN116243147A (en) * | 2023-05-09 | 2023-06-09 | 武汉芯必达微电子有限公司 | PAD function matrix-based integrated control chip peripheral self-test method and device |
US11714128B2 (en) | 2019-12-31 | 2023-08-01 | Kunlunxin Technology (Beijing) Company Limited | Method and apparatus for testing artificial intelligence chip, device and storage medium |
CN117172202A (en) * | 2023-09-05 | 2023-12-05 | 苏州异格技术有限公司 | Core particle self-checking and inter-core particle communication recovery method and device |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1564532A (en) * | 2004-04-09 | 2005-01-12 | 中兴通讯股份有限公司 | Method of testing exchanged chip and related high speed link |
US20050102593A1 (en) * | 2003-11-07 | 2005-05-12 | Ko Jesse J. | Method of testing phase lock loop status during a serializer/deserializer internal loopback built-in self-test |
US20080250289A1 (en) * | 2007-04-03 | 2008-10-09 | International Business Machines Corporation | Method for Performing a Logic Built-in-Self-Test in an Electronic Circuit |
US20110302471A1 (en) * | 2010-06-07 | 2011-12-08 | Stmicroelectronics (Grenoble 2) Sas | Circuitry for built-in self-test |
CN102752125A (en) * | 2011-04-20 | 2012-10-24 | 华为数字技术有限公司 | Fault locating method and device for data link |
US20140122955A1 (en) * | 2012-11-01 | 2014-05-01 | Futurewei Technologies, Inc. | Prbs test memory interface considering ddr burst operation |
CN107408032A (en) * | 2015-03-26 | 2017-11-28 | 英特尔公司 | PRBS pseudo-random bit sequence in interconnection |
-
2019
- 2019-03-11 CN CN201910180305.8A patent/CN109765482A/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050102593A1 (en) * | 2003-11-07 | 2005-05-12 | Ko Jesse J. | Method of testing phase lock loop status during a serializer/deserializer internal loopback built-in self-test |
CN1564532A (en) * | 2004-04-09 | 2005-01-12 | 中兴通讯股份有限公司 | Method of testing exchanged chip and related high speed link |
US20080250289A1 (en) * | 2007-04-03 | 2008-10-09 | International Business Machines Corporation | Method for Performing a Logic Built-in-Self-Test in an Electronic Circuit |
US20110302471A1 (en) * | 2010-06-07 | 2011-12-08 | Stmicroelectronics (Grenoble 2) Sas | Circuitry for built-in self-test |
CN102752125A (en) * | 2011-04-20 | 2012-10-24 | 华为数字技术有限公司 | Fault locating method and device for data link |
US20140122955A1 (en) * | 2012-11-01 | 2014-05-01 | Futurewei Technologies, Inc. | Prbs test memory interface considering ddr burst operation |
CN107408032A (en) * | 2015-03-26 | 2017-11-28 | 英特尔公司 | PRBS pseudo-random bit sequence in interconnection |
Non-Patent Citations (1)
Title |
---|
詹遥: ""SERDES芯片的验证与测试研究"", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11714128B2 (en) | 2019-12-31 | 2023-08-01 | Kunlunxin Technology (Beijing) Company Limited | Method and apparatus for testing artificial intelligence chip, device and storage medium |
CN112748326A (en) * | 2020-12-30 | 2021-05-04 | 上海捷策创电子科技有限公司 | Chip test circuit, device and system |
CN116243147A (en) * | 2023-05-09 | 2023-06-09 | 武汉芯必达微电子有限公司 | PAD function matrix-based integrated control chip peripheral self-test method and device |
CN116243147B (en) * | 2023-05-09 | 2023-08-18 | 武汉芯必达微电子有限公司 | PAD function matrix-based integrated control chip peripheral self-test method and device |
CN117172202A (en) * | 2023-09-05 | 2023-12-05 | 苏州异格技术有限公司 | Core particle self-checking and inter-core particle communication recovery method and device |
CN117172202B (en) * | 2023-09-05 | 2024-05-07 | 苏州异格技术有限公司 | Core particle self-checking and inter-core particle communication recovery method and device |
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