CN109765482A

CN109765482A - A kind of high speed interconnecting test method between multi-chip

Info

Publication number: CN109765482A
Application number: CN201910180305.8A
Authority: CN
Inventors: 何立柱; 冯建华
Original assignee: Shixin Electronic Technology (wuxi) Co Ltd
Current assignee: Shixin Electronic Technology (wuxi) Co Ltd
Priority date: 2019-03-11
Filing date: 2019-03-11
Publication date: 2019-05-17

Abstract

The invention discloses a kind of high speed interconnecting test methods between multi-chip to be introduced into mbio_test_top module and be inserted into circuit in the DFT design for Measurability stage；According to circuit diagram, chip is manufactured；Chip is placed on above the board of test machine later, connects the probe above board with chip；Test machine tests chip according to the test vector that outside provides, and carries out loopback test and chip chamber external loopback in chip to chip and tests, and test clock is introduced by PLL, by controlling mbio_test_top module, to control the interconnection communication of chip chamber；Can be with high speed test, the flexibility of test vector is high, can be tested by test machine, and test mode is not limited to, and test process is simple and convenient, flexible, is easy to use and promotes.

Description

A kind of high speed interconnecting test method between multi-chip

Technical field

The present invention relates to a kind of high speed interconnecting test method between multichip interconnection the field of test technology more particularly to multi-chip.

Background technique

With the high speed development of IC design level and technique, the circuit requirement integrated to multi-chip is higher and higher； In DFT design, the interconnecting test of chip chamber is also an indispensable one side having to take into account that.

Currently popular chip interconnecting test is mainly the mode for using JTAG, is developed based on the agreements such as 1149.1；It lacks Point be can only low speed test, within usual 50MHz；The flexibility of test vector is poor.It must be produced according to agreement with eda tool It is raw.

Summary of the invention

The purpose of the present invention is to solve the problems of the prior art, and the mutual tie-in of high speed between a kind of multi-chip proposed Method for testing.

To achieve the goals above, present invention employs following technical solutions:

A kind of high speed interconnecting test method between multi-chip, specific step is as follows for high speed interconnecting test between the multi-chip:

(1) it in the DFT design for Measurability stage, is introduced into mbio_test_top module and is inserted into circuit；

(2) according to circuit diagram, chip is manufactured, it is spare；

(3) chip is placed on above the board of test machine, connects the probe above board with chip；

(4) test machine tests chip according to the test vector that outside provides, to chip carry out in chip loopback test and The test of chip chamber external loopback, and test clock is introduced by PLL, by controlling mbio_test_top module, to control chip chamber Interconnection communication.

It preferably, can be by write circuit rtl code in step (1) when being inserted into mbio_test_top module When and circuit function function finish writing together insertion circuit in, or function rtl code logic integrate patrolled After collecting netlist (netlist), it is added in circuit by eda tool or by writing command order.

Preferably, the port fast_clk pin of mbio_test_top module is connected to the output end of PLL in step (1), The port Tck, rst, cfg_en, tdi, tdo and tx_valid of mbio_test_top module is connected to corresponding outside port (GPIO) on；The port Ctl_i_* of mbio_test_top module is connected in corresponding high speed I O port.

Preferably, in step (4), in the chip in loopback test, PLL sends test clock signal, mbio_ Test_top module sends data, behind the port IO PAD of chip, and returns in mbio_test_top module, carries out Observe data.

Preferably, in step (4), in the chip chamber external loopback test, a chip passes through mbio_test_top PRBS generator in module sends data, and the end IO PAD of another chip is connected to by the port IO PAD of chip Mouthful, the PRBS checker in the mbio_test_top module of this chip receives data.

Beneficial effects of the present invention: the present invention provides a kind of high speed interconnecting test methods between multi-chip, can survey at a high speed Examination, the flexibility of test vector is high, can be tested by test machine, and test mode is not limited to, test process is simple and convenient, Flexibly, it is easy to use and promotes.

It is not directed to part in the device to be the same as those in the prior art or can be realized by using the prior art, structure of the invention Simply, easy to operate.

Detailed description of the invention

Fig. 1 is the circuit diagram of the detection circuit of high speed interconnecting test method between a kind of multi-chip proposed by the present invention；

Fig. 2 is the mbio_test_top modular circuit of high speed interconnecting test method between a kind of multi-chip proposed by the present invention Figure；

Fig. 3 is loopback test circuit diagram in the chip of high speed interconnecting test method between a kind of multi-chip proposed by the present invention；

Fig. 4 is the chip chamber external loopback test circuit of high speed interconnecting test method between a kind of multi-chip proposed by the present invention Figure.

Specific embodiment

To be easy to understand the technical means, the creative features, the aims and the efficiencies achieved by the present invention, below with reference to Specific embodiment, the present invention is further explained.

Embodiment 1

As shown in Figs. 1-2, a kind of high speed interconnecting test method between multi-chip, the specific step of high speed interconnecting test between multi-chip It is rapid as follows:

(2) according to circuit diagram, chip is manufactured, it is spare；

In step (1) when being inserted into mbio_test_top module, can by when write circuit rtl code and Circuit function function is finished writing together in insertion circuit, or function rtl code logic synthesis is obtained logic netlist (netlist) it after, is added in circuit by eda tool or by writing command order.

The port fast_clk pin of mbio_test_top module is connected to the output end of PLL, mbio_ in step (1) The port Tck, rst, cfg_en, tdi, tdo and tx_valid of test_top module is connected to corresponding outside port (GPIO) On；The port Ctl_i_* of mbio_test_top module is connected in corresponding high speed I O port.

In step (4), in chip in loopback test, PLL sends test clock signal, mbio_test_top module hair Data are sent, behind the port IO PAD of chip, and returns in mbio_test_top module, is observed data, such as Fig. 3 It is shown.

In step (4), in the test of chip chamber external loopback, a chip passes through in mbio_test_top module PRBS generator sends data, and the port IO PAD of another chip, this core are connected to by the port IO PAD of chip PRBS checker in the mbio_test_top module of piece receives data, as shown in Figure 4.

It should be noted that can be surveyed the present invention provides a kind of high speed interconnecting test method between multi-chip with high speed test The flexibility for trying vector is high, can be tested by test machine, and test mode is not limited to, and test process is simple and convenient, flexible, It is easy to use and promotes.

The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto, Anyone skilled in the art in the technical scope disclosed by the present invention, according to the technique and scheme of the present invention and its Inventive concept is subject to equivalent substitution or change, should be covered by the protection scope of the present invention.

Claims

1. a kind of high speed interconnecting test method between multi-chip, which is characterized in that high speed interconnecting test is specific between the multi-chip Steps are as follows:

(2) according to circuit diagram, chip is manufactured, it is spare；

(4) test machine tests chip according to the test vector that outside provides, and carries out loopback test and chip in chip to chip Between external loopback test, and test clock is introduced by PLL, by controlling mbio_test_top module, to control the mutual of chip chamber Connection letter.

2. high speed interconnecting test method between a kind of multi-chip according to claim 1, which is characterized in that in step (1) When being inserted into mbio_test_top module, can by when write circuit rtl code and circuit function function together Finish writing insertion circuit in, or function rtl code logic integrate obtain logic netlist (netlist) after, pass through EDA Tool is added in circuit by writing command order.

3. high speed interconnecting test method between a kind of multi-chip according to claim 1, which is characterized in that in step (1) The port fast_clk pin of mbio_test_top module is connected to the output end of PLL, the Tck of mbio_test_top module, The port rst, cfg_en, tdi, tdo and tx_valid is connected on corresponding outside port (GPIO)；Mbio_test_top mould The port Ctl_i_* of block is connected in corresponding high speed I O port.

4. high speed interconnecting test method between a kind of multi-chip according to claim 1, which is characterized in that in step (4), In the chip in loopback test, PLL sends test clock signal, and mbio_test_top module sends data, passes through chip It behind the port IO PAD, and returns in mbio_test_top module, is observed data.

5. high speed interconnecting test method between a kind of multi-chip according to claim 1, which is characterized in that in step (4), In the chip chamber external loopback test, a chip is sent by the PRBS generator in mbio_test_top module Data are connected to the port IO PAD of another chip, the mbio_test_top mould of this chip by the port IO PAD of chip PRBS checker in block receives data.