CN107340467A - Test system - Google Patents
Test system Download PDFInfo
- Publication number
- CN107340467A CN107340467A CN201710536672.8A CN201710536672A CN107340467A CN 107340467 A CN107340467 A CN 107340467A CN 201710536672 A CN201710536672 A CN 201710536672A CN 107340467 A CN107340467 A CN 107340467A
- Authority
- CN
- China
- Prior art keywords
- data
- circuit
- integrated circuit
- test
- test system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318544—Scanning methods, algorithms and patterns
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31912—Tester/user interface
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a kind of test system.The test system includes circuit board and electronic installation.The circuit board includes test system, joint test (JTAG) interface, and scan chain circuits.Scan chain circuits include multiple scan chains, and are coupled to test system and joint test interface, and each of which scan chain includes multiple scanning D flip-flops.Electronic installation couples the small interface of combined testing action, to test test system.
Description
Technical field
The invention mainly relates to sweep test (Scan testing) technology, more particularly to pass through joint test (Joint
Test Action Group, JTAG) interface carry out chip sweep test scan testing techniques.
Background technology
At integrated circuit (IC)) in manufacturing process, all there is the needs eliminated the false and retained the true, so needing to use integrated circuit
Auto-Test System (Automatic Test System) detect integrated circuit function integrality, screen defect ware, prevent into
Enter next procedure, it is ensured that integrated circuit manufactures quality, reduces the manufacturing expense of redundancy.
One of function of integrated circuit automatic testing system is to be scanned test (Scan testing), and sweep test is
A kind of method of testing for configuring scan chain (scan chain) detection IC interior logical relation on the integrated, such as
IC interior is detected with the presence or absence of short circuit, open circuit, delay etc..
Fig. 1 is the block diagram using integrated circuit automatic testing system, as shown in figure 1, the test system 100 includes circuit
Plate 101, to-be-measured integrated circuit 103 and integrated circuit automatic testing machine (Automatic Test Equipment, ATE) 105.
To-be-measured integrated circuit 103 is placed on circuit board 101, automatic by multiple data-interfaces 104 and the integrated circuit of circuit board 101
Test machine 105 is connected, the parallel test instruction for reading the output of integrated circuit automatic testing machine 105, and is connect from the multiple data
104 parallel output sweep test results of mouth.
However, integrated circuit automatic testing system is extremely complex expensive and needs use specially in fixed venue and test environment
With computer, therefore in the case where needing the to-be-measured integrated circuit for being scanned test more, IC design life is influenceed
Produce the cycle, it is therefore desirable to develop it is a kind of being capable of scanning test function that is compatible but not exclusively relying on integrated circuit Auto-Test System
Another scan test system.
The content of the invention
In view of above mentioned problem, the invention provides a kind of compliant joint test (JTAG) interface to carry out IC scanning
The test system of test.
According to an embodiment of the invention, the test system, compliant joint test pattern and integrated circuit automatic testing mould
Formula, the test system include processor, interface convertor, and circuit board, and wherein processor passes through interface convertor and circuit
Plate realizes data exchange.The circuit board includes joint test interface, integrated circuit automatic testing system interface, the first deposit chain electricity
Road, the second deposit chain circuit, to-be-measured integrated circuit；And scan chain circuits.
According to one embodiment of the invention, when the test system is in joint test pattern, what circuit board included first posts
Data of the chain circuit selection from joint test interface are deposited, are exported to above-mentioned scan chain circuits and above-mentioned to-be-measured integrated circuit, with
And the second deposit chain circuit that circuit board includes, also by from the test data that the scan chain circuits obtain to the joint test
Interface exports.
According to one embodiment of the invention, when the test system is in integrated circuit automatic testing pattern, first deposit
Chain circuit selection receives data from integrated circuit automatic testing system interface, exports to above-mentioned scan chain circuits and above-mentioned collection to be measured
Also second data are exported into circuit, and the second deposit chain circuit to the integrated circuit automatic testing system interface.
According to one embodiment of the invention, processor receives sweep test result, judge inside to-be-measured integrated circuit whether
It is faulty, when processor judges that to-be-measured integrated circuit does not have trouble point, judge to-be-measured integrated circuit for qualified circuit.
According to one embodiment of the invention, when processor judges the faulty point of to-be-measured integrated circuit, integrated electricity to be measured is judged
Road is faulty circuit, and processor is traced to the source to the to-be-measured integrated circuit according to sweep test result, generates a model, and mark event
Barrier point position, so that user decides whether to repair.
On other additional features and advantages of the invention, those skilled in the art are not departing from the spirit and model of the present invention
In enclosing, it should can do a little change according to the test system disclosed in this case embodiment and be obtained with retouching.
Brief description of the drawings
Fig. 1 is the block diagram using integrated circuit automatic testing system 100.
Fig. 2 is the block diagram of the test system 200 described in one embodiment of the invention.
Fig. 3 is the schematic diagram of the jtag interface 221 described in one embodiment of the invention.
Fig. 4 is the schematic diagram of the first JTAG deposit chain circuits 222 described in one embodiment of the invention.
Fig. 5 is the schematic diagram of the scan chain circuits 223 described in one embodiment of the invention.
Fig. 6 is the schematic diagram of the 2nd JTAG deposit chain circuits 224 described in one embodiment of the invention.
Fig. 7 is the schematic diagram of the processor 210 described in one embodiment of the invention.
Embodiment
Described by this section is preferred embodiment of the present invention, it is therefore intended that illustrates the spirit of the present invention and is not used to
Protection scope of the present invention is limited, what protection scope of the present invention should be defined depending on appended claims is defined.
Test system proposed by the invention, has ATE tests concurrently and jtag test both of which, adaptive surface are wider.User
Can be when to-be-measured integrated circuit be more, by processor, such as personal computer, anywhere directly to collection to be measured
Test, and the state of the model intuitive judgment to-be-measured integrated circuit using generation are scanned into circuit.User can also treat
When survey integrated circuit is less, directly complete to test the global function of to-be-measured integrated circuit using ATE test.
Fig. 2 is the block diagram of the test system 200 described in one embodiment of the invention.As shown in Fig. 2 test system 200
Circuit board 220 and interface conversion including processor 210, the data-interface 104 for retaining former integrated circuit automatic testing system
Device 230.Joint test (Joint Test Action Group, JTAG) interface 221 is equipped with circuit board 220, the first JTAG is posted
Deposit chain circuit 222, scan chain circuits 223, the 2nd JTAG deposit chain circuits 224, and to-be-measured integrated circuit 225.Joint test
Interface is also known as jtag interface, and JTAG is a kind of boundary scan testing standard formulated in IEEE 1149.1.Interface convertor
230 are respectively coupled to the jtag interface 221 on processor 210 and circuit board 220, and interface convertor 230 includes protocol conversion
Chip 231 is to support the communication between processor 210 and jtag interface 221, for example, working as on processor 210, there is a USB to connect
Mouthful, then protocol conversion chip 231 is USB-JTAG protocol conversion chips.
Processor 210 is connected to circuit board 220 by interface convertor 230, and data Data is write to jtag interface 221,
Jtag interface 221 is respectively connecting to the first deposit chain circuit 222 and the second deposit chain circuit 224, to the first deposit chain circuit
222 output data TDI, and read data TDO from the second deposit chain circuit 224.First deposit chain circuit 222 is connected to collection to be measured
Into circuit 225, treated to the output mode control signal MCtr of to-be-measured integrated circuit 225, mode control signal MCtr for control
Integrated circuit 225 is surveyed under the pattern of needs.First deposit chain circuit 222 is connected to scan chain circuits 223, to scan chain circuits
223 output clock signal Gclk and initializing signal Rst.The first deposit chain circuit 222 is also attached to the second deposit chain circuit
224, pour into data TDI to the second deposit chain circuit 224 and promote the output signal TDO of the second deposit chain circuit 224.Scan chain circuits
223 are connected to to-be-measured integrated circuit 225, the second deposit chain circuit 224, and the first deposit chain circuit 222.Scan chain electricity
Road 223 receives the data that the first deposit chain circuit 222 is transmitted through coming, in the case where the data that the first deposit chain circuit 222 is transmitted through urge
The internal logic relation of to-be-measured integrated circuit 225 is read, and test result SData1-SDataM is exported to the 2nd JTAG and deposits chain
Circuit 224.Now, the first deposit chain circuit 222 pours into data TDI to the second deposit chain circuit 224 and promotes the second deposit chain electric
Road 224 constantly outputs test result TDO to jtag interface 221.
According to one embodiment of the invention, when being scanned test to to-be-measured integrated circuit 225, processor 210 is by connecing
The data Data that mouth converter 230 transmits to jtag interface 221 includes test mode select signal TMS, test clock signal
TCK, test reset signal TRST, and input signal of test data TDI.Jtag interface 221 receives data Data, and by data
Input signal of test data TDI in Data is distributed to first and is deposited chain circuit 222, and pattern is further comprises in input signal TDI
Control signal MCtr, clock signal Gclk and initializing signal Rst, enter to to-be-measured integrated circuit 225 and scan chain circuits 223
Row is set and initialization.Other data are further comprises in input signal TDI, scan chain circuits 223 is urged and reads integrated electricity to be measured
The internal logic relation on road 225, and transmit sweep test result SData1-SDataM to the 2nd JTAG deposit chain circuits 224.The
Two JTAG deposit chain circuit 224 and arrange sweep test result SData1-SDataM orders, and output signal TDO to JTAG connects
Mouth 221, passes through interface 230 again in the inter-process of jtag interface 221 into final output signal TDOL, final output signal TDOL
Reach processor 210.
Fig. 3 is the schematic diagram of the jtag interface 221 described in one embodiment of the invention.As shown in figure 3, jtag interface 221 wraps
Include test access port controller 310, order register decoder 320, multiple test data register 331-33n, the first multichannel
The MUX 350 of selector 340 and second.
As shown in figure 3, the test access port controller 310 that jtag interface 221 includes is received by interface convertor 230
The test mode select signal TMS that processor 210 issues, test clock signal TCK, and test reset signal TRST, output
To the control signal of order register decoder 320
CTRIR, to multiple test data register 331-33n control signal CTRDR, to the second MUX 350
Control signal SEL2, and test clock signal TCK.Order register decoder 320 is respectively coupled to test access port control
Device 310 processed, and multiple test data registers 330.Order register decoder 320 receives test access port controller 310
The control signal CTRIR sent, built-in command is updated under control signal CTRIR control, send enable signal EN1-ENn extremely
Multiple test data register 331-33n, enable corresponding test data register.Order register decoder 320 also receives survey
Try data input signal TDI and export selection control signal SEL1 to the first MUX 340.Multiple test data registers
331-33n is respectively coupled to test access port controller 310, order register decoder 320, and the first MUX
340.Each test data register in enabled state receives the control signal that test access port controller 310 issues
CTRDR, receive, store under control signal CTRDR control, and allocation for test data input signal TDI to first is deposited
Chain circuit 222, the deposit chain circuit 224 of storage second returns the test result output signal TDO to come, and each ties test
Fruit output signal TDO1-TDOn is exported to the first MUX 340.First MUX 340 is respectively coupled to instruction and posted
Deposit decoder 320, multiple test data register 331-33n, and the second MUX 350.First MUX 340
TDOx all the way in selection signal TDO1-TDOn in the presence of the control signal SEL1 that order register decoder 320 issues is defeated
Go out to the second MUX 350.Second MUX 350 is respectively coupled to the first MUX 340, and order register is translated
Code device 320, test access port controller 310, and interface convertor 230.Second MUX 350 is in test access terminals
Under the control signal SEL2 controls that mouthful controller 310 issues, signal TDOx that the first MUX 340 is exported, with instruction
The input signal of test data TDI that register-translator 320 exports is compared, and filters out the signal TDI contained in signal TDOx
Data, export final testing result output signal TDOL, and processor 210 be back to by interface convertor 230.
Fig. 4 is the schematic diagram of the first JTAG deposit chain circuits 222 described in one embodiment of the invention.As shown in figure 4, first
JTAG deposit chain circuits 222 are made up of the register 411-41N and multiple MUX 421-42N of multiple series connection.It is multiple
The register of series connection is sequentially connected, and the register 411 of front end receives input signal of test data TDI, successively to follow-up deposit
Device 412-41N is transmitted, and is sent to multiple MUXs, and last register 41N exports signal TDI to the 2nd JTAG
Chain circuit 224 is deposited, promotes the 2nd JTAG deposit chain circuits 224 to output test result output signal TDO.Each MUX
The input signal of test data TDI of series connection register corresponding to can selecting or the number from former integrated circuit automatic testing system
It is used as according to the data of interface 104 to scan chain circuits 223, and the output to to-be-measured integrated circuit 225.According to the one of the present invention
Embodiment, register 411-41N can be D flip-flops.
It is more when test system of the present invention is in JTAG mode as shown in figure 4, according to one embodiment of the invention
Individual MUX 421-42N selections send input signal of test data TDI to scan chain circuits 223 and integrated electricity to be measured
Road 225.When the sweep test that test system of the present invention performs is in ATE patterns, multiple selections of MUX 420 are certainly
The data output that the data-interface 104 of former integrated circuit automatic testing system obtains is and to be measured integrated to scan chain circuits 223
Circuit 225.
As shown in figure 4, according to one embodiment of the invention, some registers need to carry other functions, for example, register
411 receive the mode control signal MCtr that signal TDI is included with register 412, now register 411 and register 412
Mode control signal MCtr of the storage to to-be-measured integrated circuit 225 is exclusively used in, for MUX 421 and MUX 422
Selection, now MUX 421 also receives the pattern that the data-interface 104 of former integrated circuit automatic testing system is sent
Data are set, when the scan test system is in JTAG mode, the mould that the mask register 411 of MUX 421 transmits
Formula control signal MCtr, which exports, to to-be-measured integrated circuit 225, makes to-be-measured integrated circuit 225 be in the state for being adapted to sweep test.
Similarly, register 413 is exclusively used in clock signal Gclk of the storage to scan chain circuits 223, so that each D in scan chain circuits
D-flip flop is controlled by same clock signal.Register 414 is exclusively used in initializing signal Rst of the storage to scan chain circuits 223,
Before sweep test is started every time, each register internal data of initialization scan chain circuit 223.Certainly, carry it is above-mentioned other
The quantity and function of the register of function specify with some or certain it is several, need to be determined on a case-by-case basis.Multiple series connection
Register 411-41N in, in addition to needing to carry the register of other above-mentioned functions, other registers be used for store signal
Other data in TDI.Corresponding, also just selection corresponding data transmits downwards MUX 421-42N.
Fig. 5 is the schematic diagram of the scan chain circuits 223 described in one embodiment of the invention.As shown in figure 5, scan chain circuits
223 include multiple scan chains, and every scan chain includes the scanning D flip-flop of multiple series connection, is represented below with SDFF, often
Individual SDFF, which is both connected to to-be-measured integrated circuit 225, to be needed in place of detecting logical relation, and each SDFF is all by clock signal Gclk
Controlled.When each sweep test starts, scan chain circuits latch all SDFF in the presence of initializing signal Rst
Data are put 1 or set to 0, then will be from to-be-measured integrated circuit 225 under the urging of other data of the MUX output shown in Fig. 4
The internal logic value of acquisition, i.e. test result SData1-SDataM export to the 2nd JTAG and deposit chain circuit 224.According to this hair
A bright embodiment, the logical relation situation that test result SData1-SDataM reflects inside to-be-measured integrated circuit 225, such as
Whether short circuit, open circuit, logic error etc. are had.According to another embodiment of the present invention, the scan chain circuits 223 shown in Fig. 5
D flip-flop contained by to-be-measured integrated circuit 225 itself can directly be taken, is in series with reference to MUX, therefore, scan chain electricity
Road 223 can be built in to-be-measured integrated circuit 225.
Fig. 6 is the schematic diagram of the 2nd JTAG deposit chain circuits 224 described in one embodiment of the invention.As shown in fig. 6, second
JTAG deposit chain circuits 224 are made up of the register and multiple MUXs of multiple series connection.
As shown in fig. 6, when the test system is in JTAG mode, the register 611-61M of multiple series connection is sequentially connected, right
The test result data SData1-SDataM of scan chain circuits 223 should be obtained, and is not stopped in the first JTAG deposit chain circuits 222
Pour under data TDI driving, serial arrangement test result data SData1-SDataM and the output signal that outputs test result
TDO is to test data register 330.Because the last register 61M also receives the signal TDI poured into, so as to export
Test result output signal TDO is pushed successively to the direction of register 611, so the test result data except serial arrangement
Outside SData1-SDataM, the signal TDI poured into is also mingled with signal TDO.Pushed away to ensure that signal TDI only plays trigger data
The effect sent, the output signal TDO that outputs test result is not influenceed, according to one embodiment of the invention, the signal TDI poured into is carried
One flag bit, can be identified by the second MUX 350 in jtag interface 221 so that judge it is invalid.According to the present invention's
Another embodiment, register 611-61M number is M, therefore often after M data of reading, the second multichannel in jtag interface 221
Selector 350 abandons 1 signal poured into TDI data.According to another embodiment of the present invention, second in jtag interface 221
The direct comparison signal TDO of MUX 350 and signal TDI, filters out the TDI data included in signal TDO.According to the present invention
An embodiment, register 611-61M can be D flip-flop.
As shown in fig. 6, when the test system is in ATE patterns, test is tied by multiple MUX 621-62M selections
The direct parallel outputs of fruit data SData1-SdataM to former integrated circuit automatic testing system data-interface 104.
According to an embodiment of the invention, the test system also includes controller, is easy to user to select the behaviour of the test system
Operation mode, the controller produce control signal S, and control signal S acts on N number of multichannel contained by the first deposit chain circuit 222
Selector 421-42N, and M MUX 621-62M contained by the second deposit chain circuit 224.When user's selection should
Test system is placed in JTAG mode, and control signal S controls N number of MUX 421-42N selections that test data is inputted into letter
Number TDI sends scan chain circuits 223 and to-be-measured integrated circuit 225 to, and control signal S also controls M MUX
621-62M is in disabled state.The controller can be placed on circuit board 220, can also be placed in outside circuit board 220.
When the test system is placed in ATE patterns by user's selection, signal S controls N number of MUX 421-42N selections certainly
The data output that the data-interface 104 of former integrated circuit automatic testing system obtains is and to be measured integrated to scan chain circuits 223
Circuit 225, signal S also M MUX 621-62M of enable, MUX 621-62M is set to obtain sweep test result
And it is transferred to the data-interface 104 of former integrated circuit automatic testing system.
According to one embodiment of the invention, to meet the sweep test demand of various to-be-measured integrated circuits, it is foregoing to retain original
The circuit board 220 of the data-interface of integrated circuit automatic testing system can be extended, i.e., multiple circuit boards 220 can be concatenated to prop up
Hold the sweep test of large-scale to-be-measured integrated circuit.
According to one embodiment of the invention, the test access port controller 310 included by jtag interface 221 can be to
One JTAG deposit chain circuit 222 and the 2nd JTAG deposit chain circuits 224 export test clock signal TCK, test clock letter
Each register that number TCK is acted on the first JTAG deposit chain circuit 222 and the 2nd JTAG deposit chain circuits 224.
According to one embodiment of the invention, the first JTAG deposit chain circuits 222 and the 2nd JTAG is deposited in chain circuit 224
The register of contained multiple series connection can be built in multiple test data register 331-33n contained by jtag interface 221.
According to one embodiment of the invention, directly can also be posted using multiple test datas included by jtag interface 221
String of the resource contained by as the first JTAG deposit chain circuit 222 and the 2nd JTAG deposit chain circuits 224 in storage 331-33n
The register of connection.
According to one embodiment of the invention, jtag interface 221 receives test result signal TDO, in filtration treatment signal TDO
Contained TDI data, signal TDOL is obtained, and signal TDOL is back to processor 210.Processor 210 is according to receiving
Signal TDOL judges whether broken down in to-be-measured integrated circuit 225, i.e., internal whether to have a logical relation mistake, such as short circuit,
Open circuit etc., so as to decide whether to establish integrated circuit model, reduction trouble point position is further processed for user.
Fig. 7 is the schematic diagram of the processor 210 described in one embodiment of the invention.As shown in fig. 7, processor 210 includes determining
Position module 701, model generation module 703, and human-computer interaction interface 705.
As shown in fig. 7, according to one embodiment of the invention, if failure is not present in to-be-measured integrated circuit 225, judgement is treated
Survey integrated circuit 225 is qualified circuit.If to-be-measured integrated circuit 225 has failure, believed in real time by locating module 701
Number TDOL, after confirming that invalid TDI signal data all filter out, traces to the source according to TDOL transmission order and draws in scan chain circuits
Every SDFF coordinate, and the coordinate of every SDFF is sent to model generation module 703 in real time.Model generation module 703
The every SDFF to be traced to the source according to locating module 701 coordinate real-time simulation obtains to-be-measured integrated circuit internal logic relation solid
Model, and position of failure point is marked on the three-dimensional model, directly shown on human-computer interaction interface 705 to user, by user
Determine whether the point of the internal logic relation mistake is convenient to repair.
In summary, test system proposed by the invention, ATE tests and jtag test both of which, adaptive surface are had concurrently
It is wider.When user can be more or larger in to-be-measured integrated circuit, by processor, such as personal computer, any
Place is directly scanned test, and the shape of the model intuitive judgment to-be-measured integrated circuit using generation to to-be-measured integrated circuit
State.When user can also be less or less in to-be-measured integrated circuit, directly completed using ATE test to be measured integrated
The global function test of circuit.
" embodiment " that is previously mentioned in this specification or " embodiment ", represent the specific spy relevant with embodiment
Sign, structure or characteristic are included at least one embodiment according to the present invention, it is not intended that they are present in each reality
Apply in example.Therefore, " in one embodiment " or " in embodiment " phrase that different places occur in this manual is not necessarily
So represent the identical embodiment of the present invention.
Above paragraph is described using a variety of aspects.Obvious, teaching herein may be implemented in a variety of ways, and in example
Disclosed any certain architectures or function are only representational situation.According to teaching herein, any those skilled in the art should
Understanding can independently implement in each aspect disclosed herein or two or more aspects can merge implementation.
Although the present invention is disclosed as above with preferred embodiment, but it is not limited to the present invention, any this area
Technical staff without departing from the spirit and scope of the present invention, should can make a little change and retouching, therefore the present invention
What protection domain should be defined depending on appended claims is defined.
Claims (10)
1. a kind of test system, compliant joint test pattern and integrated circuit automatic testing pattern, including：
Processor, export the first data；And
Circuit board, receives first data, and the circuit board includes：
Scan chain circuits, to-be-measured integrated circuit is scanned, and produce the second data, each of which scan chain includes multiple serial scans
D flip-flop；And
Joint test interface, the 3rd data are returned to above-mentioned processor.
2. test system as claimed in claim 1, wherein the board receiver control signal, to control the test system
In joint test pattern or integrated circuit automatic testing pattern.
3. test system as claimed in claim 2, wherein when the test system is in integrated circuit automatic testing pattern, it is described
Circuit board also includes：
Integrated circuit automatic testing system interface, the 4th data are obtained from integrated circuit automatic testing machine, and to integrated circuit certainly
Dynamic test machine exports second data.
First deposit chain circuit, the first deposit chain circuit receive the described 4th from the integrated circuit automatic testing system interface
Data, export to the scan chain circuits and the to-be-measured integrated circuit；And
Second deposit chain circuit, the second deposit chain circuit obtain second data from the scan chain circuits, and to described
Joint test interface exports second data.
4. test system as claimed in claim 2, wherein when the test system is in joint test pattern, the circuit board is also
Including：
First deposit chain circuit, the first data described in the first deposit chain circuit from the joint test interface, output is extremely
The scan chain circuits and the to-be-measured integrated circuit；And
Second deposit chain circuit, the second deposit chain circuit obtain second data from the scan chain circuits, and to described
Joint test interface exports second data.
5. test system as claimed in claim 4, first data reach scan chain circuits and described to be measured integrated
Circuit, pattern residing for the to-be-measured integrated circuit is controlled, and initialize the scan chain circuits.
6. test system as claimed in claim 4, second packet containing the scan chain circuits collect described in treat
Survey IC interior logical value.
7. test system as claimed in claim 4, first data serial transmission promotes this to the second deposit chain circuit
Second deposit chain circuit exports second data to joint test interface serial, and second packet is containing part first number
According to value.
8. test system as claimed in claim 7, wherein the joint test interface also includes：
Test data register, first data are exported to the described first deposit chain circuit, and receive the second deposit chain
Second data of circuit output；And
MUX, the value for part first data that second data are included is filtered out, exports the 3rd data,
And the 3rd data are returned to the processor.
9. test system as claimed in claim 1, wherein the processor receives the 3rd data, judge the collection to be measured
Inside into circuit whether faulty point, it is when the processor judges that the to-be-measured integrated circuit does not have the trouble point, then described to treat
Survey integrated circuit is qualified circuit.
10. test system as claimed in claim 9, wherein when the processor judges that the to-be-measured integrated circuit has the failure
Point, then the to-be-measured integrated circuit is faulty circuit, and the processor is traced to the source to the to-be-measured integrated circuit according to the 3rd data, raw
Into a model, and position of failure point is marked, so that user observes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710536672.8A CN107340467B (en) | 2017-07-04 | 2017-07-04 | Test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710536672.8A CN107340467B (en) | 2017-07-04 | 2017-07-04 | Test system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107340467A true CN107340467A (en) | 2017-11-10 |
| CN107340467B CN107340467B (en) | 2020-02-07 |
Family
ID=60219050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710536672.8A Active CN107340467B (en) | 2017-07-04 | 2017-07-04 | Test system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107340467B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020043014A1 (en) * | 2018-08-28 | 2020-03-05 | Changxin Memory Technologies, Inc. | Boundary test circuit, memory and boundary test method |
| CN112290932A (en) * | 2020-09-30 | 2021-01-29 | 上海兆芯集成电路有限公司 | Circuit and test circuit thereof |
| CN112345925A (en) * | 2020-10-30 | 2021-02-09 | 上海兆芯集成电路有限公司 | Scan chain control circuit |
| TWI760400B (en) * | 2017-12-15 | 2022-04-11 | 英業達股份有限公司 | System for using different chains to test differential signal and method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1270671A (en) * | 1997-09-16 | 2000-10-18 | 泰拉丁公司 | Test system for integrated circuits using a single memory for both the parallel and scan modes of testing |
| CN101446624A (en) * | 2008-12-29 | 2009-06-03 | 华为技术有限公司 | Linking method of combined test group link and link device of combined test group |
| JP2010271126A (en) * | 2009-05-20 | 2010-12-02 | Mitsubishi Electric Corp | Boundary scan circuit |
| CN104237666A (en) * | 2013-06-21 | 2014-12-24 | 京微雅格（北京）科技有限公司 | Method for testing devices in series connection chain of joint test action group |
| CN104422878A (en) * | 2013-09-02 | 2015-03-18 | 三星电子株式会社 | Integrated circuit (IC), method of operating the IC, and device having the IC |
-
2017
- 2017-07-04 CN CN201710536672.8A patent/CN107340467B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1270671A (en) * | 1997-09-16 | 2000-10-18 | 泰拉丁公司 | Test system for integrated circuits using a single memory for both the parallel and scan modes of testing |
| CN101446624A (en) * | 2008-12-29 | 2009-06-03 | 华为技术有限公司 | Linking method of combined test group link and link device of combined test group |
| JP2010271126A (en) * | 2009-05-20 | 2010-12-02 | Mitsubishi Electric Corp | Boundary scan circuit |
| CN104237666A (en) * | 2013-06-21 | 2014-12-24 | 京微雅格（北京）科技有限公司 | Method for testing devices in series connection chain of joint test action group |
| CN104422878A (en) * | 2013-09-02 | 2015-03-18 | 三星电子株式会社 | Integrated circuit (IC), method of operating the IC, and device having the IC |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI760400B (en) * | 2017-12-15 | 2022-04-11 | 英業達股份有限公司 | System for using different chains to test differential signal and method thereof |
| WO2020043014A1 (en) * | 2018-08-28 | 2020-03-05 | Changxin Memory Technologies, Inc. | Boundary test circuit, memory and boundary test method |
| US11340294B2 (en) | 2018-08-28 | 2022-05-24 | Changxin Memory Technologies, Inc. | Boundary test circuit, memory and boundary test method |
| CN112290932A (en) * | 2020-09-30 | 2021-01-29 | 上海兆芯集成电路有限公司 | Circuit and test circuit thereof |
| CN112290932B (en) * | 2020-09-30 | 2022-09-06 | 上海兆芯集成电路有限公司 | Circuit and test circuit thereof |
| CN112345925A (en) * | 2020-10-30 | 2021-02-09 | 上海兆芯集成电路有限公司 | Scan chain control circuit |
| CN112345925B (en) * | 2020-10-30 | 2024-05-24 | 格兰菲智能科技有限公司 | Scan chain control circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107340467B (en) | 2020-02-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107340467A (en) | Test system | |
| CN103744009B (en) | A kind of serial transmission chip detecting method, system and integrated chip | |
| CN101071155A (en) | Device and method for realizing border-scanning multi-link test | |
| CN106503308A (en) | A kind of CAN controller IP verification platform based on UVM | |
| CN104569794B (en) | A kind of FPGA In-circiut testers and method of testing based on boundary-scan architecture | |
| US7757139B2 (en) | Boundary scan method, system and device | |
| CN107843828A (en) | A kind of digital circuit boundary scan control system based on FPGA | |
| CN105844056B (en) | A kind of GPIO verifying System and method for | |
| JP6115042B2 (en) | Information processing device, test data creation device, test data creation method, and program | |
| EP0862115B1 (en) | Trigger sequencing controller | |
| CN101545951B (en) | Scan control method, scan control circuit and apparatus | |
| CN109765482A (en) | A kind of high speed interconnecting test method between multi-chip | |
| CN102305907A (en) | Test method and system for multichip encapsulating structure | |
| CN1542459A (en) | Boundary scan testing device for integrated circuit | |
| CN104950241A (en) | Integrated circuit and method for establishing scanning test framework in integrated circuit | |
| CN105334452A (en) | Testing system for boundary scan | |
| US20040068675A1 (en) | Circuit board having boundary scan self-testing function | |
| CN101196553A (en) | Method for improving SOC chip testing efficiency | |
| CN105334451A (en) | Boundary scanning and testing system | |
| CN103645435A (en) | Software module testability design method of multi-signal model programming logic device | |
| CN106610462A (en) | Electronic system, system diagnostic circuit and operation method thereof | |
| CN114113990B (en) | Embedded boundary scan controller | |
| CN102183727B (en) | Boundary scanning test method with error detection function | |
| CN106844118B (en) | A kind of on-chip bus test macro based on Tbus bus standard | |
| CN106918725A (en) | Tool joint test work group signal concatenates the test circuit plate of circuit design |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |