CN112748326A - Chip test circuit, device and system - Google Patents
Chip test circuit, device and system Download PDFInfo
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- CN112748326A CN112748326A CN202011613846.4A CN202011613846A CN112748326A CN 112748326 A CN112748326 A CN 112748326A CN 202011613846 A CN202011613846 A CN 202011613846A CN 112748326 A CN112748326 A CN 112748326A
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The invention discloses a chip test circuit, a device and a system. The chip test circuit includes: the high-frequency signal testing module and the chip form a loop; the first low-frequency signal testing module, the second low-frequency signal testing module, the third low-frequency signal testing module and the fourth low-frequency signal testing module are electrically connected with the chip and the low-frequency signal testing device respectively, and the first low-frequency signal testing module, the second low-frequency signal testing module, the third low-frequency signal testing module and the fourth low-frequency signal testing module are identical in circuit structure and comprise resistors or tapered inductors. According to the technical scheme provided by the embodiment of the invention, on the basis of simultaneously transmitting the high-frequency test signal and the low-frequency test signal, the frequency of the high-frequency test signal which can be transmitted by the chip test circuit is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of chip testing, in particular to a chip testing circuit, a device and a system.
Background
Before the chip leaves the factory, whether the chip can transmit high-frequency signals or not and whether the chip can detect the electrical defects of the chip pins or not need to be detected.
Because, when detecting the electrical defects of the chip pins, the chip pins need to transmit low-frequency test signals. The existing chip test circuit is simultaneously used for transmitting a high-frequency test signal and a low-frequency test signal, the high-frequency test signal is interfered, and the frequency of the transmitted high-frequency test signal is too low to meet the test requirement.
Disclosure of Invention
In view of this, embodiments of the present invention provide a chip test circuit, an apparatus and a system, which are used to increase the frequency of a high-frequency test signal that can be transmitted by the chip test circuit on the basis of simultaneously transmitting the high-frequency test signal and a low-frequency test signal.
In a first aspect, an embodiment of the present invention provides a chip testing circuit, including:
the high-frequency signal testing module is characterized in that a first signal input end of the high-frequency signal testing module is electrically connected with a first testing signal sending pin of a chip, a first signal output end of the high-frequency signal testing module is electrically connected with a first testing signal receiving pin of the chip, a second signal input end of the high-frequency signal testing module is electrically connected with a second testing signal sending pin of the chip, and a second signal output end of the high-frequency signal testing module is electrically connected with a second testing signal receiving pin of the chip, wherein a testing signal sent by the first testing signal sending pin of the chip is equal in amplitude and opposite in phase to a testing signal sent by the second testing signal sending pin of the chip;
the device comprises a first low-frequency signal testing module, a second low-frequency signal testing module, a third low-frequency signal testing module and a fourth low-frequency signal testing module; a first test signal sending pin of the chip is electrically connected with a signal input end of the first low-frequency signal test module, and a signal output end of the first low-frequency signal test module is electrically connected with a first test end of the low-frequency signal test device; a first test signal receiving pin of the chip is electrically connected with a signal input end of a second low-frequency signal test module, and a signal output end of the second low-frequency signal test module is electrically connected with a second test end of the low-frequency signal test device; a second test signal sending pin of the chip is electrically connected with a signal input end of a third low-frequency signal test module, and a signal output end of the third low-frequency signal test module is electrically connected with a third test end of the low-frequency signal test device; a second test signal receiving pin of the chip is electrically connected with a signal input end of a fourth low-frequency signal test module, and a signal output end of the fourth low-frequency signal test module is electrically connected with a fourth test end of the low-frequency signal test device;
the first low-frequency signal testing module, the second low-frequency signal testing module, the third low-frequency signal testing module and the fourth low-frequency signal testing module have the same circuit structure and respectively comprise a resistor or a conical inductor.
Optionally, the high-frequency signal testing module includes a first capacitor, a first electrode of the first capacitor is electrically connected to the first test signal sending pin of the chip, and a second electrode of the first capacitor is electrically connected to the first test signal receiving pin of the chip.
Optionally, the high-frequency signal testing module includes a second capacitor, a first electrode of the second capacitor is electrically connected to a second test signal sending pin of the chip, and a second electrode of the second capacitor is electrically connected to a second test signal receiving pin of the chip.
Optionally, a baseband frequency of a signal transmitted by the first signal output end of the high-frequency signal testing module is equal to 28 GHz.
Optionally, a baseband frequency of a signal transmitted by the second signal output terminal of the high-frequency signal testing module is equal to 28 GHz.
Optionally, the resistance of the resistor is greater than or equal to 953 ohms and less than or equal to 4000 ohms.
In a second aspect, an embodiment of the present invention further provides a chip testing apparatus, including:
the device comprises a printed circuit board, a chip test device and a low-frequency signal test device, wherein a chip slot and a low-frequency signal test device slot are arranged on the first surface of the printed circuit board; a chip connecting pad is arranged in the chip slot and used for accessing a test signal of the chip; a low-frequency signal test connecting pad is arranged in the low-frequency signal test device slot and is used for being electrically connected with a low-frequency signal test device;
a chip test circuit as in any of the first aspect, the chip test circuit being located on a second surface of the printed circuit board opposite to the first surface, the chip test circuit being electrically connected to the chip connection pad through a conductive via passing through the printed circuit board, and the chip test circuit being electrically connected to the low frequency signal test connection pad through a conductive via passing through the printed circuit board.
Optionally, the printed circuit board is further provided with at least one ground via.
Optionally, the ground vias are symmetrically disposed about a center of the printed circuit board.
In a third aspect, an embodiment of the present invention further provides a chip testing system, including:
the chip is used for sending a test signal and detecting the frequency of a high-frequency signal transmitted by the chip;
a chip test circuit as in any of the first aspects, the chip test circuit being electrically connected to the chip for transmitting the test signal;
the low-frequency signal testing device is respectively and electrically connected with the chip and the chip testing circuit and is used for detecting electrical defects of a testing signal sending pin and a testing signal receiving pin of the chip, wherein the electrical defects comprise one or more of open circuit, short circuit and physical defects.
In the technical scheme provided in this embodiment, in a first aspect, the high-frequency signal test module and the chip form a chip high-frequency signal test loop, wherein after a high-frequency test signal in the test signals sent by the first test signal sending pin and the second test signal sending pin of the chip is transmitted in the high-frequency signal test module and then returns to the chip, the chip detects the frequency of the high-frequency test signal, so as to complete the detection of whether the chip test circuit can transmit the high-frequency signal to the chip. In a second aspect, a resistor or a tapered inductor is used as a first low-frequency signal testing module, a second low-frequency signal testing module, a third low-frequency signal testing module and a fourth low-frequency signal testing module, and forms a low-frequency signal testing loop with a pin of a chip and a low-frequency signal testing device, and the low-frequency signal testing device determines that the pin of the chip has electrical defects by detecting electrical signals of signal output ends of the first low-frequency signal testing module, the second low-frequency signal testing module, the third low-frequency signal testing module and the fourth low-frequency signal testing module, wherein the electrical defects include one or more of open circuit, short circuit and physical defects. Specifically, the resistor does not interfere with a high-frequency test signal in the test signal when transmitting the low-frequency test signal; or, the conical inductor has the function of mixing a high-frequency signal into a low-frequency signal when transmitting the low-frequency test signal, so that the high-frequency test signal in the test signal cannot be interfered; according to the technical scheme, the chip test circuit can not interfere the high-frequency test signal when transmitting the low-frequency test signal through the resistor or the conical inductor, and further the technical effect that the frequency of the high-frequency test signal is improved on the basis that the chip test circuit transmits the high-frequency test signal and the low-frequency test signal at the same time is achieved.
Drawings
Fig. 1 is a schematic structural diagram of a chip testing circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another chip test circuit according to an embodiment of the present invention;
FIG. 3 is a test chart showing the variation of the energy of the test signal transmitted by the chip test circuit with the baseband frequency according to the embodiment of the present invention;
FIG. 4 is a test chart showing the variation of the energy of the test signal transmitted by the chip test circuit with the baseband frequency according to another embodiment of the present invention;
fig. 5 is a schematic structural diagram of a chip testing apparatus according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a chip testing system according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, when a chip testing circuit used at present detects whether a chip can transmit a high-frequency signal and electrical defects of chip pins, the high-frequency testing signal is interfered when transmitting the high-frequency testing signal and a low-frequency testing signal, so that the frequency of the transmitted high-frequency testing signal is too low to meet the testing requirement.
In view of the above technical problems, an embodiment of the present invention provides the following technical solutions:
fig. 1 is a schematic structural diagram of a chip testing circuit according to an embodiment of the present invention. The low frequency signal testing module 20 in fig. 1b is a resistor R1, and the low frequency signal testing module 20 in fig. 1c is a tapered inductor L1. Referring to fig. 1, the chip test circuit includes: the high-frequency signal testing module 10 comprises a first signal input end 10A of the high-frequency signal testing module 10, a first test signal sending pin B10 of the chip, a first signal output end 10B of the high-frequency signal testing module 10, a second signal input end 10C of the high-frequency signal testing module 10, a second test signal sending pin B30 of the chip and a second signal output end 10D of the high-frequency signal testing module 10, wherein the first signal input end 10A of the high-frequency signal testing module 10 is electrically connected with a first test signal receiving pin B20 of the chip, the second signal input end 10C of the high-frequency signal testing module 10 is electrically connected with a second test signal receiving pin B40 of the chip, and a test signal sent by the first test signal sending pin B10 of the chip and a test signal sent by the second test signal sending pin B; the test device comprises a first low-frequency signal test module 21, a second low-frequency signal test module 22, a third low-frequency signal test module 23 and a fourth low-frequency signal test module 24, wherein a first test signal sending pin B10 of the chip is electrically connected with a signal input end 20A of the first low-frequency signal test module 21, and a signal output end 20B of the first low-frequency signal test module 21 is electrically connected with a first test end C10 of a low-frequency signal test device; the first test signal receiving pin B20 of the chip is electrically connected with the signal input end 20A of the second low-frequency signal test module 22, and the signal output end 20B of the second low-frequency signal test module 22 is electrically connected with the second test end C20 of the low-frequency signal test device; a second test signal sending pin B30 of the chip is electrically connected with a signal input end 20A of the third low-frequency signal testing module 23, and a signal output end 20B of the third low-frequency signal testing module 23 is electrically connected with a third testing end C30 of the low-frequency signal testing device; the second test signal receiving pin B40 of the chip is electrically connected to the signal input terminal 20A of the fourth low-frequency signal testing module 24, and the signal output terminal 20B of the fourth low-frequency signal testing module 24 is electrically connected to the fourth test terminal C40 of the low-frequency signal testing device; the first low-frequency signal testing module 21, the second low-frequency signal testing module 22, the third low-frequency signal testing module 23, and the fourth low-frequency signal testing module 24 each include a resistor R1 or a tapered inductor L1, wherein a first end of the resistor R1 or a small-end pin of the tapered inductor L1 serves as a signal input terminal 20A of the first low-frequency signal testing module 21, the second low-frequency signal testing module 22, the third low-frequency signal testing module 23, and the fourth low-frequency signal testing module 24, and a second end of the resistor R1 or a large-end pin of the tapered inductor L1 serves as a signal output terminal 20B of the first low-frequency signal testing module 21, the second low-frequency signal testing module 22, the third low-frequency signal testing module 23, and the fourth low-frequency signal testing module 24.
In the present embodiment, the test signal transmitted from the first test signal transmitting pin B10 of the chip and the test signal transmitted from the second test signal transmitting pin B30 of the chip have the same amplitude and opposite phase, i.e., the test signals transmitted from the first test signal transmitting pin B10 of the chip and the second test signal transmitting pin B30 of the chip are differential signals.
In the technical scheme provided in this embodiment, in a first aspect, the high-frequency signal testing module 10 and the chip form a chip high-frequency signal testing loop, wherein after a high-frequency testing signal in the testing signals sent by the first testing signal sending pin B10 and the second testing signal sending pin B30 of the chip is transmitted in the high-frequency signal testing module 10 and then returns to the chip, the chip detects the frequency of the high-frequency testing signal, so as to complete the detection of whether the chip can transmit the high-frequency signal by the chip testing circuit. In a second aspect, the resistor R1 or the tapered inductor L1, as the first low frequency signal testing module 21, the second low frequency signal testing module 22, the third low frequency signal testing module 23, and the fourth low frequency signal testing module 24, forms a low frequency signal testing loop with the pins of the chip and the low frequency signal testing device, and the low frequency signal testing device determines that the pins of the chip all have electrical defects by detecting electrical signals of the signal output terminals 20B of the first low frequency signal testing module 21, the second low frequency signal testing module 22, the third low frequency signal testing module 23, and the fourth low frequency signal testing module 24, where the electrical defects include one or more of open circuits, short circuits, and physical defects. Specifically, the resistor R1 does not interfere with a high-frequency test signal in the test signals when transmitting the low-frequency test signal; or, the tapered inductor L1 has the function of mixing the high-frequency signal into the low-frequency signal when the tapered inductor L1 transmits the low-frequency test signal, so that the high-frequency test signal in the test signal is not interfered; above-mentioned technical scheme through resistance R1 or toper inductance L1, has realized that chip test circuit can not disturb high frequency test signal when transmitting low frequency test signal, and then has realized that chip test circuit improves the technological effect of the frequency of high frequency test signal on the basis of transmitting high frequency test signal and low frequency test signal simultaneously.
Fig. 2 is a schematic structural diagram of another chip test circuit according to an embodiment of the present invention. On the basis of the above technical solution, referring to fig. 2, the high frequency signal testing module 10 includes a first capacitor C1, a first electrode of the first capacitor C1 is electrically connected to the first test signal transmitting pin B10 of the chip, and a second electrode of the first capacitor C1 is electrically connected to the first test signal receiving pin B20 of the chip.
Specifically, the first capacitor C1 has the functions of passing high frequency and blocking low frequency, so that a chip high-frequency signal test loop can be formed by the first capacitor C1, the first test signal sending pin B10 of the chip and the first test signal receiving pin B20 of the chip, wherein after a high-frequency test signal in the test signal sent by the first test signal sending pin B10 of the chip is transmitted in the first capacitor C1 and then returns to the chip, the chip detects the frequency of the high-frequency test signal, so as to complete the detection of whether the chip can transmit the high-frequency signal by the chip test circuit.
On the basis of the above technical solution, referring to fig. 2, the high frequency signal testing module 10 includes a second capacitor C2, a first electrode of the second capacitor C2 is electrically connected to the second test signal transmitting pin B30 of the chip, and a second electrode of the second capacitor C2 is electrically connected to the second test signal receiving pin B40 of the chip.
Specifically, the second capacitor C2 has the functions of passing high frequency and blocking low frequency, so that a high frequency signal test loop of the chip can be formed by the second capacitor C2, the second test signal sending pin B30 of the chip, and the second test signal receiving pin B40 of the chip, wherein after a high frequency test signal in the test signal sent by the second test signal sending pin B30 returns to the chip after being transmitted in the second capacitor C2, the chip detects the frequency of the high frequency test signal, so as to complete the detection of whether the chip can transmit the high frequency signal by the chip test circuit.
On the basis of the above technical solution, the baseband frequency of the signal transmitted by the first signal output end 10B of the high-frequency signal testing module 10 is equal to 28GHz, so that the first testing signal receiving pin B20 of the chip receives the high-frequency testing signal with the baseband frequency equal to 28GHz, and the chip detects the frequency of the high-frequency testing signal, so as to complete the function of the chip testing circuit in transmitting the high-frequency signal.
On the basis of the above technical solution, the baseband frequency of the signal transmitted by the second signal output end of the high-frequency signal testing module 10 is equal to 28GHz, so that the first testing signal receiving pin B20 of the chip receives the high-frequency testing signal with the baseband frequency equal to 28GHz, and the chip detects the frequency of the high-frequency testing signal, so as to complete the function of the chip testing circuit in transmitting the high-frequency signal.
It should be noted that, when the baseband frequency is equal to 28GHz, since the coding method in this embodiment adopts a PAM4 modulation method, and the PAM4 modulation method adopts 4 different signal levels for signal transmission, each symbol period may represent logic information of 2 bits, so that the frequency of the high-frequency test signal transmitted in the chip test circuit is 112 GHz. Because each symbol period of the PAM4 signal can transmit 2 bits of information, to achieve the same signal transmission capability, the symbol rate of the PAM4 signal only needs to reach half of that of the NRZ signal, and therefore loss caused by a transmission channel is greatly reduced.
Fig. 3 is a test chart of the energy of the test signal transmitted by the chip test circuit according to the embodiment of the invention, which varies with the baseband frequency. Fig. 3a is a test chart of the energy of the high-frequency test signal transmitted by the chip test circuit changing with the baseband frequency, and fig. 3b is a test chart of the energy of the low-frequency test signal transmitted by the chip test circuit changing with the baseband frequency. Referring to fig. 3a, when the baseband frequency of the test signal is greater than 16GHz, the chip test circuit in the prior art, in which the inductor and the magnetic bead are connected in series, transmits the test signal and generates a large signal reflection phenomenon, so that only the test signal with the bandwidth of 16GHz baseband frequency can be satisfied. However, when the chip test circuit (LC) composed of the tapered inductor L1 and the capacitor C and the chip test circuit (RC) composed of the resistor R1 and the capacitor C are at the baseband frequency of 37Ghz, the linear relationship between the energy of the test signal and the baseband frequency is still good, and no signal reflection phenomenon occurs. Therefore, the chip test circuit provided by the embodiment can transmit the high-frequency test signal with the baseband frequency equal to 28 GHz.
Referring to fig. 3b, the chip test circuit (LC) composed of the tapered inductor L1 and the capacitor C and the chip test circuit (RC) composed of the resistor R1 and the capacitor C can meet the requirement of low-speed test within the baseband frequency of 200 Mhz.
Fig. 4 is a test chart of the energy of the test signal transmitted by the chip test circuit according to another embodiment of the present invention, which varies with the baseband frequency. The chip test circuit in fig. 4 is a chip test circuit (LC) composed of a tapered inductor L1 and a capacitor C. On the basis of the technical scheme, the resistance value of the resistor R1 is greater than or equal to 953 ohms and less than or equal to 4000 ohms.
Table 1 is a data table of the energy and resistance of the test signal transmitted by the chip test circuit shown in fig. 4. Wherein the baseband frequency of the test signal is 28 GHz.
TABLE 1 data sheet of energy and resistance of test signals
| Resistance R1 (ohm) | Energy (dB) |
| 0 | 0.86 |
| 4000 | 0.85 |
| 2000 | 0.84 |
| 953 | 0.82 |
| 100 | 0.65 |
| 50 | 0.57 |
Referring to fig. 4 and table 1, the baseband frequency of the test signal is 28GHz, the resistance of the resistor R1 is greater than or equal to 953 ohms and less than or equal to 4000 ohms, the energy of the test signal is above 0.82dB, and the difference is not much from that when the resistor R1 is not provided. Therefore, the resistance value of the resistor R1 is more than or equal to 953 ohms and less than or equal to 4000 ohms, and is set in the value range, the resistor R1 has small interference on a high-frequency test signal with the baseband frequency of 28 GHz.
The embodiment of the invention also provides a chip testing device. Fig. 5 is a schematic structural diagram of a chip testing apparatus according to an embodiment of the present invention. Wherein, FIG. 5a is a cross-sectional view taken along the direction C1-C2 in FIG. 5 b. FIG. 5b is a top view of the chip testing apparatus. Fig. 5c and 5d are schematic structural views of the second surface of the printed circuit board in the chip testing device. Referring to fig. 5, the chip testing apparatus includes: the circuit board comprises a printed circuit board 200, wherein a chip slot 210 and a low-frequency signal testing device slot 220 are arranged on a first surface 201 of the printed circuit board 200; the chip socket 210 has a chip connection pad 210A disposed therein, the chip connection pad 210A is electrically connected to a pin 310 of the chip 300, and the chip connection pad 210A is used for accessing a test signal of the chip 300. Wherein the pins 310 include a first test signal transmission pin B10 of the chip, a first test signal reception pin B20 of the chip, a second test signal transmission pin B30 of the chip, and a second test signal reception pin B40 of the chip. A low frequency signal test connection pad for electrically connecting with a low frequency signal test device (not shown) is provided in the low frequency signal test device socket 220.
On the basis of the above technical solution, referring to fig. 5, the printed circuit board 200 is further provided with at least one ground via 204.
Specifically, the arrangement of the ground via 204 can realize matching of the impedance of the chip test circuit 100 with the impedance of the chip 300.
Specifically, the ground vias 204 are symmetrically disposed about the center of the printed circuit board 200. Specifically, on the basis of obtaining the center of the printed circuit board 200, the ground vias 204 are symmetrically arranged with respect to the center of the printed circuit board 200, so that the position accuracy of the ground vias 204 can be improved.
The chip testing device provided by the present embodiment includes the chip testing circuit of the above embodiment, and the technical effect of the chip testing device provided by the present embodiment is similar to that of the above embodiment, and is not described herein again.
The embodiment of the invention also provides a chip testing system. Fig. 6 is a schematic structural diagram of a chip testing system according to an embodiment of the present invention. Referring to fig. 6, the chip test system includes:
a chip 300 for sending a test signal and detecting the frequency of a high-frequency signal transmitted by the chip; the chip testing circuit 100 is the chip testing circuit according to any one of the above technical solutions, and the chip testing circuit 100 is electrically connected with the chip 300 and used for transmitting a testing signal; the low frequency signal testing device 400, the low frequency signal testing device 400 is electrically connected to the chip 300 and the chip testing circuit 100, respectively, and the low frequency signal testing device 400 is used for detecting electrical defects of a testing signal sending pin and a testing signal receiving pin of the chip 300, wherein the electrical defects include one or more of open circuit, short circuit and physical defects.
The chip test system provided by this embodiment includes the chip test circuit of the above embodiment, and the implementation principle and technical effect of the chip test system provided by this embodiment are similar to those of the above embodiment, and are not described here again.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A chip test circuit, comprising:
the high-frequency signal testing module is characterized in that a first signal input end of the high-frequency signal testing module is electrically connected with a first testing signal sending pin of a chip, a first signal output end of the high-frequency signal testing module is electrically connected with a first testing signal receiving pin of the chip, a second signal input end of the high-frequency signal testing module is electrically connected with a second testing signal sending pin of the chip, and a second signal output end of the high-frequency signal testing module is electrically connected with a second testing signal receiving pin of the chip, wherein a testing signal sent by the first testing signal sending pin of the chip is equal in amplitude and opposite in phase to a testing signal sent by the second testing signal sending pin of the chip;
the device comprises a first low-frequency signal testing module, a second low-frequency signal testing module, a third low-frequency signal testing module and a fourth low-frequency signal testing module; a first test signal sending pin of the chip is electrically connected with a signal input end of the first low-frequency signal test module, and a signal output end of the first low-frequency signal test module is electrically connected with a first test end of the low-frequency signal test device; a first test signal receiving pin of the chip is electrically connected with a signal input end of a second low-frequency signal test module, and a signal output end of the second low-frequency signal test module is electrically connected with a second test end of the low-frequency signal test device; a second test signal sending pin of the chip is electrically connected with a signal input end of a third low-frequency signal test module, and a signal output end of the third low-frequency signal test module is electrically connected with a third test end of the low-frequency signal test device; a second test signal receiving pin of the chip is electrically connected with a signal input end of a fourth low-frequency signal test module, and a signal output end of the fourth low-frequency signal test module is electrically connected with a fourth test end of the low-frequency signal test device;
the first low-frequency signal testing module, the second low-frequency signal testing module, the third low-frequency signal testing module and the fourth low-frequency signal testing module have the same circuit structure and respectively comprise a resistor or a conical inductor.
2. The chip test circuit according to claim 1, wherein the high frequency signal test module comprises a first capacitor, a first electrode of the first capacitor is electrically connected to a first test signal transmitting pin of the chip, and a second electrode of the first capacitor is electrically connected to a first test signal receiving pin of the chip.
3. The chip test circuit according to claim 1, wherein the high frequency signal test module comprises a second capacitor, a first electrode of the second capacitor is electrically connected to a second test signal transmitting pin of the chip, and a second electrode of the second capacitor is electrically connected to a second test signal receiving pin of the chip.
4. The chip test circuit according to claim 1, wherein the baseband frequency of the signal transmitted by the first signal output terminal of the high frequency signal test module is equal to 28 GHz.
5. The chip test circuit according to claim 1, wherein the baseband frequency of the signal transmitted by the second signal output terminal of the high frequency signal test module is equal to 28 GHz.
6. The chip test circuit according to claim 1, wherein the resistance of the resistor is 953 ohms or more and 4000 ohms or less.
7. A chip testing apparatus, comprising:
the device comprises a printed circuit board, a chip test device and a low-frequency signal test device, wherein a chip slot and a low-frequency signal test device slot are arranged on the first surface of the printed circuit board; a chip connecting pad is arranged in the chip slot and used for accessing a test signal of the chip; a low-frequency signal test connecting pad is arranged in the low-frequency signal test device slot and is used for being electrically connected with a low-frequency signal test device;
a chip test circuit according to any one of claims 1 to 6, the chip test circuit being located on a second surface of the printed circuit board opposite to the first surface, the chip test circuit being electrically connected to the chip connection pad through a conductive via passing through the printed circuit board, and the chip test circuit being electrically connected to the low frequency signal test connection pad through a conductive via passing through the printed circuit board.
8. The chip testing device according to claim 7, wherein the printed circuit board is further provided with at least one ground via.
9. The chip testing device according to claim 8, wherein the ground vias are symmetrically disposed about a center of the printed circuit board.
10. A chip test system, comprising:
the chip is used for sending a test signal and detecting the frequency of a high-frequency signal transmitted by the chip;
a chip test circuit according to any one of claims 1 to 6, the chip test circuit being electrically connected to the chip for transmitting the test signal;
the low-frequency signal testing device is respectively and electrically connected with the chip and the chip testing circuit and is used for detecting electrical defects of a testing signal sending pin and a testing signal receiving pin of the chip, wherein the electrical defects comprise one or more of open circuit, short circuit and physical defects.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113740707A (en) * | 2021-08-20 | 2021-12-03 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Loopback test circuit of chip interface module |
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