CN202929399U - Mixed signal circuit boundary scan test controller - Google Patents
Mixed signal circuit boundary scan test controller Download PDFInfo
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- CN202929399U CN202929399U CN 201220413127 CN201220413127U CN202929399U CN 202929399 U CN202929399 U CN 202929399U CN 201220413127 CN201220413127 CN 201220413127 CN 201220413127 U CN201220413127 U CN 201220413127U CN 202929399 U CN202929399 U CN 202929399U
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Abstract
The utility model relates to a mixed signal circuit boundary scan test controller, which comprises a host module, a counting module, an instruction module, a test clock divider, a general register group, an analog register group, a serial scanning module and an analog instrument platform control module, wherein the counting module, the instruction module, the test clock divider, the general register group, the analog register group, the serial scanning module and the analog instrument platform control module are connected with the host module through read-write data bus. The mixed signal circuit boundary scan test controller is equipped with a processor interface and a test bus interface. The analog instrument platform control module is equipped with a mixed signal control interface, wherein the interface is connected with a program-controlled signal source producing voltage/current stimulus signals and a voltage collector collecting response signals of a circuit under test. The processor interface of the host module is connected with a microprocessor. The serial scanning module is equipped with two groups of test bus interfaces. The mixed signal control interface is an SPI interface and connected with an analog instrument platform. The mixed signal circuit boundary scan test controller is convenient for assembling a mixed signal circuit boundary scan test system to carry out a digital/analog boundary scan test, and solves a problem of synchronizing digital vector applying, analog test stimulus applying and voltage collection.
Description
Technical field
The utility model relates to ic test technique field, especially mixed signal circuit Boundary Scan Controller.
Background technology
Along with the progress of semiconductor technology and the raising of integrated circuit (IC) design technology, in chip, the scale of integrated transistor is being the exponential form growth always according to Moore's Law, the integrated function of chip internal from strength to strength, inner structure is increasingly sophisticated, and integrated circuit has entered system level chip (SOC) epoch.The pin that the high integration of chip and the High Density Packaging of printed panel make the integrated circuit (IC) chip outside to contact is fewer and feweri, the difficulty of test is also increasing, the expense that the testing cost of chip is even produced higher than the design of chip itself, chip testing have become the bottleneck of restriction chip development.
At present, when the board-level circuit fault diagnosis, the main method that applies or obtain signal is the contact diagnosis, namely uses needle-bar or manually uses probe, and the electric signal of detection circuit internal node carries out localization of fault according to these information.Gradually to the future development of miniaturization, densification, multiple stratification, the test of contact diagnosis is hard to carry on along with circuit board.Under this background, boundary scan testing (BST:Boundary Scan Test) technology is arisen at the historic moment.
Standardization design for Measurability technology based on boundary scan has now formed comparatively ripe system, and the field tests of the different levels such as chip, circuit board, the system integration has been contained in its impact.IEEE 1149.1 standard definitions a kind of boundary-scan architecture and test interface thereof of standard, its main thought is by increase boundary scan cell between chip pin and chip internal logical circuit, realization is set and reads the serial of chip pin state, mainly solves the test problem of circuit board level digital circuit.IEEE 1149.4 operating such IEEE 1149.1 standards in addition will be by in the newly-increased simulation test bus of chip internal and relevant control module, realizes the simulating signal in the mixed signal circuit plate is monitored and the parameter measurement of analog element.This technical standard provides a solution for the mixed signal circuit design for Measurability.Yet, in composite signal integrated circuits, the test of simulation part is generally compared the test difficulty of numerical portion, and has been become " bottleneck " of Mixed-signal IC test.According to external, in a mixed signal chip, the testing cost that only accounts for the simulation part of silicon area 5% has but accounted for 95% of whole chip testing cost.
at present mixed signal circuit is carried out the Boundary Scan Controller that boundary scan testing adopts existing support IEEE 1149.1 standards, consist of the analog meter platform with general voltage signal source/current signal source and voltage collector, coordinate testing control module, existing Boundary Scan Controller produces the test signal that meets IEEE 1149.1 standards, produce by voltage signal source/current signal source the pumping signal that frequency and the adjustable voltage of amplitude or electric current are used for providing mixed signal circuit, voltage collector is used for gathering the signal amplitude of mixed signal circuit response, the information that testing control module is completed Boundary Scan Controller and microcomputer transmits, and the analog meter platform is controlled.This test mode because the direct control simulation instrument platform of Boundary Scan Controller, is difficult to process that digital vector applies, analog stimulus applies, and the stationary problem between the circuit-under-test voltage signal acquisition.
The utility model content
the purpose of this utility model is a kind of mixed signal circuit Boundary Scan Controller of design, this mixed signal circuit Boundary Scan Controller can produce the test signal that meets IEEE 1149.1 standards, is furnished with simultaneously the mixed signal control interface, the programme-controlled signal source of control simulation instrument platform and voltage collector, apply to solve digital vector, simulation test excitation apply and the voltage acquisition three between synchronous, the boundary scan testing that the mixed signal circuit boundary scan and test system that mixed signal Boundary Scan Controller of the present utility model is set up can be realized supporting the digital circuit of IEEE 1149.1 standards and support the mixed signal circuit of IEEE 1149.4 standards.
Mixed signal circuit Boundary Scan Controller of the present utility model comprises host module and the counting module, the command module that are connected with host module through the bus that reads and writes data, and be furnished with processor interface and test bus interface, host module is also through bus connecting test Clock dividers (TCK frequency divider), general purpose register set, simulation register group, serial scan module and the analog meter platform control module of reading and writing data.Described analog meter platform control module is furnished with the mixed signal control interface, and this interface connects the programme-controlled signal source that produces voltage or current excitation signal and the voltage collector that gathers circuit-under-test voltage responsive signal, swap data with it.
Described circuit-under-test is for supporting the circuit of IEEE 1149.1 or IEEE 1149.4 standards.Supporting the circuit-under-test of IEEE1149.1 standard, is the digital circuit boundary scan testing to its test, and this type of circuit-under-test is furnished with the test bus interface; Supporting the circuit-under-test of IEEE 1149.4 standards, is digital circuit boundary scan testing and mimic channel boundary scan testing to its full test, and this type of circuit-under-test is furnished with the test bus interface, also is furnished with excitation interface and response voltage acquisition interface.
Described host module is furnished with processor interface, and processor interface comprises 16 BDB Bi-directional Data Bus (DATA (15:0)), 5 bit address lines (ADDR (4:0)), reading signal lines
The write signal line
Line of chip select
Interrupt request line
And reseting signal line (RESET).Processor interface is used for connecting microprocessor, host module receives by processor interface the parallel data that microprocessor sends, and store in the corresponding register of this mixed signal circuit Boundary Scan Controller, host module sends the status data of this mixed signal circuit Boundary Scan Controller and test result to microprocessor by processor interface.
Described test clock frequency divider is for generation of the adjustable tck clock signal of frequency.
Described serial scan module is furnished with two groups of test bus interfaces (jtag interface), one group of test bus interface connects one of the described circuit-under-test independently test bus interface of scan chain circuit, and perhaps two groups of test bus interfaces connect two of the described circuit-under-test independently test bus interfaces of scan chain circuit simultaneously.Every group of test bus interface comprises the test reset line
Test clock line (TCK), test pattern are selected line (TMS), test data output line (TDO), test data input line (TDI).The serial scan module is according to IEEE 1149.1 standard output test mode select signals (TMS), arrive circuit-under-test in test access port (TAP) controller shift order registered state and shifted data registered state by test data output line (TDO) transmission test command and test data, the while is the serial test result of Data In-Line (TDI) reception circuit-under-test after tested.
Described counting module is counted data displaced condition, instruction shift state and three kinds of states of test run/idle condition of test access port (TAP) controller of circuit-under-test.Test instruction/the vector of circuit-under-test is when shift order/data registered state, in the clock period of a test clock (TCK) displacement 1 bit instruction/data, the number of times of displacement is the number of bits of test instruction/vector, and the number of bits of described test instruction is the summation of number of bits of the boundary scan testing instruction of each chip in the circuit-under-test scan chain; The number of bits of described test vector is the summation of the boundary scan cell number of each chip in the circuit-under-test boundary scan chain.
Described command module comprises reset command, test run/free time order, instruction scan order and data scanning order four class instructions.Described reset command makes test access port (TAP) controller of circuit-under-test enter the test logic reset mode for output test mode select signal (TMS); Described test run/free time order makes test access port (TAP) controller of circuit-under-test enter test run/idle condition for output test mode select signal (TMS); Described instruction scan order mainly comprises shift order registered state and two steady state (SS)s of pause instruction registered state.command module output test mode select signal (TMS), make test access port (TAP) controller of circuit-under-test be in the shift order registered state, the test access port of circuit-under-test (TAP) controller under this state at clock period serial-shift one bit instruction of a test clock (TCK), the counting module of this mixed signal circuit Boundary Scan Controller is counted test clock (TCK) simultaneously, when the instruction figure place of actual shift during less than the instruction length of 32 digit counters indications, output test mode select signal (TMS) makes test access port (TAP) controller of circuit-under-test enter test run/idle condition, the instruction figure place of actual shift is during greater than the instruction length of 32 digit counters indications, output test mode select signal (TMS) makes test access port (TAP) controller of circuit-under-test enter the pause instruction registered state, wait for again receiving instruction, complete the shifting function of remaining instruction.described data scanning order, mainly comprise and make circuit-under-test be in the shifted data registered state and suspend two steady state (SS)s of data registered state, command module output test mode select signal (TMS), make test access port (TAP) controller of circuit-under-test be in the shifted data registered state, the test access port of circuit-under-test (TAP) controller under this state in the clock period of a test clock (TCK) serial-shift a data, the counting module of this test controller is counted test clock (TCK) simultaneously, when the data bits of actual shift during less than the data length of 32 digit counters indications, output test mode select signal (TMS) makes test access port (TAP) controller of circuit-under-test enter test run/idle condition, the data bits of actual shift is during greater than the data length of 32 digit counters indications, output test mode select signal (TMS) makes test access port (TAP) controller of circuit-under-test enter time-out data registered state, wait for receive data again, complete the shifting function of data left.
Described mixed signal control interface is serial peripheral (SPI, the abbreviation of Serial Peripheral Interface) from the pattern interface, be furnished with serial peripheral (SPI) holotype interface take the analog meter platform as main frame, be furnished with serial peripheral take this mixed signal circuit Boundary Scan Controller as slave from the pattern interface.The analog meter platform comprises the programme-controlled signal source and the voltage collector that gathers circuit-under-test voltage responsive signal that circuit-under-test is produced voltage or current excitation signal.The serial peripheral of slave is connected with the serial peripheral holotype interface of main frame from the pattern interface and carries out exchanges data.The analog meter platform receives frequency and the amplitude control information of the voltage/current pumping signal that analog meter platform control module sends by Serial Peripheral Interface (SPI), send simultaneously the voltage acquisition result of voltage collector to analog meter platform control module by Serial Peripheral Interface (SPI).Described serial peripheral comprises clock line (SCK), slave selection line from the pattern interface
Main frame output slave input line (MOSI) and main frame input slave output line (MISO), this serial peripheral meets the requirement of Serial Peripheral Interface (SPI) standard time sequence from the pattern interface.
Described general purpose register set, be used for controlling the control that this mixed signal circuit Boundary Scan Controller is completed different operations, comprise configuration register, command register, status register, test data input buffer, test data output buffer and 32 digit counters.
Described configuration register, be 16 read/writable registers, the testing clock frequency, the test pattern that are used for two groups of test bus interfaces of this mixed signal circuit of configuration Boundary Scan Controller select (TMS) output mode, test data output (TDO) output mode and circuit-mode to select four kinds of configuration informations.
Described command register is 16 read/writable registers, be divided into two groups of most-significant byte and least-significant bytes, be respectively the order of two groups of test bus interfaces of this mixed signal circuit Boundary Scan Controller, mainly be divided into test reset, test run/free time, instruction scan and data scanning four class orders.
Described status register, it is the read-only register of 16, be divided into two groups of most-significant byte and least-significant bytes, represent respectively the running status of test access port controller of the circuit-under-test scan chain circuit that two groups of test bus interfaces connect and the state of analog circuit test response results.
Described test data input buffer, be 4 16 read-only first in first out (FIFO) registers, be used for preserving the test result of the circuit-under-test that moves into by test data input line (TDI) serial, two groups of test bus interfaces have respectively independently test data input buffer.
Described test data output buffer, be 4 16 and only write first in first out (FIFO) register, be used for preserving test instruction or the test vector that shifts out by test data output line (TDO) serial, two groups of test bus interfaces have respectively independently test data output buffer.
Described 32 digit counters, it is the read/writable register of 32, the figure place that is used for recording instruction displacement or data displacement, namely realize the counting to the clock period of test clock frequency divider (TCK), when carrying out boundary scan testing with assurance, the test instruction of circuit-under-test test data input line (TDI) input or the figure place of test vector are correct.Two groups of test bus interfaces have respectively independently 32 digit counters.Described simulation register group comprises frequency register, amplitude registers, effective value register and user register.Described frequency register is 48 read-only registers, is used for preserving programme-controlled signal source alternating voltage or the current excitation frequency control information of analog meter platform; Described amplitude registers is 48 read-only registers, is used for AC/DC voltage or the control information of current excitation amplitude of the programme-controlled signal source of preservation analog meter platform; Described effective value register is 48 write-only registers, be used for to preserve the AC/DC voltage responsive result that the voltage collector of analog meter platform collects; Described user register is 48 read/writable registers, has 1～3 group, by user's self-defining purposes as required.
Compared with prior art, the advantage of the utility model mixed signal circuit Boundary Scan Controller is: 1, compatible IEEE 1149.1 standards and IEEE 1149.4 standards, be furnished with serial peripheral from the pattern interface, but the control simulation instrument platform to circuit-under-test produce that voltage or current excitation signal have solved that test bus interface (JTAG) digital vector in the mixed signal circuit boundary scan testing applies, the simulation test excitation applies and the voltage acquisition three between stationary problem; 2, be convenient to assemble the mixed signal circuit boundary scan and test system, saved the high expense of all purpose instrument, effectively improved the cost performance of simulating boundary scan test system.
Description of drawings
Fig. 1 is this mixed signal circuit Boundary Scan Controller example structure block diagram.
Number in the figure is:
1, test bus interface, 2, the mixed signal control interface, 3, processor interface, 4, bus reads and writes data.
Embodiment
Below in conjunction with drawings and Examples, the utility model is further described:
This mixed signal circuit Boundary Scan Controller embodiment comprises host module and the counting module that is connected with host module through the bus 4 that reads and writes data, command module, test clock frequency divider (TCK frequency divider), general purpose register set, simulation register group, serial scan module and analog meter platform control module as shown in Figure 1.
Described host module is furnished with processor interface 3, and processor interface 3 comprises 16 BDB Bi-directional Data Bus (DATA (15:0)), 5 bit address lines (ADDR (4:0)), reading signal lines
The write signal line
Line of chip select
Interrupt request line
And reseting signal line (RESET).Processor interface is used for connecting microprocessor, host module receives by processor interface 3 parallel data that microprocessor sends, and store in the corresponding register of this mixed signal circuit Boundary Scan Controller, host module sends the status data of this mixed signal circuit Boundary Scan Controller and test result to microprocessor by processor interface.
This routine analog meter platform control module be furnished with serial peripheral SPI from the pattern interface as mixed signal control interface 2, this interface connects the programme-controlled signal source that produces voltage or current excitation signal and connects with the voltage collector that is connected circuit-under-test voltage responsive signal, with it swap data.Be furnished with SPI holotype interface take the analog meter platform as main frame, be furnished with SPI take this mixed signal circuit Boundary Scan Controller as slave from the pattern interface.The analog meter platform comprises the programme-controlled signal source and the voltage collector that gathers circuit-under-test voltage responsive signal that circuit-under-test is produced voltage or current excitation signal.The SPI of slave is connected with the SPI holotype interface of main frame from the pattern interface and carries out exchanges data.
Described SPI comprises clock line (SCK), slave selection line from the pattern interface
Main frame output slave input line (MOSI) and main frame input slave output line (MISO), this SPI meets the requirement of SPI standard time sequence from the pattern interface.
The analog meter platform receives frequency and the amplitude control information of the voltage/current pumping signal that analog meter platform control module sends by the SPI interface, send simultaneously the voltage acquisition result of voltage collector to analog meter platform control module by the SPI interface.
SPI communication sequential is: at the rising edge of clock period of clock line (SCK), the mixed signal Boundary Scan Controller is exported slave input line (MOSI) by main frame data serial is moved into; At the negative edge of clock period of clock line (SCK), the mixed signal circuit Boundary Scan Controller is inputted slave output line (MISO) by main frame the internal data serial is shifted out.For completing the serial peripheral equipment interface SPI communication mode, described analog meter platform control module is obtained mixed signal Boundary Scan Controller simulation test state by reading the SPI status register, utilize the SPI communication register that the type of the simulation register that needs access is set, reading frequency register and amplitude registers arrange frequency and the amplitude of the voltage/current pumping signal of programme-controlled signal source, gather circuit-under-test voltage responsive result and are stored in the effective value register.
Described SPI communication register is eight bit register, is mainly used in selecting corresponding registers and the read/write operation type of general purpose register set, its position definition and function such as table 1:
Table 1, SPI communication register everybody definition and function list
Described SPI status register is mainly used in instruction simulation test correlation behavior, and its position definition is as shown in table 2 with functional description:
Table 2, SPI status register everybody definition and function list
Described test clock frequency divider (TCK frequency divider) is for generation of the adjustable tck clock signal of frequency.
Described serial scan module is furnished with two groups of test bus interface 1(JTAG interfaces), one group of test bus interface 1 connects one of the described circuit-under-test independently test bus interface of scan chain circuit, and perhaps two groups of test bus interfaces 1 connect two of the described circuit-under-test independently test bus interfaces of scan chain circuit simultaneously.Every group of test bus interface 1 comprises the test reset line
Test clock line (TCK), test pattern are selected line (TMS), test data output line (TDO), test data input line (TDI).The serial scan module is according to IEEE 1149.1 standard output test mode select signals (TMS), arrive circuit-under-test in test access port (TAP) controller shift order registered state and shifted data registered state by test data output line (TDO) transmission test command and test data, the while is the serial test result of Data In-Line (TDI) reception circuit-under-test after tested.
Described counting module is counted data displaced condition, instruction shift state and three kinds of states of test run/idle condition of test access port (TAP) controller of circuit-under-test.Test instruction/the vector of circuit-under-test is when shift order/data registered state, in the clock period of a test clock (TCK) displacement 1 bit instruction/data, the number of times of displacement is the number of bits of test instruction/vector, and the number of bits of described test instruction is the summation of number of bits of the boundary scan testing instruction of each chip in the circuit-under-test scan chain; The number of bits of described test vector is the summation of the boundary scan cell number of each chip in the circuit-under-test boundary scan chain.
Described command module comprises reset command, test run/free time order, instruction scan order and data scanning order four class instructions.described reset command makes test access port (TAP) controller of circuit-under-test enter the test logic reset mode for output test mode select signal (TMS), described test run/free time order makes test access port (TAP) controller of circuit-under-test enter test run/idle condition for output test mode select signal (TMS), described instruction scan order mainly comprises shift order registered state or two steady state (SS)s of pause instruction registered state, command module output test mode select signal (TMS), make test access port (TAP) controller of circuit-under-test be in the shift order registered state, the test access port of circuit-under-test (TAP) controller under this state at clock period serial-shift one bit instruction of a test clock (TCK), the counting module of this mixed signal circuit Boundary Scan Controller is counted test clock (TCK) simultaneously, when the instruction figure place of actual shift during less than the instruction length of 32 digit counters indications, output test mode select signal (TMS) makes test access port (TAP) controller of circuit-under-test enter test run/idle condition, the instruction figure place of actual shift is during greater than the instruction length of 32 digit counters indications, output test mode select signal (TMS) makes test access port (TAP) controller of circuit-under-test enter the pause instruction registered state, wait for again receiving instruction, complete the shifting function of remaining instruction.described data scanning order, mainly comprise the instruction that makes circuit-under-test be in the shifted data registered state and suspend two steady state (SS)s of data registered state, command module output test mode select signal (TMS), make test access port (TAP) controller of circuit-under-test be in the shifted data registered state, the test access port of circuit-under-test (TAP) controller under this state in the clock period of test clock TCK serial-shift a data, the counting module of this mixed signal circuit Boundary Scan Controller is counted test clock TCK simultaneously, when the data bits of actual shift during less than the data length of 32 digit counters indications, output test mode select signal (TMS) makes test access port (TAP) controller of circuit-under-test enter test run/idle condition, the data bits of actual shift is during greater than the data length of 32 digit counters indications, output test mode select signal (TMS) makes test access port (TAP) controller of circuit-under-test enter time-out data registered state, wait for receive data again, complete the shifting function of data left.
Described general purpose register set, be used for controlling the control that this mixed signal circuit Boundary Scan Controller is completed different operations, comprise configuration register, command register, status register, test data input buffer, test data output buffer and 32 digit counters.
Described configuration register, be 16 read/writable registers, the testing clock frequency, the test pattern that are used for two groups of test bus interfaces of this mixed signal circuit of configuration Boundary Scan Controller select (TMS) output mode, test data output (TDO) output mode and circuit-mode to select four kinds of configuration informations, and the definition of concrete position and function are as shown in table 3:
Table 3, configuration register everybody definition and function list
Described command register is 16 read/writable registers, be divided into two groups of most-significant byte and least-significant bytes, two groups of test bus interfaces of respectively corresponding this mixed signal circuit Boundary Scan Controller mainly are divided into test reset, test run/free time, instruction scan and data scanning four class orders; The definition of concrete position and function are as shown in table 4:
Table 4, command register everybody definition and function list
Described status register, it is the read-only register of 16, be divided into two groups of most-significant byte and least-significant bytes, represent respectively the state for the running status of two groups of test bus interfaces and tested analog circuit test response results of test access port (TAP) controller of the circuit-under-test scan chain circuit that two groups of test bus interfaces connect.The definition of concrete position and function are as shown in table 5:
Table 5, status register everybody definition and function list
Described test data input buffer, be 4 16 read-only first in first out (FIFO) registers, be used for preserving the test result of the circuit-under-test that moves into by test data input line (TDI) serial, two groups of test bus interfaces have respectively independently test data input buffer.
Described test data output buffer, be 4 16 and only write first in first out (FIFO) register, be used for preserving test instruction or the test vector that shifts out by test data output line (TDO) serial, two groups of test bus interfaces have respectively independently test data output buffer.
Described 32 digit counters, it is the read/writable register of 32, the figure place that is used for recording instruction displacement or data displacement, namely realize the counting to the clock period of test clock frequency divider (TCK), when carrying out boundary scan testing with assurance, the test instruction of circuit-under-test test data input line (TDI) input or the figure place of test vector are correct.Two groups of test bus interfaces have respectively independently 32 digit counters.
Described simulation register group comprises frequency register, amplitude registers, effective value register and user register.Described frequency register is 48 read-only registers, and this example is used for preserving the programme-controlled signal source current excitation frequency control information of analog meter platform; Described amplitude registers is 48 read-only registers, and this example is used for the current excitation amplitude control information of the programme-controlled signal source of preservation analog meter platform; Described effective value register is 48 write-only registers, be used for to preserve the AC/DC voltage responsive result that the voltage collector of analog meter platform collects; This routine user register is 48 read/writable registers, has 3 groups, by user's self-defining purposes as required.
Above-described embodiment is only the specific case that the purpose of this utility model, technical scheme and beneficial effect are further described, and the utility model is not to be defined in this.All any modifications of making, be equal to replacement, improvement etc., within all being included in protection domain of the present utility model within scope of disclosure of the present utility model.
Claims (7)
1. the mixed signal circuit Boundary Scan Controller, comprise host module and the counting module, the command module that are connected with host module through the bus that reads and writes data, and be furnished with processor interface and test bus interface, it is characterized in that:
Described host module is also through the bus connecting test Clock dividers that reads and writes data, general purpose register set, simulation register group, serial scan module and analog meter platform control module; Described analog meter platform control module is furnished with the mixed signal control interface, and this interface connects the programme-controlled signal source that produces voltage or current excitation signal and connects with the voltage collector that is connected circuit-under-test voltage responsive signal; Described circuit-under-test is for supporting the circuit of IEEE 1149.1 or IEEE 1149.4 standards.
2. mixed signal circuit Boundary Scan Controller according to claim 1 is characterized in that:
Described host module is furnished with processor interface, and processor interface comprises 16 BDB Bi-directional Data Bus, 5 bit address lines, reading signal lines, write signal line, line of chip select, interrupt request line and reseting signal line.
3. mixed signal circuit Boundary Scan Controller according to claim 1 is characterized in that:
Described serial scan module is furnished with two groups of test bus interfaces, one group of test bus interface connects one of the described circuit-under-test independently test bus interface of scan chain circuit, and perhaps two groups of test bus interfaces connect two of the described circuit-under-test independently test bus interfaces of scan chain circuit simultaneously; Every group of test bus interface comprises test reset line, test clock line, test pattern selection line, test data output line, test data input line.
4. mixed signal circuit Boundary Scan Controller according to claim 1 is characterized in that:
Described mixed signal control interface be serial peripheral from the pattern interface, be furnished with serial peripheral holotype interface take the analog meter platform as main frame, be furnished with serial peripheral take this mixed signal circuit Boundary Scan Controller as slave from the pattern interface; The analog meter platform comprises circuit-under-test produced the programme-controlled signal source of voltage or current excitation signal and gathers the voltage collector of circuit-under-test response signal, and the serial peripheral of slave is connected with the serial peripheral holotype interface of main frame from the pattern interface and carries out exchanges data.
5. mixed signal circuit Boundary Scan Controller according to claim 4 is characterized in that:
Described serial peripheral comprises that from the pattern interface clock line, slave select line, main frame to export the slave input line and main frame is inputted the slave output line, and this serial peripheral meets the requirement of serial peripheral standard time sequence from the pattern interface.
6. mixed signal circuit Boundary Scan Controller according to claim 1 is characterized in that:
Described general purpose register set comprises configuration register, command register, status register, test data input buffer, test data output buffer and 32 digit counters;
Described configuration register is 16 read/writable registers;
Described command register is 16 read/writable registers, is divided into two groups of most-significant byte and least-significant bytes;
Described status register is the read-only register of 16, is divided into two groups of most-significant byte and least-significant bytes;
Described test data input buffer is 4 16 read-only first-in first-out registers, and two groups of test bus interfaces have respectively independently test data input buffer;
Described test data output buffer is 4 16 first-in first-out registers of only writing, and two groups of test bus interfaces have respectively independently test data output buffer;
Described 32 digit counters are the read/writable register of 32, and two groups of test bus interfaces have respectively independently 32 digit counters.
7. mixed signal circuit Boundary Scan Controller according to claim 1 is characterized in that:
Described simulation register group comprises frequency register, amplitude registers, effective value register and user register;
Described frequency register is 48 read-only registers;
Described amplitude registers is 48 read-only registers;
Described effective value register is 48 write-only registers;
Described user register is 48 read/writable registers, has 1～3 group.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102809934A (en) * | 2012-08-20 | 2012-12-05 | 桂林电子科技大学 | Boundary scan test controller for mixed signal circuit |
| CN103558544A (en) * | 2013-10-25 | 2014-02-05 | 中国航空综合技术研究所 | Digital-analog hybrid circuit built-in test device based on boundary scan |
| CN111856251A (en) * | 2020-08-03 | 2020-10-30 | 泰州市博泰电子有限公司 | Mobile communication circuit board test system |
| TWI752886B (en) * | 2020-11-02 | 2022-01-11 | 大陸商創意電子（南京）有限公司 | System in package element testing system based on boudary scan circuit |
| CN114113990A (en) * | 2021-08-31 | 2022-03-01 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Embedded boundary scan controller |
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- 2012-08-20 CN CN 201220413127 patent/CN202929399U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102809934A (en) * | 2012-08-20 | 2012-12-05 | 桂林电子科技大学 | Boundary scan test controller for mixed signal circuit |
| CN103558544A (en) * | 2013-10-25 | 2014-02-05 | 中国航空综合技术研究所 | Digital-analog hybrid circuit built-in test device based on boundary scan |
| CN111856251A (en) * | 2020-08-03 | 2020-10-30 | 泰州市博泰电子有限公司 | Mobile communication circuit board test system |
| TWI752886B (en) * | 2020-11-02 | 2022-01-11 | 大陸商創意電子（南京）有限公司 | System in package element testing system based on boudary scan circuit |
| CN114113990A (en) * | 2021-08-31 | 2022-03-01 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Embedded boundary scan controller |
| CN114113990B (en) * | 2021-08-31 | 2023-08-04 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Embedded boundary scan controller |
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