CN103163451B - Super computing system oriented self-gating boundary scan test method and device - Google Patents
Super computing system oriented self-gating boundary scan test method and device Download PDFInfo
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- CN103163451B CN103163451B CN201310071178.0A CN201310071178A CN103163451B CN 103163451 B CN103163451 B CN 103163451B CN 201310071178 A CN201310071178 A CN 201310071178A CN 103163451 B CN103163451 B CN 103163451B
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Abstract
The invention discloses a super computing system oriented self-gating boundary scan test method and a super computing system oriented self-gating boundary scan test device. The method comprises the following steps of: calculating to obtain the optimum test joint test action group (JTAG) line according to an input target main board number, a test command and test concurrency to determine a JTAG output port of a monitoring main board and send a control signal; and receiving the control signal of a JTAG gate by using a crossbar network on a rear panel, and changing turn-on and turn-off of each switch in the crossbar switch network according to the control signal to finish gating and executing a test command by using the gated JTAG output port. The device comprises a JTAG controller and the JTAG gate which are positioned on the monitoring main board, and a crossbar switch network module positioned on the rear panel. The method and the device have the advantages of simple structure, few rear panel wire, high test flexibility, high test efficiency and balanced JTAG line load.
Description
Technical field
The present invention is mainly concerned with boundary scan and adjusts technical field of measurement and test, refer in particular to a kind of towards super computer system from gating boundary scan commissioning method for testing and device.
Background technology
Boundary scan (Boundary Scan Test) technology utilizes additional boundary scan cell and steering logic thereof in chip pin to realize the tune test function irrelevant with packaged type, has overcome that tradition " probe " method efficiency is low, cost is high and the problem such as poor reliability.Nineteen ninety U.S. electric and electronic engineering association (IEEE) ratified the boundary scan testing standard that JTAG (Joint Test Action Group) is drafted, formed ieee standard 1149.1, be called for short JTAG standard.Boundary scan technique, since proposing, has been widely used in adjusting the line between internal logic, the line between chip and the complicated printed board (PCB) of test chip, has greatly shortened the process that large scale integrated circuit and PCB research and development are produced.
Nearly all chip all has jtag interface at present.According to JTAG standard, jtag interface provides the boundary scan chain of five pins for access destination chip, and it comprises that data input pin TDI, data output pin TDO, test pattern select pin TMS, test clock pin TCK and optional reset pin TRST.On chip, the inner additional boundary scan cell of other pins is concatenated together, and has formed boundary scan register (boundary scan chain).Test data is inputted boundary scan register from TDI, and outputs test result from TDO.
Super computer system adopts mainboard to rack, rack, to arrive the system architecture of system to subrack, subrack conventionally again.In order to guarantee reliability, availability and the serviceability of system, in each subrack, be conventionally inserted with at least one monitoring mainboard, be responsible for the tune test job of function mainboard in this subrack, and state during supervisory control system running.Along with the lifting of application level and the expansion of application, the scale of super computer system is more and more huger, and in a performance 10P level super computer system, mainboard number is up to ten thousand easily, and in single subrack, function mainboard number grows with each passing day; Meanwhile, the function of integrated chip is also more and more, and on mainboard, device density improves constantly, and it is more tediously long, complicated that boundary scan chain becomes.Therefore to have mainboard to be measured many for the single subrack commissioning examination in super computer system, the features such as scan chain complexity.How making good use of existing JTAG technique to high-efficiency and realize single subrack commissioning examination, is one of super computer system major issue urgently to be resolved hurrily.
The tune test optimization that the patent that great majority are relevant to boundary scan and paper are mainly paid close attention to single mainboard or chip, as Chinese invention patent 201120079849.4, Chinese invention patent 201110254917.0 and Chinese invention patent 201210090599.3 etc.Published boundary scan commissioning electricity testing device and method towards super computer system is less at present.As Chinese invention patent 200710143086.4 provides a kind of border scanning system and method based on high-performance calculation communication construction, the method is connected in mainboard to be measured on jtag bus, can only carry out commissioning examination to a mainboard at every turn, and efficiency is lower.And for example Chinese invention patent 201210083040.8 provides the parallel boundary scan device of a kind of efficient multilink and method, what the method adopted equally is jtag bus form cabling mode, but the boundary scan chain of polylith mainboard is connected into an integral body, can to polylith mainboard, carry out commissioning examination simultaneously.Yet the weak point of the method is that different mainboards to be measured can only adopt identical tune test command and test data at every turn, dirigibility is poor.For commissioning examination realizes maximum concurrency, monitoring mainboard can be all mainboards to be measured independent JTAG circuit is all set in addition, although can be simultaneously in subrack arbitrarily mainboard carry out commissioning examination, yet there is the defect of backboard cabling complexity in this kind of method.
Summary of the invention
The technical problem to be solved in the present invention is just: the technical matters existing for prior art, the invention provides that a kind of structure is more simple, backboard cabling is less, commissioning examination dirigibility is better, adjust that testing efficiency is higher, the equilibrium of JTAG line load towards super computer system from gating boundary scan commissioning method for testing and device.
For solving the problems of the technologies described above, the present invention by the following technical solutions:
A kind of towards super computer system from gating boundary scan commissioning method for testing, according to input target mainboard number, adjust test command and commissioning examination concurrency to calculate optimum commissioning examination JTAG circuit, to determine monitoring mainboard JTAG output port and to send control signal; Utilize the control signal of the cross bar switch network reception JTAG gate on backboard, according to control signal, change the break-make of each switch in cross bar switch network, complete gating and utilize the JTAG output port of gating to carry out tune test command.
As a further improvement on the present invention:
When carrying out gating, the destination register of some is set according to the number of mainboard to be measured, certain is 1 and identifies this corresponding mainboard to be measured of gating, otherwise this position is 0; Meanwhile, jtag port register is set, certain is that 1 this corresponding JTAG output port of sign is occupied.
The idiographic flow of described gating is: the target mainboard number of the tune test command of entry terminal, then obtain the current value of destination register and port register, and judgement target mainboard is in the value of the corresponding position of destination register:
● if corresponding position is 1, represents that certain concurrent user carries out commissioning examination to this target mainboard, so gating failure, to monitor terminal, returns to the busy signal of this target mainboard;
● if corresponding position is 0, step-by-step search port register:
■ when a certain position is 0 in finding port register, records this port numbers, stops search; According to port numbers and mainboard number, build the control signal of cross bar switch network, transmit control signal to the cross bar switch network on backboard, and the corresponding position of destination register and port register is put respectively to 1, notify jtag controller to utilize corresponding port to carry out this tune test command simultaneously; Otherwise gating failure, returns to the busy signal of port to monitor terminal and builds.
The present invention further provides a kind of device that is used for realizing above-mentioned method of testing, it comprises:
Jtag controller, is positioned on monitoring mainboard;
JTAG gate, is positioned on monitoring mainboard, and the destination register of some is set according to the number of mainboard to be measured in described JTAG gate, and certain is 1 and identifies this corresponding mainboard to be measured of gating, otherwise this position is 0; The jtag port register of monitoring mainboard is set in described JTAG gate, and certain is that 1 this corresponding JTAG output port of sign is occupied; In described JTAG gate, arrange from gating module, described from gating module according to input target mainboard number, adjust test command and commissioning examination concurrency to calculate optimum commissioning examination JTAG circuit, to determine monitoring mainboard JTAG output port;
Cross bar switch network module, is positioned on backboard, and described cross bar switch network module is connected with JTAG gate by control signal wire, changes the break-make of each switch in cross bar switch network according to control signal.
Described jtag controller customizes jtag controller and JTAG output port according to commissioning examination concurrency, mainboard number to be measured on monitoring mainboard.
Described JTAG output port number is less than or equal to mainboard number to be measured and is less than the commissioning examination concurrency that monitoring mainboard can bear.
Compared with prior art, the invention has the advantages that:
1, the present invention dynamically realizes multiple JTAG cabling mode by JTAG gate and cross bar switch network module in adjusting test process, comprises serial, parallel and serial parallel mixing, has greatly improved the dirigibility of commissioning examination.
2, the present invention effectively reduces the number of backboard cabling, takes full advantage of limited JTAG circuit, according to concurrent demand, realizes maximum boundary scan degree of parallelism, and load that can balance JTAG circuit.
3, the present invention, compared with serial boundary scan cabling mode, has higher tune testing efficiency.The present invention can be concurrent difference mainboard to be measured carried out to different tune test commands, improved the efficiency of commissioning examination.
Accompanying drawing explanation
Fig. 1 is the logical organization schematic diagram of commissioning electricity testing device of the present invention.
Fig. 2 is the schematic flow sheet of gating method of the present invention.
Fig. 3 is the schematic diagram of cross bar switch network module in the present invention.
Embodiment
Below with reference to Figure of description and specific embodiment, the present invention is described in further details.
Of the present invention towards super computer system from gating boundary scan commissioning method for testing, according to input target mainboard number, adjust test command and commissioning examination concurrency to calculate optimum commissioning examination JTAG circuit, to determine monitoring mainboard JTAG output port and to send control signal; Utilize the control signal of the cross bar switch network reception JTAG gate on backboard, according to control signal, change the break-make of each switch in cross bar switch network, complete gating and utilize the JTAG output port of gating to carry out tune test command.
When carrying out gating, the destination register of some is set according to the number of mainboard to be measured, certain is 1 and identifies this corresponding mainboard to be measured of gating, otherwise this position is 0; Meanwhile, jtag port register is set, certain is that 1 this corresponding JTAG output port of sign is occupied.
Referring to Fig. 2, in this example, the idiographic flow of gating is: the target mainboard number of the tune test command of entry terminal, then obtain the current value of destination register and port register, and judgement target mainboard is in the value of the corresponding position of destination register:
● if corresponding position is 1, represents that certain concurrent user carries out commissioning examination to this target mainboard, so gating failure, to monitor terminal, returns to the busy signal of this target mainboard;
● if corresponding position is 0, step-by-step search port register:
■ when a certain position is 0 in finding port register, records this port numbers, stops search; According to port numbers and mainboard number, build the control signal of cross bar switch network, transmit control signal to the cross bar switch network on backboard, and the corresponding position of destination register and port register is put respectively to 1, notify jtag controller to utilize corresponding port to carry out this tune test command simultaneously; Otherwise gating failure, returns to the busy signal of port to monitor terminal and builds.
As shown in Figure 1, the present invention further provides a kind of towards super computer system from gating boundary scan commissioning electricity testing device, comprise being positioned at jtag controller and the JTAG gate of monitoring on mainboard, being positioned at the cross bar switch network module on backboard.
Jtag controller is on monitoring mainboard, and the number of definite JTAG output port.That is, on monitoring mainboard, according to commissioning examination concurrency, mainboard number to be measured, customize jtag controller and JTAG output port.As mode preferably, require JTAG output port number to be less than or equal to mainboard number to be measured, and be less than the commissioning that monitoring mainboard can bear and try concurrency.
JTAG gate, on monitoring mainboard, in JTAG gate, arranges the destination register of some according to the number of mainboard to be measured, certain is 1 and identifies this corresponding mainboard to be measured of gating, otherwise this position is 0; Meanwhile, the jtag port register of monitoring mainboard is set in JTAG gate, certain is that 1 this corresponding JTAG output port of sign is occupied.In JTAG gate from gating module can be according to input target mainboard number, adjust test command and commissioning examination concurrency to calculate optimum commissioning examination JTAG circuit, to determine monitoring mainboard JTAG output port.
Cross bar switch network module, on backboard, according to the JTAG output port quantity of monitoring mainboard and the mainboard number to be measured in subrack, builds the cross bar switch network module that JTAG circuit forms on backboard.Referring to Fig. 3, for example, on monitoring mainboard, there are 4 road JTAG output ports, in subrack, there are 16 mainboards to be measured, on backboard, build 4 * 16 cross bar switch network module, each road JTAG is 5 signal line, comprises TDI, TDO, TMS, TCK and enable signal.Cross bar switch network module is connected with JTAG gate by control signal wire, changes the break-make of each switch in cross bar switch network according to control signal.
In concrete application, when monitoring mainboard starts, JTAG gate is first by destination register and the zero clearing of jtag port register.After commissioning runin is begun, mainboard to be measured in user command number is inputted from gating module, select idle JTAG output port, and according to the value of destination register and jtag port register, by the cross bar switch network module in control signal wire toward back plate, transmit control signal, with in closed cross bar switch network module to inductive switch, complete gating; Meanwhile, notice jtag controller utilizes the JTAG output port of gating to carry out and adjusts test command.When having completed the tune test command of terminal, jtag controller discharges notice JTAG gate by the response bit of destination register and jtag port register, to prepare to receive new order.
Below be only the preferred embodiment of the present invention, protection scope of the present invention is also not only confined to above-described embodiment, and all technical schemes belonging under thinking of the present invention all belong to protection scope of the present invention.It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principles of the present invention, should be considered as protection scope of the present invention.
Claims (4)
- One kind towards super computer system from gating boundary scan commissioning method for testing, it is characterized in that, according to input target mainboard number, adjust test command and commissioning examination concurrency to calculate optimum commissioning examination JTAG circuit, to determine monitoring mainboard JTAG output port and to send control signal; Utilize the control signal of the cross bar switch network reception JTAG gate on backboard, according to control signal, change the break-make of each switch in cross bar switch network, complete gating and utilize the JTAG output port of gating to carry out tune test command;When carrying out gating, the destination register of some is set according to the number of mainboard to be measured, certain is 1 and identifies this corresponding mainboard to be measured of gating, otherwise this position is 0; Meanwhile, jtag port register is set, certain is that 1 this corresponding JTAG output port of sign is occupied;The idiographic flow of gating is: the target mainboard number of test command is adjusted in terminal input, then obtains the current value of destination register and port register, and judgement target mainboard is in the value of the corresponding position of destination register:● if corresponding position is 1, represents that certain concurrent user carries out commissioning examination to this target mainboard, so gating failure, to monitor terminal, returns to the busy signal of this target mainboard;● if corresponding position is 0, step-by-step search port register:■ when a certain position is 0 in finding port register, records this port numbers, stops search; According to port numbers and mainboard number, build the control signal of cross bar switch network, transmit control signal to the cross bar switch network on backboard, and the corresponding position of destination register and port register is put respectively to 1, notify jtag controller to utilize corresponding port to carry out this tune test command simultaneously; Otherwise gating failure, returns to the busy signal of port to monitor terminal and builds.
- 2. be used for realizing described in claim 1 from a device for gating boundary scan commissioning method for testing, it is characterized in that, comprising:Jtag controller, is positioned on monitoring mainboard;JTAG gate, is positioned on monitoring mainboard, and the destination register of some is set according to the number of mainboard to be measured in described JTAG gate, and certain is 1 and identifies this corresponding mainboard to be measured of gating, otherwise this position is 0; The jtag port register of monitoring mainboard is set in described JTAG gate, and certain is that 1 this corresponding JTAG output port of sign is occupied; In described JTAG gate, arrange from gating module, described from gating module according to input target mainboard number, adjust test command and commissioning examination concurrency to calculate optimum commissioning examination JTAG circuit, to determine monitoring mainboard JTAG output port;Cross bar switch network module, is positioned on backboard, and described cross bar switch network module is connected with JTAG gate by control signal wire, changes the break-make of each switch in cross bar switch network according to control signal.
- 3. device according to claim 2, is characterized in that: described jtag controller customizes jtag controller and JTAG output port according to commissioning examination concurrency, mainboard number to be measured on monitoring mainboard.
- 4. device according to claim 3, is characterized in that: described JTAG output port number is less than or equal to mainboard number to be measured and is less than the commissioning examination concurrency that monitoring mainboard can bear.
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| CN109901045A (en) * | 2017-12-08 | 2019-06-18 | 英业达科技有限公司 | The connector plugging slot pin conduction detecting system and its method of circuit board |
| CN110750086B (en) * | 2019-09-02 | 2020-11-17 | 芯创智（北京）微电子有限公司 | Digital logic automatic testing device and method |
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| CN100370269C (en) * | 2003-11-19 | 2008-02-20 | 华为技术有限公司 | Boundary scanning testing controller and boundary scanning testing method |
| CN100426252C (en) * | 2006-11-24 | 2008-10-15 | 华为技术有限公司 | Device and method to regulate automatically data sampling dot of output interface of testing data |
| CN101141317B (en) * | 2007-04-12 | 2011-11-23 | 中兴通讯股份有限公司 | Automatic testing equipment and method for multiple JTAG chain |
| CN101105782B (en) * | 2007-08-22 | 2011-08-24 | 中兴通讯股份有限公司 | Border scanning system based on high-performance computer communication framework and method therefor |
| CN101470169B (en) * | 2007-12-27 | 2012-01-11 | 华为技术有限公司 | Method, system and apparatus for fault detection of tested device |
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| CN102043122B (en) * | 2011-01-17 | 2012-12-05 | 哈尔滨工业大学 | Improved scan chain unit and non-concurrent testing method based on same |
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