CN104459522A - Chip self-test method and system - Google Patents
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Abstract
The invention provides a chip self-test method executed by a self-test system; the method comprises the following steps: the self-test system respectively generates a serial debug command sequential macrodefinition set and a test control scheme macrodefinition set; the self-test system obtains front end logic information of the chip; the self-test system generates a test vector file according to the front end logic information, the sequential macrodefinition set and the test control scheme macrodefinition set; the self-test system writes the test vector file into a tested chip through a test machine, and receives a test result returned by the test machine. The chip self-test method can fast and effectively verify SOC global address space, is simple in operation, easy to realize, and the method has high transplantability and connectivity; in addition, the method can save resources, and reduces test cost; the invention also provides the chip self-test system.
Description
Technical field
The present invention relates to embedded and SOC technical field, particularly a kind of chip self-testing method and system.
Background technology
At present, at embedded and SOC(System On Chip, SOC (system on a chip)) in field, at design and Qualify Phase, generally by loading external signal excitation or downloading the method that testing software is driven into SOC inside, the integrality of the correctness of test and check SOC internal trigger and functional realiey, the accordance of sequential and system.
Specifically, at Front-end Design Qualify Phase, do not use debugging interface function, and compiled Test driver file is passed through EDA design and simulation tool loads in SOC code storage model, then to design loading simulation external signal test and excitation, file is driven, observation test result, to reach the object testing and verify this design by emulation tool testing results.At engineering verification test phase, by debugging interface, Test driver is downloaded in SOC internal code memory bank, then the excitation of true external signal is loaded to SOC, run SOC system and carry out testing authentication.
But, in the SOC design verification stage, by current method of testing, cannot complete detection SOC system functional in the process of front end, whole debugging testing process cannot be authenticated to, the basic application function of SOC can only be authenticated to.Secondly, in checking external testing debug process, sometimes need to increase FPGA(Field Programmable GateArray, field programmable gate array in design front-end phase) plate level verification and external debug assembly, thus add the cost of great number.Meanwhile, current method of testing, when detecting SOC full address space read-write capability, shortage dirigibility, software needs constantly amendment-compiling-loading, and different register testing situation is more simultaneously, and on time and resource, utilization factor is not high.
In addition, external signal test and debugging function is applied very extensive after real SOC product design output, is all used in sweep test, solidification code, debugging upgrading and systems axiol-ogy etc. are numerous.What require in low cost designs and develops in process, there is no FPGA plate level verification process, until after design realization, use real wafer or print to go to test such function, considerably increase risk.Once this functional realiey goes wrong, product design will return front-end phase, greatly waste test duration and test resource, in the delay product cycle, even may lose the market opportunity.
Summary of the invention
The present invention is intended at least one of solve the problems of the technologies described above.
For this reason, one object of the present invention is to propose a kind of chip self-testing method, the method can fast and effeciently be verified SOC global address space, and simple to operate, easily realize, the method also has higher portability and connectivity, in addition, can saving resource in the method implementation procedure, reduce testing cost.
Another object of the present invention is to provide a kind of chip self-measuring system.
To achieve these goals, the embodiment of first aspect present invention proposes a kind of chip self-testing method, described method is performed by self-measuring system, said method comprising the steps of: self-measuring system generates serial debug command timing macro definition collection and testing and control scheme macro definition collection respectively; Described self-measuring system obtains the front end logic information of chip; Described self-measuring system generates test vector file according to described front end logic information, described sequential macro definition collection and testing and control scheme macro definition collection; And described test vector file is write to chip to be measured by test machine by described self-measuring system, and receive the test result of described test machine feedback.
According to the chip self-testing method of the embodiment of the present invention, test to serial debug flow process can be realized in system-on-chip designs front end, fundamentally ensure that SOC(SOC (system on a chip)) debug the correctness of test function; In addition, the method without the need to increasing external module, thus reduces testing cost; The method can fast and effectively for the checking of SOC global address space, simple to operate and easily realize; Meanwhile, the method can run through and is applied to whole SOC and designs and develops the production test stage, and therefore its connectivity is higher.
Second aspect present invention embodiment still provides a kind of chip self-measuring system, it is characterized in that, comprising: module of testing oneself, described in module of testing oneself generate serial debug command timing macro definition collection and testing and control scheme macro definition collection respectively; Acquisition module, described acquisition module is for obtaining the front end logic information of chip; Test vector generation module, described test vector generation module is used for generating test vector file according to described front end logic information, described sequential macro definition collection and testing and control scheme macro definition collection; And writing module, said write module is used for, by test machine, described test vector file is write to chip to be measured, and receives the test result of described test machine feedback.
According to the chip self-measuring system of the embodiment of the present invention, test to serial debug flow process can be realized in system-on-chip designs front end, fundamentally ensure that SOC(SOC (system on a chip)) debug the correctness of test function; In addition, this system without the need to increasing external module, thus reduces testing cost; This system can fast and effectively for the checking of SOC global address space, and system architecture is simple and easy and simple to handle; Meanwhile, this system can run through and is applied to whole SOC and designs and develops the production test stage, and therefore its connectivity is higher.
Additional aspect of the present invention and advantage will part provide in the following description, and part will become obvious from the following description, or be recognized by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or additional aspect of the present invention and advantage will become obvious and easy understand from accompanying drawing below combining to the description of embodiment, wherein:
Fig. 1 is the process flow diagram of chip self-testing method according to an embodiment of the invention;
Fig. 2 is the system architecture of the self-measuring system of chip self-testing method according to an embodiment of the invention and platform schematic diagram of testing oneself;
Fig. 3 is the design basis ground motion principle schematic of chip self-testing method according to an embodiment of the invention;
Fig. 4 is that the test vector file of chip self-testing method according to an embodiment of the invention generates schematic diagram;
Fig. 5 is the process flow diagram of chip self-testing method in accordance with another embodiment of the present invention; With
Fig. 6 is the structural representation of chip self-measuring system according to an embodiment of the invention.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
In describing the invention, it will be appreciated that, term " " center ", " longitudinal direction ", " transverse direction ", " on ", D score, " front ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " end ", " interior ", orientation or the position relationship of the instruction such as " outward " are based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, instead of indicate or imply that the device of indication or element must have specific orientation, with specific azimuth configuration and operation, therefore limitation of the present invention can not be interpreted as.In addition, term " first ", " second " only for describing object, and can not be interpreted as instruction or hint relative importance.
In describing the invention, it should be noted that, unless otherwise clearly defined and limited, term " installation ", " being connected ", " connection " should be interpreted broadly, and such as, can be fixedly connected with, also can be removably connect, or connect integratedly; Can be mechanical connection, also can be electrical connection; Can be directly be connected, also indirectly can be connected by intermediary, can be the connection of two element internals.For the ordinary skill in the art, concrete condition above-mentioned term concrete meaning in the present invention can be understood.
Below in conjunction with accompanying drawing description according to the chip self-testing method of the embodiment of the present invention and system.
Fig. 1 is the process flow diagram of chip self-testing method according to an embodiment of the invention.As shown in Figure 1, chip self-testing method according to an embodiment of the invention, wherein, the method is performed by self-measuring system, and the method comprises the following steps:
Step S101, self-measuring system generates serial debug command timing macro definition collection and testing and control scheme macro definition collection respectively.
As a concrete example, as shown in Figure 3, this chip self-testing method realizes relating generally to when testing oneself SW command timing macro definition collection, SOC testing and control scheme macro definition collection, order and data to reorder the functional modules such as logic, test vector file formation logic, vectorial transmission control logic and test clock steering logic in conjunction with logic, test vector.In above-mentioned steps S101, be mainly concerned with SW command timing macro definition collection and SOC testing and control scheme macro definition collection two functional modules.
Specifically, SW(Serial Wire, string line) command timing macro definition collection and serial debug command timing macro definition collection.It is included in SW serial debug agreement the sequential of carrying out required for test and debugging.Particularly, each sequential carried out integrating and macro definition, for testing oneself, logic is called.Such as: SW reset command is that SWDIO inputs 50 cycle 1, then macro definition defineRESET_ORDER11111 ... 11111(50 individual 1); SW reads IDCODE order: define READ_IDCODE1010_0101.Macro definition is carried out, to treat that self-measuring system calls by needing the SW timing command used with this.After this set has defined, without the need to 2 amendments, just can mate other SW based on ARM microprocessor completely and debug test.
SOC testing and control scheme macro definition collection and testing and control scheme macro definition collection.Specifically, different SOC has different testing and control scheme macro definition based on different designs framework.This set comprises address and address space, test data and the self-measuring system control configuration parameter of required test SOC.Such as: test address 1 is define A10000_1010; Test address 2 is define A21001_1000; The test data that test address 1 needs is define AD11101_0001; The test data that test address 2 needs is define AD20011_0100; SWCLK frequency control is define FSWCLK2(2M); A2 address testing sequence priority is define A2_PRI3; Output vector file system is defineCODEBOH2(scale-of-two).Thus, with this by the testing and control scheme of survey SOC be all integrated into this macro definition and concentrate, to treat that self-measuring system calls.When changing content measurement, only needing amendment or increasing and decreasing in this set to test macro definition accordingly to realize the change of testing scheme, thus there is very high portability, in addition, participate in without software in change procedure, have easy and simple to handle, the advantage that complexity is low and reliability is high.
Step S102, self-measuring system obtains the front end logic information of chip.
Step S103, self-measuring system generates test vector file according to front end logic information, sequential macro definition collection and testing and control scheme macro definition collection.Specifically, first, self-measuring system generates vector row group according to sequential macro definition collection and testing and control scheme macro definition collection, then reorders to generate test vector file to the vector in this vector row group according to front end logic information.Wherein, in one embodiment of the invention, testing and control scheme macro definition collection comprises address and address space, test data and the self-measuring system control configuration parameter of chip to be measured.
As a concrete example, shown in composition graphs 3, namely order calls SW command timing macro definition collection and SOC testing and control scheme macro definition collection with data in conjunction with logic module, and according to testing scheme regulation, automatically the control sequence specified in test command, test address, test data and testing scheme is combined into one group of continuous binary vector (as shown in Fig. 5 flow process).Specifically, such as shown in Fig. 4, by AD2 data in A2 address write vector 2 in vector 1, then call the TAR register command (vector 1) of A2 to SW assembly, call the DRW register (middle vectorial 2) of AD2 to SW assembly, and vector 1 and vector 2 are integrated by bind command, thus one group of test vector can be formed.Further, as shown in Figure 3 and Figure 5, the test vector logic module that reorders integrates according to SOC testing and control scheme macro definition and address space macro definition concentrates the test prioritization macro definition (such as PRI) of regulation, arranging order and the test vector group that data generate in conjunction with logic, complete the integration of whole SOC test vector and export from high to low.
Finally, the test vector after integration is generated corresponding binary file according to CODEBOH and exports by test vector file formation logic module.
Step S104, test vector file is write to chip to be measured by test machine by self-measuring system, and receives the test result of test machine feedback.Wherein, in one embodiment of the invention, chip to be measured is but is not limited to SOC (system on a chip) SOC.As a concrete example, shown in composition graphs 3, vector transmission control logic module is SW interface transmission control core, for vectorial to SOC input test, and according to SW sequential regulation, control SWCLK clock inputs, and the response that in treatment S OC, SW assembly returns (such as: OK response, WAIT response, ERROR response), and carry out different reply process, such as: OK responds, control vector transmission and access continue to carry out according to current normal condition; WAIT response then controls current vector transmission and suspends, and resends the vector of the current WAIT response be fed, or considers the transmission interrupting current vector; ERROR response needs transmission control logic module to confirm the correctness of SW agreement and the correctness of target response, and carries out reading IDCODE register or carrying out reset command.Vector transmission control logic module is also for making transmission meet the timing requirements of SW agreement and ensure the correctness of transmission and control the input/output state of two-way IO.Wherein, in figure 3, test clock steering logic module is used for being configured SWCLK frequency, and receives vectorial transmission control logic module to the control of Clock gating, with controls transfer sequential accurately.
In sum, in this self-testing method implementation procedure, when after self-measuring system startup optimization, the automatic testing scheme that specifies according to SOC testing and control scheme macro definition collection and flow process are tested by self-measuring system, test result statistics feedback the most at last.
According to the chip self-testing method of the embodiment of the present invention, test to serial debug flow process can be realized in system-on-chip designs front end, fundamentally ensure that SOC(SOC (system on a chip)) debug the correctness of test function; In addition, the method without the need to increasing external module, thus reduces testing cost; The method can fast and effectively for the checking of SOC global address space, simple to operate and easily realize; In addition, the method can run through and is applied to whole SOC and designs and develops the production test stage, and therefore its connectivity is higher.
Fig. 2 is the system architecture of the self-measuring system of chip self-testing method according to an embodiment of the invention and platform schematic diagram of testing oneself.
As shown in Figure 2, in this self-testing method implementation procedure, self-measuring system connects the SOC logic needing testing authentication by SWCLK and SWDIO, or the test vector file generated by self-measuring system is by production test board, inputs to the SOC that need test equally through SWCLK and SWDIO; The result produced after Receipt Validation test simultaneously.
Specifically, the principle that realizes of this chip self-testing method is: extracted one by one by timing command used in SW debug protocol, and by macrodefined formal definition, and it is concentrated with to be called to be integrated into serial debug command timing macro definition; And add up all address space, test data and the corresponding testing schemes needing to detect of current designed SOC, carry out macro definition according to testing requirement classification, and be integrated into SOC testing and control scheme macro definition and concentrate with to be called; And design a macro definition calling system, its interface meets the requirement of SW string line debugging interface, by the test address needed in the file of surveyed item, data and scheme row group after the command macro definition that serial debug command timing macro definition is concentrated is integrated, form continuous print test vector, automatically carry out testing authentication by SW string line.
In addition, when needs change test item or test condition, only need newly-increased item to be measured or change in item file to be measured, after having changed, self-measuring system forms follow-on test vector automatically, automatically carries out testing authentication by SW string line, thus has portability.
Further, the test vector generated by system, can preserve into the binary file of needs, can be used for the test of production test machine to SOC, therefore has higher connectivity.
It should be noted that, automatically complete in this test process by hardware, participate in without software, therefore, this method of testing also has easy and simple to handle, and complexity is low, the advantage that cost of development is low and reliability is high.
Fig. 5 is the process flow diagram of chip self-testing method in accordance with another embodiment of the present invention.As shown in Figure 5, chip self-testing method in accordance with another embodiment of the present invention, comprises the following steps:
Step S501, system is tested oneself.Namely chip is tested oneself beginning, and self-measuring system is started working.
Step S502, calls SW order and test address data.Particularly, timing command used in SW debug protocol is extracted one by one, and by macrodefined formal definition, and it is concentrated with to be called to be integrated into serial debug command timing macro definition; And add up all address space, test data and the corresponding testing schemes needing to detect of current designed SOC, carry out macro definition according to testing requirement classification, and be integrated into SOC testing and control scheme macro definition and concentrate with to be called.
Step S503, order and address and data assemblies.
Step S504, produces vector.Specifically, call SW command timing macro definition collection and SOC testing and control scheme macro definition collection, and according to testing scheme regulation, automatically the control sequence specified in test command, test address, test data and testing scheme is combined into one group of continuous binary vector.
Step S505, sorts to all test vectors according to initial order configuration.Specifically, concentrate the test prioritization macro definition of regulation according to SOC testing and control scheme macro definition collection and address space macro definition, arranging order and test vector group from high to low, completes the integration of whole SOC test vector and exports.
Step S506, the test vector group that generation order is determined.Namely, in above-mentioned steps S506, the test vector group of output is the test vector group that order is determined.
Step S507, by transmission control inputs to SOC.Specifically, transmission controls to SOC input test vector, and according to SW sequential regulation, control SWCLK clock inputs, and the response that in treatment S OC, SW assembly returns (such as: OK response, WAIT response, ERROR response), and carries out different reply process.Such as: OK responds, control vector transmission and access continue to carry out according to current normal condition; WAIT response then controls current vector transmission and suspends, and resends the vector of the current WAIT response be fed, or considers the transmission interrupting current vector; ERROR response needs transmission control logic module to confirm the correctness of SW agreement and the correctness of target response, and carries out reading IDCODE register or carrying out reset command.
Step S508, examination and assess test result.Namely receive and the test result of checkout machine feedback.
Does step S509, judge whether to need to revise testing requirement? if so, then perform step S510, otherwise perform step S512.
Step S510, amendment test address and data and other demands of test item.Namely, in above-mentioned steps S509, if judge to need to revise testing requirement, then test address and data and other demands of test item are revised.Specifically, when needs change test item or test condition, only need newly-increased item to be measured or change in item file to be measured, after having changed, self-measuring system forms follow-on test vector automatically, automatically carries out testing authentication by SW string line, thus has portability.
Step S511, test item macro definition file is preserved in amendment, and returns execution step S502.Specifically, the test vector that self-measuring system generates, can preserve into the binary file of needs, can be used for the test of production test machine to SOC, therefore have higher connectivity.
Step S512, terminates.Namely, in above-mentioned steps S509, when not needing amendment testing requirement, chip is terminated from flow gauge.
Step S513, produces test vector file according to the configuration of file system.In other words, namely after step s 505, further the test vector after integration generated corresponding binary file according to CODEBOH and export.
Step S514, exports the test vector file obtained.
In sum, and composition graphs 5 can obtain, the chip self-testing method of the embodiment of the present invention, on the one hand, can realizing when not increasing external module (as FPGA), designing front end, to the checking being carried out SOC test and debugging process by SW string line debug logic at SOC.On the other hand, when testing the read-write of space, SOC full address, do not rely on traditional software-driven test, by the verification system for SOC, by macro definition test file, in conjunction with SW agreement, simple and quick carrying out detects.
In addition, when self-measuring system is for another SOC design test based on ARM serial debug, only need change SOC testing and control scheme macro definition collection, guarantee that it meets the test to this SOC, without the need to changing self-measuring system, without the need to driving by testing software, therefore, easy to operate and efficiency is higher.
According to the chip self-testing method of the embodiment of the present invention, test to serial debug flow process can be realized in system-on-chip designs front end, fundamentally ensure that SOC(SOC (system on a chip)) debug the correctness of test function; In addition, the method without the need to increasing external module, thus reduces testing cost; The method can fast and effectively for the checking of SOC global address space, simple to operate and easily realize; In addition, for the testing authentication of the different SOC design based on string line, only need change control program macro definition collection, therefore, there is higher test portable; Meanwhile, the method can run through and is applied to whole SOC and designs and develops the production test stage, and therefore its connectivity is higher.
The invention allows for a kind of chip self-measuring system.Below in conjunction with accompanying drawing 6, the chip self-measuring system according to the embodiment of the present invention is described.
Fig. 6 is the structural representation of chip self-measuring system according to an embodiment of the invention.As shown in Figure 6, chip self-measuring system 600 according to an embodiment of the invention, comprising: module of testing oneself 610, acquisition module 620, test vector generation module 630 and writing module 640.
Specifically, module of testing oneself 610 generates serial debug command timing macro definition collection and testing and control scheme macro definition collection respectively.Wherein, in one embodiment of the invention, testing and control scheme macro definition collection comprises address and address space, test data and the self-measuring system control configuration parameter of chip to be measured.
Acquisition module 620 is for obtaining the front end logic information of chip.
Test vector generation module 630 is for generating test vector file according to front end logic information, sequential macro definition collection and testing and control scheme macro definition collection.Specifically, test vector generation module 630 for generating vector row group according to sequential macro definition collection and testing and control scheme macro definition collection, and reorders to generate test vector file to the vector in vector row group according to front end logic information.
Writing module 640 for test vector file being write to chip to be measured by test machine, and receives the test result of test machine feedback.Wherein, in one embodiment of the invention, chip to be measured is but is not limited to SOC (system on a chip) SOC.
According to the chip self-measuring system of the embodiment of the present invention, test to serial debug flow process can be realized in system-on-chip designs front end, fundamentally ensure that SOC(SOC (system on a chip)) debug the correctness of test function; In addition, this system without the need to increasing external module, thus reduces testing cost; This system can fast and effectively for the checking of SOC global address space, and system architecture is simple and easy and simple to handle; In addition, for the testing authentication of the different SOC design based on string line, only need change control program macro definition collection, therefore, there is higher test portable; Meanwhile, this system can run through and is applied to whole SOC and designs and develops the production test stage, and therefore its connectivity is higher.
In the description of this instructions, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.In this manual, identical embodiment or example are not necessarily referred to the schematic representation of above-mentioned term.And the specific features of description, structure, material or feature can combine in an appropriate manner in any one or more embodiment or example.
Although illustrate and describe embodiments of the invention, those having ordinary skill in the art will appreciate that: can carry out multiple change, amendment, replacement and modification to these embodiments when not departing from principle of the present invention and aim, scope of the present invention is by claim and equivalency thereof.
Claims (8)
1. a chip self-testing method, described method is performed by self-measuring system, it is characterized in that, comprises the following steps:
Described self-measuring system generates serial debug command timing macro definition collection and testing and control scheme macro definition collection respectively;
Described self-measuring system obtains the front end logic information of chip;
Described self-measuring system generates test vector file according to described front end logic information, described sequential macro definition collection and testing and control scheme macro definition collection; And
Described test vector file is write to chip to be measured by test machine by described self-measuring system, and receives the test result of described test machine feedback.
2. chip self-testing method as claimed in claim 1, is characterized in that, described testing and control scheme macro definition collection comprises address and address space, test data and the self-measuring system control configuration parameter of chip to be measured.
3. chip self-testing method as claimed in claim 1, is characterized in that, described self-measuring system generates test vector file according to described front end logic information, described sequential macro definition collection and testing and control scheme macro definition collection and comprises further:
Described self-measuring system generates vector row group according to described sequential macro definition collection and testing and control scheme macro definition collection; And
Reorder to generate described test vector file to the vector in described vector row group according to described front end logic information.
4. chip self-testing method as claimed in claim 1, it is characterized in that, described chip to be measured is SOC (system on a chip) SOC.
5. a chip self-measuring system, is characterized in that, comprising:
To test oneself module, described in module of testing oneself generate serial debug command timing macro definition collection and testing and control scheme macro definition collection respectively;
Acquisition module, described acquisition module is for obtaining the front end logic information of chip;
Test vector generation module, described test vector generation module is used for generating test vector file according to described front end logic information, described sequential macro definition collection and testing and control scheme macro definition collection; And
Writing module, said write module is used for, by test machine, described test vector file is write to chip to be measured, and receives the test result of described test machine feedback.
6. chip self-measuring system as claimed in claim 5, is characterized in that, described testing and control scheme macro definition collection comprises address and address space, test data and the self-measuring system control configuration parameter of chip to be measured.
7. chip self-measuring system as claimed in claim 5, it is characterized in that, described test vector generation module is used for generating vector row group according to described sequential macro definition collection and testing and control scheme macro definition collection, and reorders to generate described test vector file to the vector in described vector row group according to described front end logic information.
8. chip self-measuring system as claimed in claim 5, it is characterized in that, described chip to be measured is SOC (system on a chip) SOC.
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| CN102565685A (en) * | 2010-12-14 | 2012-07-11 | 苏州工业园区谱芯科技有限公司 | Logic built-in self-test system |
| CN102608518A (en) * | 2012-02-29 | 2012-07-25 | 华为技术有限公司 | Chip testing method and device |
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