CN104459522B - chip self-testing method and system - Google Patents
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Abstract
The present invention proposes a kind of chip self-testing method, wherein, this method is performed by self-measuring system, and this method comprises the following steps：Self-measuring system generates serial debug command sequential macrodefinition collection and testing and control scheme macrodefinition collection respectively；Self-measuring system obtains the front end logic information of chip；Self-measuring system generates test vector file according to front end logic information, sequential macrodefinition collection and testing and control scheme macrodefinition collection；And self-measuring system is write test vector file to chip to be measured by test machine, and receive the test result of test machine feedback.The chip self-testing method of the present invention can be verified fast and effeciently to SOC global address spaces, and simple to operate, easy realization, and method has higher portability and connectivity, in addition, can save resource in this method implementation process, reduce testing cost.Present invention also offers a kind of chip self-measuring system.
Description
Technical field
The present invention relates to embedded and SOC technical fields, more particularly to a kind of chip self-testing method and system.
Background technology
At present, in embedded and SOC（System On Chip, on-chip system）In field, in design and Qualify Phase,
Typically by loading external signal excitation or downloading test software driving to the method inside SOC, test and examine inside SOC and touch
The integrality of correctness, the accordance of sequential and system that hair device and function are realized.
Specifically, in Front-end Design Qualify Phase, without using debugging interface function, and by compiled Test driver text
Part, into SOC code storage model bodies, is then tested design loading simulation external signal by EDA design and simulations tool loads
Excitation, file is driven by emulation tool testing results, observes test result, with the purpose for reaching test and verifying the design.
In engineering verification test phase, Test driver is downloaded in SOC internal code memory banks by debugging interface, then to SOC
True external signal excitation is loaded, runs SOC systems to carry out test checking.
However, in SOC design Qualify Phase, can not complete detection during front end by current method of testing
The feature of SOC systems, whole debugging testing process can not be authenticated to, SOC is able to validate only and applies sexual function substantially.Secondly,
Verify in external testing debugging process, it is sometimes desirable in design front-end phase increase FPGA（Field Programmable Gate
Array, field programmable gate array）Plate level verification and outside debugging component, so as to add the cost of great number.Meanwhile at present
Method of testing, when detecting SOC full addresses space read-write capability, lack flexibility, software need continuous modification-compiling-plus
Carry, while different registers test case is more, utilization rate is not high on time and resource.
In addition, external signal test and debugging function after real SOC product designs output using extremely wide, surveyed in scanning
Numerous aspects such as examination, solidification code, debugging upgrading and system detectio are used.Process is designed and developed what low cost required
In, FPGA plate level verification processes are had no, after design is realized, go to test such function using real wafer or print,
Considerably increase risk.Once the function realizes and gone wrong that product design will return to front-end phase, greatly waste survey
Try time and test resource, delay product cycle, in some instances it may even be possible to lose the market opportunity.
The content of the invention
It is contemplated that at least solves one of above-mentioned technical problem.
Therefore, it is an object of the present invention to propose a kind of chip self-testing method, this method can be fast and effeciently right
SOC global address spaces verify, and simple to operate, easy realization, this method also have higher portability and connectivity, separately
Outside, resource can be saved in this method implementation process, reduces testing cost.
It is another object of the present invention to provide a kind of chip self-measuring system.
To achieve these goals, the embodiment of first aspect present invention proposes a kind of chip self-testing method, the side
Method is performed by self-measuring system, the described method comprises the following steps：Self-measuring system generates serial debug command sequential respectively
Macrodefinition collection and testing and control scheme macrodefinition collection；The self-measuring system obtains the front end logic information of chip；Described test oneself be
System generates test vector text according to the front end logic information, the sequential macrodefinition collection and testing and control scheme macrodefinition collection
Part；And the self-measuring system is write the test vector file to chip to be measured by test machine, and receive the test
The test result of machine feedback.
Chip self-testing method according to embodiments of the present invention, it can be realized in system-on-chip designs front end to serial debugging flow
Test, fundamentally ensure that SOC（On-chip system）Debug the correctness of test function；In addition, this method is outer without increase
Parts, so as to reduce testing cost；This method can fast and effectively verify that operation is simple for SOC global address spaces
Single and easily realization；Meanwhile this method can arrive the production test stage through whole SOC design exploitation is applied to, therefore it is penetrated
Property is higher.
The embodiment of second aspect of the present invention additionally provides a kind of chip self-measuring system, it is characterised in that including：Test oneself mould
Block, the module of testing oneself generate serial debug command sequential macrodefinition collection and testing and control scheme macrodefinition collection respectively；Obtain mould
Block, the acquisition module are used for the front end logic information for obtaining chip；Test vector generation module, the test vector generation mould
Block is used to generate test vector according to the front end logic information, the sequential macrodefinition collection and testing and control scheme macrodefinition collection
File；And writing module, said write module are used to write the test vector file to chip to be measured by test machine,
And receive the test result of the test machine feedback.
Chip self-measuring system according to embodiments of the present invention, it can be realized in system-on-chip designs front end to serial debugging flow
Test, fundamentally ensure that SOC（On-chip system）Debug the correctness of test function；In addition, the system is outer without increase
Parts, so as to reduce testing cost；The system can be fast and effectively for the checking of SOC global address spaces, system knot
Structure is simple and easy to operate；Meanwhile the system can arrive the production test stage through whole SOC design exploitation is applied to, therefore
Its connectivity is higher.
The additional aspect and advantage of the present invention will be set forth in part in the description, and will partly become from the following description
Obtain substantially, or recognized by the practice of the present invention.
Brief description of the drawings
The above-mentioned and/or additional aspect and advantage of the present invention will become in the description from combination accompanying drawings below to embodiment
Substantially and it is readily appreciated that, wherein：
Fig. 1 is the flow chart according to the chip self-testing method of one embodiment of the invention；
Fig. 2 is the system architecture of the self-measuring system according to the chip self-testing method of one embodiment of the invention and platform of testing oneself
Schematic diagram；
Fig. 3 is the design and realization principle schematic diagram according to the chip self-testing method of one embodiment of the invention；
Fig. 4 is to generate schematic diagram according to the test vector file of the chip self-testing method of one embodiment of the invention；
Fig. 5 is the flow chart according to the chip self-testing method of another embodiment of the present invention；With
Fig. 6 is the structural representation according to the chip self-measuring system of one embodiment of the invention.
Embodiment
Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, wherein from beginning to end
Same or similar label represents same or similar element or the element with same or like function.Below with reference to attached
The embodiment of figure description is exemplary, is only used for explaining the present invention, and is not considered as limiting the invention.
In the description of the invention, it is to be understood that term " " center ", " longitudinal direction ", " transverse direction ", " on ", " under ",
The orientation or position relationship of the instruction such as "front", "rear", "left", "right", " vertical ", " level ", " top ", " bottom ", " interior ", " outer " are
Based on orientation shown in the drawings or position relationship, it is for only for ease of the description present invention and simplifies description, rather than instruction or dark
Show that the device of meaning or element there must be specific orientation, with specific azimuth configuration and operation, thus it is it is not intended that right
The limitation of the present invention.In addition, term " first ", " second " are only used for describing purpose, and it is not intended that instruction or hint are relative
Importance.
In the description of the invention, it is necessary to illustrate, unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected, or be integrally connected；Can
To be mechanical connection or electrical connection；Can be joined directly together, can also be indirectly connected by intermediary, Ke Yishi
The connection of two element internals.For the ordinary skill in the art, with concrete condition above-mentioned term can be understood at this
Concrete meaning in invention.
Chip self-testing method according to embodiments of the present invention and system are described below in conjunction with accompanying drawing.
Fig. 1 is the flow chart according to the chip self-testing method of one embodiment of the invention.As shown in figure 1, according to the present invention
The chip self-testing method of one embodiment, wherein, this method is performed by self-measuring system, and this method comprises the following steps：
Step S101, self-measuring system generate serial debug command sequential macrodefinition collection and testing and control scheme macrodefinition respectively
Collection.
As a specific example, as shown in figure 3, when the chip self-testing method relates generally to SW orders when realizing and testing oneself
Sequence macrodefinition collection, SOC testing and control scheme macrodefinitions collection, order and data combination logic, test vector reorder logic, test
The functional modules such as vector file generation logic, vectorial transmission control logic and test clock control logic.In above-mentioned steps S101
In, it is mainly concerned with SW command timing macrodefinition collection and SOC testing and control scheme macrodefinition two functional modules of collection.
Specifically, SW（Serial Wire, string line）Command timing macrodefinition collection is that serial debug command sequential is grand fixed
Justice collection.It is included in SW and serially debugs the sequential carried out in agreement required for test and debugging.Specifically, each sequential is integrated
And macrodefinition, called for logic of testing oneself.Such as：SW reset commands are that SWDIO inputted for 50 cycles 1, then macrodefinition define
RESET_ORDER11111…11111（50 1）；SW reads IDCODE orders：define READ_IDCODE1010_0101.With
The SW timing commands needed to use are carried out macrodefinition by this, to treat that self-measuring system calls.After the completion of set definition, without 2
Secondary modification, other SW debugging tests based on ARM microprocessor can be matched completely.
SOC testing and control scheme macrodefinition collection is testing and control scheme macrodefinition collection.Specifically, different SOC are based on not
Possess different testing and control scheme macrodefinitions with design architecture.The set includes address and the address sky of required test SOC
Between, test data and self-measuring system control configuration parameter.Such as：Test address 1 is define A10000_1010；Test address
2 be define A21001_1000；The test data that test address 1 needs is define AD11101_0001；Test address 2
The test data needed is define AD20011_0100；SWCLK FREQUENCY CONTROLs are define FSWCLK2（2M）；A2 addresses
Testing sequence priority is define A2_PRI3；Output vector file enters to be made as define CODEBOH2（Binary system）.From
And with this by survey SOC testing and control scheme be all integrated into the macrodefinition concentrate, with treat self-measuring system call.When
When changing test content, it is only necessary to change or increase and decrease and test macrodefinition in the set accordingly to realize the change of testing scheme, from
And there is very high portability, in addition, being participated in change procedure without software, have easy to operate, complexity is low and reliability
The advantages of high.
Step S102, self-measuring system obtain the front end logic information of chip.
Step S103, self-measuring system is according to front end logic information, sequential macrodefinition collection and testing and control scheme macrodefinition collection
Generate test vector file.Specifically, first, self-measuring system is according to sequential macrodefinition collection and testing and control scheme macrodefinition collection
Vector row group is generated, then the vector in the vector row group is reordered according to front end logic information to generate test
Vector file.Wherein, in one embodiment of the invention, the address of testing and control scheme macrodefinition collection including chip to be measured and
Address space, test data and self-measuring system control configuration parameter.
As a specific example, with reference to shown in Fig. 3, i.e. order calls SW command timings grand with data combination logic module
Definition collection and SOC testing and control scheme macrodefinition collection, and provided according to testing scheme, automatically by test command, test address, survey
Control sequence specified in examination data and testing scheme is combined into one group of continuous binary vector（As shown in Fig. 5 flows）.Specifically
For, such as shown in Fig. 4, A2 addresses in vector 1 are write into AD2 data in vector 2, then call the TAR of A2 to SW components to deposit
Device order（Vector 1）, AD2 is called to the DRW registers of SW components（Middle vectorial 2）, and by bind command by vector 1 and vector
2 integrate, so as to form one group of test vector.Further, as shown in Figure 3 and Figure 5, test vector reorder logic module according to
According to test prioritization macrodefinition specified in SOC testing and controls scheme macrodefinition collection and address space macrodefinition collection（For example,
PRI）, arranging order generates with data combination logic from high to low test vector group completes the integration of whole SOC test vectors
And export.
Finally, test vector file generation logic module generates the test vector after integration according to CODEBOH corresponding
Binary file simultaneously exports.
Step S104, self-measuring system is write test vector file to chip to be measured by test machine, and receives test machine
The test result of feedback.Wherein, in one embodiment of the invention, chip to be measured is but is not limited to on-chip system SOC.
As a specific example, with reference to shown in Fig. 3, vectorial transmission control logic module is that SW interfaces transmit control core, is used for
Provided to SOC input tests vector, and according to SW sequential, control SWCLK clock inputs, and SW components return in processing SOC
Response（Such as：OK responses, WAIT responses, ERROR responses）, and different reply process is carried out, such as：OK responses then control
Vector transmission and access continue to carry out according to current normal condition；Then the current vector transmission of control is suspended for WAIT responses, and
The vector for the WAIT responses currently fed back is resend, or considers to interrupt the transmission of current vector；ERROR responses need to pass
Defeated control logic module confirms the correctness of SW agreements and the correctness of target response, and read IDCODE registers or
Carry out reset command.Vectorial transmission control logic module is additionally operable to the timing requirements for making transmission meet SW agreements and ensures transmission
The input/output state of correctness and the two-way IO of control.Wherein, in figure 3, test clock control logic module be used for pair
SWCLK frequencies are configured, and control of the received vector transmission control logic module to Clock gating, with accurate controlling transmission
Sequential.
In summary, in the self-testing method implementation process, after self-measuring system startup optimization, self-measuring system is by automatic root
Tested according to testing scheme and flow as defined in SOC testing and control scheme macrodefinition collection, most test result statistics is fed back at last.
Chip self-testing method according to embodiments of the present invention, it can be realized in system-on-chip designs front end to serial debugging flow
Test, fundamentally ensure that SOC（On-chip system）Debug the correctness of test function；In addition, this method is outer without increase
Parts, so as to reduce testing cost；This method can fast and effectively verify that operation is simple for SOC global address spaces
Single and easily realization；In addition, this method can arrive the production test stage through whole SOC design exploitation is applied to, therefore it is penetrated
Property is higher.
Fig. 2 is the system architecture of the self-measuring system according to the chip self-testing method of one embodiment of the invention and platform of testing oneself
Schematic diagram.
As shown in Fig. 2 in the self-testing method implementation process, self-measuring system needs to survey by SWCLK and SWDIO connections
The SOC logics of card are tested, or the test vector file of self-measuring system generation is also passed through into SWCLK by production test board
And SWDIO is inputted to the SOC that need to be tested；Receive caused result after validation test simultaneously.
Specifically, the realization principle of the chip self-testing method is：By SW debug timing command used in agreement by
One extraction, and by the formal definition of macrodefinition, and be integrated into serial debug command sequential macrodefinition and concentrate with to be called；And unite
Address space, test data and the corresponding testing scheme of the current designed SOC institutes detection in need of meter, according to testing need
Ask classification to carry out macrodefinition, and be integrated into SOC testing and control schemes macrodefinition and concentrate with to be called；And design a macrodefinition and adjust
With system, its interface meets SW string line debugging interface requirements, by the test address needed in the file of surveyed item, data and
Scheme row group forms continuous test vector after the order macrodefinition that serial debug command sequential macrodefinition is concentrated is integrated,
Test checking is carried out automatically by SW string lines.
In addition, when needing to change test item or test condition, it is only necessary to increase item to be measured newly or changed in item file to be measured,
After the completion of change, self-measuring system automatically forms follow-on test vector, test checking is carried out automatically by SW string lines, so as to have
It is portable.
Further, the test vector generated by system, the binary file of needs can be preserved into, available for production test
Test of the machine to SOC, therefore there is higher connectivity.
It should be noted that being automatically performed in the test process by hardware, no software participates in, therefore, the test side
Method also has the advantages of easy to operate, complexity is low, and development cost is low and reliability is high.
Fig. 5 is the flow chart according to the chip self-testing method of another embodiment of the present invention.As shown in figure 5, according to this hair
The chip self-testing method of another bright embodiment, comprises the following steps：
Step S501, system are tested oneself.That is chip is tested oneself beginning, and self-measuring system is started working.
Step S502, call SW orders and test address data.Specifically, SW is debugged into sequential used in agreement to order
Order is extracted one by one, and by the formal definition of macrodefinition, and be integrated into serial debug command sequential macrodefinition and concentrate with to be called；
And count current designed SOC detection in need address space, test data and corresponding testing scheme, according to survey
Try demand classification and carry out macrodefinition, and be integrated into SOC testing and control schemes macrodefinition and concentrate with to be called.
Step S503, order are combined with address and data.
Step S504, produce vector.Specifically, call SW command timing macrodefinition collection and SOC testing and control schemes grand
Definition collection, and provided according to testing scheme, automatically by specified in test command, test address, test data and testing scheme
Control sequence is combined into one group of continuous binary vector.
Step S505, all test vectors are sorted according to initial order configuration.Specifically, according to SOC testing and controls
Test prioritization macrodefinition specified in scheme macrodefinition collection and address space macrodefinition collection, from high to low arranging order and test
Vector Groups, complete integration and the output of whole SOC test vectors.
Step S506, the test vector group that generation order determines.I.e. in above-mentioned steps S506, the test vector group of output
For the test vector group sequentially determined.
Step S507, by transmission control input to SOC.Specifically, transmission control is vectorial to SOC input tests, and according to
Provided according to SW sequential, control SWCLK clock inputs, and the response that SW components return in processing SOC（Such as：OK responses, WAIT
Response, ERROR responses）, and carry out different reply process.Such as：OK response then dominant vector transmission and access continue according to
Current normal condition is carried out；Then the current vector transmission of control is suspended for WAIT responses, and resends what is currently fed back
The vector of WAIT responses, or consider to interrupt the transmission of current vector；ERROR responses need transmission control logic module to confirm SW
The correctness of agreement and the correctness of target response, and carry out reading IDCODE registers or carry out reset command.
Step S508, check evaluation test result.Receive and check the test result of test machine feedback.
Step S509, judge whether to need to change testing requirementIf it is, performing step S510, step is otherwise performed
S512。
Step S510, modification test address sum is according to this and test item other demands.I.e. in above-mentioned steps S509, if
Judgement needs to change testing requirement, then changes test address sum according to this and test item other demands.Specifically, when need more
When changing test item or test condition, it is only necessary to increase item to be measured newly or changed in item file to be measured, after the completion of change, self-measuring system is certainly
It is dynamic to form follow-on test vector, test checking is carried out automatically by SW string lines, so as to portability.
Step S511, modification preserve test item macrodefinition file, and return and perform step S502.Specifically, test oneself and be
Unite the test vector of generation, the binary files of needs can be preserved into, available for test of the production test machine to SOC, therefore
With higher connectivity.
Step S512, terminate.I.e. in above-mentioned steps S509, when testing requirement need not be changed, terminate chip and test oneself
Flow.
Step S513, configured according to file system and produce test vector file.In other words, i.e., after step s 505, enter
Test vector after integration is generated corresponding binary file according to CODEBOH and exported by one step.
Step S514, obtained test vector file is exported.
In summary, and with reference to Fig. 5 can obtain, the chip self-testing method of the embodiment of the present invention, on the one hand, can realize not
Increase external module（Such as FPGA）In the case of, in SOC design front end, SOC tests are carried out to debugging logic by SW string lines
The checking of debugging process.On the other hand, when testing the read-write of SOC full addresses space, tested independent of traditional software-driven,
By the checking systematization for SOC, by macrodefinition test file, with reference to SW agreements, simple and quick detect.
In addition, when the SOC design test that self-measuring system is serially debugged for another based on ARM, it is only necessary to change SOC surveys
Try control program macrodefinition collection, it is ensured that it meets the test to the SOC, without changing self-measuring system, without test software
Driving, therefore, easy to operate and efficiency is higher.
Chip self-testing method according to embodiments of the present invention, it can be realized in system-on-chip designs front end to serial debugging flow
Test, fundamentally ensure that SOC（On-chip system）Debug the correctness of test function；In addition, this method is outer without increase
Parts, so as to reduce testing cost；This method can fast and effectively verify that operation is simple for SOC global address spaces
Single and easily realization；In addition, the test checking for the different SOC designs based on string line, it is only necessary to it is grand fixed to change control program
Justice collection, therefore, have higher test portable；Meanwhile this method can arrive life through whole SOC design exploitation is applied to
Test phase is produced, therefore its connectivity is higher.
The invention also provides a kind of chip self-measuring system.Core according to embodiments of the present invention is described below in conjunction with accompanying drawing 6
Piece self-measuring system.
Fig. 6 is the structural representation according to the chip self-measuring system of one embodiment of the invention.As shown in fig. 6, according to this
The chip self-measuring system 600 of invention one embodiment, including：Module of testing oneself 610, acquisition module 620, test vector generation module
630 and writing module 640.
Specifically, module of testing oneself 610 generates serial debug command sequential macrodefinition collection respectively and testing and control scheme is grand
Definition collection.Wherein, in one embodiment of the invention, testing and control scheme macrodefinition collection includes the address and ground of chip to be measured
Location space, test data and self-measuring system control configuration parameter.
Acquisition module 620 is used for the front end logic information for obtaining chip.
Test vector generation module 630 is used for grand according to front end logic information, sequential macrodefinition collection and testing and control scheme
Definition collection generation test vector file.Specifically, test vector generation module 630 is used for according to sequential macrodefinition collection and test
Control program macrodefinition collection generates vector row group, and enters rearrangement to the vector in vector row group according to front end logic information
Sequence is to generate test vector file.
Writing module 640 is used to write test vector file to chip to be measured by test machine, and it is anti-to receive test machine
The test result of feedback.Wherein, in one embodiment of the invention, chip to be measured is but is not limited to on-chip system SOC.
Chip self-measuring system according to embodiments of the present invention, it can be realized in system-on-chip designs front end to serial debugging flow
Test, fundamentally ensure that SOC（On-chip system）Debug the correctness of test function；In addition, the system is outer without increase
Parts, so as to reduce testing cost；The system can be fast and effectively for the checking of SOC global address spaces, system knot
Structure is simple and easy to operate；In addition, the test checking for the different SOC designs based on string line, it is only necessary to change controlling party
Case macrodefinition collection, therefore, have higher test portable；Meanwhile the system can be opened through whole SOC design is applied to
The production test stage is dealt into, therefore its connectivity is higher.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or the spy for combining the embodiment or example description
Point is contained at least one embodiment or example of the present invention.In this manual, to the schematic representation of above-mentioned term not
Necessarily refer to identical embodiment or example.Moreover, specific features, structure, material or the feature of description can be any
One or more embodiments or example in combine in an appropriate manner.
Although an embodiment of the present invention has been shown and described, it will be understood by those skilled in the art that：Not
In the case of departing from the principle and objective of the present invention a variety of change, modification, replacement and modification can be carried out to these embodiments, this
The scope of invention is by claim and its equivalent limits.
Claims (6)
1. a kind of chip self-testing method, methods described are performed by self-measuring system, it is characterised in that are comprised the following steps：
The self-measuring system generates serial debug command sequential macrodefinition collection and testing and control scheme macrodefinition collection respectively, wherein,
The testing and control scheme macrodefinition collection includes the address and address space of chip to be measured, the control of test data and self-measuring system is matched somebody with somebody
Put parameter；
The self-measuring system obtains the front end logic information of chip；
The self-measuring system is given birth to according to the front end logic information, the sequential macrodefinition collection and testing and control scheme macrodefinition collection
Into test vector file；And
The self-measuring system is write the test vector file to chip to be measured by test machine, and it is anti-to receive the test machine
The test result of feedback.
2. chip self-testing method as claimed in claim 1, it is characterised in that the self-measuring system is believed according to the front end logic
Breath, the sequential macrodefinition collection and testing and control scheme macrodefinition collection generation test vector file further comprise：
The self-measuring system generates vector row group according to the sequential macrodefinition collection and testing and control scheme macrodefinition collection；And
The vector in the vector row group is reordered to generate the test vector according to the front end logic information
File.
3. chip self-testing method as claimed in claim 1, it is characterised in that the chip to be measured is on-chip system SOC.
A kind of 4. chip self-measuring system, it is characterised in that including：
Test oneself module, the module of testing oneself generates serial debug command sequential macrodefinition collection and testing and control scheme macrodefinition respectively
Collection, wherein, the address of the testing and control scheme macrodefinition collection including chip to be measured and address space, test data and test oneself and be
System control configuration parameter；
Acquisition module, the acquisition module are used for the front end logic information for obtaining chip；
Test vector generation module, the test vector generation module are used for grand according to the front end logic information, the sequential
Definition collection and testing and control scheme macrodefinition collection generation test vector file；And
Writing module, said write module is used to write the test vector file to chip to be measured by test machine, and connects
Receive the test result of the test machine feedback.
5. chip self-measuring system as claimed in claim 4, it is characterised in that the test vector generation module is used for according to institute
Sequential macrodefinition collection and testing and control scheme macrodefinition collection generation vector row group are stated, and according to the front end logic information to institute
The vector in vector row group is stated to be reordered to generate the test vector file.
6. chip self-measuring system as claimed in claim 4, it is characterised in that the chip to be measured is on-chip system SOC.
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| CN106294144B (en) * | 2016-08-04 | 2019-01-08 | 芯原微电子(上海)有限公司 | Generation method, system and the server of the test vector of serial communication protocol |
| CN112053732A (en) * | 2020-05-20 | 2020-12-08 | 深圳市宏旺微电子有限公司 | DRAM (dynamic random Access memory) fault detection method, device and system based on March algorithm optimization |
| CN111782453A (en) * | 2020-08-04 | 2020-10-16 | 西安太乙电子有限公司 | ATE-based SRAM type FPGA online test method |
| CN113466675B (en) * | 2021-05-26 | 2022-06-21 | 中国电子科技集团公司第五十四研究所 | Test vector generation method |
| CN115202947B (en) * | 2022-08-02 | 2023-05-23 | 无锡众星微系统技术有限公司 | Chip test vector generation method based on debug interface |
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| CA2321346A1 (en) * | 2000-09-28 | 2002-03-28 | Stephen K. Sunter | Method, system and program product for testing and/or diagnosing circuits using embedded test controller access data |
| US6728916B2 (en) * | 2001-05-23 | 2004-04-27 | International Business Machines Corporation | Hierarchical built-in self-test for system-on-chip design |
| CN1458592A (en) * | 2002-05-14 | 2003-11-26 | 华为技术有限公司 | Device function automatic detection method based on boundary scanning structure |
| US7380191B2 (en) * | 2005-02-09 | 2008-05-27 | International Business Machines Corporation | ABIST data compression and serialization for memory built-in self test of SRAM with redundancy |
| CN102565685B (en) * | 2010-12-14 | 2014-04-02 | 苏州工业园区谱芯科技有限公司 | Logic built-in self-test system |
| CN102608518A (en) * | 2012-02-29 | 2012-07-25 | 华为技术有限公司 | Chip testing method and device |
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