CN109283451A - A kind of integrated circuit non-defective unit detection system and method - Google Patents
A kind of integrated circuit non-defective unit detection system and method Download PDFInfo
- Publication number
- CN109283451A CN109283451A CN201811087580.7A CN201811087580A CN109283451A CN 109283451 A CN109283451 A CN 109283451A CN 201811087580 A CN201811087580 A CN 201811087580A CN 109283451 A CN109283451 A CN 109283451A
- Authority
- CN
- China
- Prior art keywords
- chip
- instruction
- control device
- measured
- tested
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2894—Aspects of quality control [QC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention belongs to chip testing technology fields, provide a kind of system and method for integrated circuit non-defective unit detection, specifically for realizing the intelligence test of multi-chip.The present invention includes control device, display device, decoder and several chips to be measured；Display device connection controls transposition, for showing testing result；The chip selection signal port of several chips to be measured connects control device by decoder, and the clock interface of each chip to be measured and data transmission interface are correspondingly connected to control device same-interface.The present invention uses the multiplexing technology of chip clock interface and data transmission interface to be measured, matches n io mouthfuls of control device of the decoder realization at the end chip CS to be measured to 2nA chip to be measured is controlled, and the problem of a large amount of I/O ports are needed in multi-chip test is effectively overcome；Optimal inspection process simultaneously, substantially reduces the testing time, effectively improves testing efficiency；That is the multi-chip intelligence test of high efficiency, low cost.
Description
Technical field
The invention belongs to chip testing technology field, it is related to test macro and side that a kind of intelligent and high-efficiency multi-chip lacks channel
Method, specially a kind of system and method for integrated circuit non-defective unit detection.
Technical background
Flash memory is used for computer and electronic equipment, automobile, Internet of Things, unmanned plane, smart home and some other
Equipment, these applications are so that flash most asks higher transmission speed and lower power consumption；The interface of flash is expanded to from SPI
OPI (Octal SPI), by increasing the data transmission channel of serial nor flash, and support single, dual, quad or
Octal I/O interface；Since the Octal SPI IO for being used for transmission data increases to 8 by 2 of SPI, transmission data speed increases
While adding, it is also required to occupy a large amount of I/O port in previous test.
Traditional chip testing is to need manual control, especially survey of the laboratory test stage to the chip of SPI interface
Examination, needs manually to give and instructs；With the development of intelligent control method and technology, move towards rapidly by intelligent control in recent ten years
Various professional domains, applied to the control problem of all kinds of complicated controlled devices, as industrial process control system, robot system,
Modern production manufacture system, traffic control system etc..Intelligent control is that the process of its target is automatically realized by intelligence machine, from
Main ground alternatively executes a kind of machine of task as defined in the mankind with people, so being also required to a kind of to discharge people in testing field
The intelligent test system of power.
DFT technique is to be tested some special constructions after the completion to design in design phase implantation circuit；Pass through
Testability Design structure, such as scan chain are added, BIST (build-in-self-test) etc., internal signal can be exposed to
Circuit external；Such as: BIST measuring technology is widely used in semi-conductor industry, and BIST technology used in memory is included in circuit
Circuit, sequence circuit, mode selection circuit and debugging test circuit occur for middle implantation resolution chart, however BIST is implanted into chip
Middle to occupy additional circuit area, additional pin increases chip cost, it is understood that there may be test blindspot.
ATE (Automatic Test Equipment) is the test request, drawing and reference scheme according to client, is used
MCU, PLC, PC are based on VB, VC development platform, utilize the technologies such as Test Stand&LabVIEW and JTAG/Boundary Scan
It develops, design all kinds of automated test devices；ATE testing cost is high, and to negotiate test item with testing factory, increases and reduces
Test item is extremely inconvenient.
Summary of the invention
The purpose of the present invention is to provide a kind of system and methods of integrated circuit non-defective unit detection, for realizing multi-chip
Intelligence test, and testing efficiency is high, testing cost is low.
To achieve the above object, the technical solution adopted by the present invention are as follows:
A kind of system of integrated circuit non-defective unit detection, including control device, display device, decoder and several cores to be measured
Piece；It is characterized in that, the display device connection controls transposition, for showing testing result；Several chips to be measured
Chip selection signal port connects control device by decoder, and the clock interface of each chip to be measured and data transmission interface are right
Control device same-interface should be connected to.
Further, the control device includes instruction testing module, monitoring module, memory module and data processing mould
Block, wherein the memory module collects for storing instruction and test data, and described instruction sending module is for sending chip selection signal
It is instructed with test, whether the monitoring module completes the judgement and system testing state of Erase instruction for realizing test chip
Monitoring.
A kind of method of integrated circuit non-defective unit detection, includes the following steps；
Instruction sending module sends chip selection signal in step 1. control device, chooses the first chip to be tested；
Step 2. instruction sending module sends READ instruction, and current chip to be tested returns corresponding after receiving and executing instruction
Address date memory module into control device, and by the accounting of " 1 " in data processing module statistics returned data, labeled as just
Beginning yield is simultaneously stored to memory module；
Step 3. instruction sending module sends Program instruction, and current chip to be tested is received and executed instruction, then,
Instruction sending module sends READ instruction, and current chip to be tested returns to appropriate address data to control after receiving and executing instruction
Memory module in device, and by data processing module statistics returned data in " 0 " accounting, labeled as program yield and store to
Memory module；
Step 4. instruction sending module sends Erase instruction, and current chip to be tested is received and executed instruction；
Step 5. instruction sending module sends chip selection signal, chooses next chip to be tested, repeats step 2~4；
Step 6. repeats step 5, until the last one chip to be measured；
Instruction sending module sends chip selection signal in step 7. control device, chooses the first chip to be tested；
Monitoring module judges whether current chip to be tested completes Erase instruction in step 8. control device, if, then into
Row step 9 carries out step 9 after if not, then waiting current chip to be tested to complete Erase instruction；
Step 9. instruction sending module sends READ instruction, and current chip to be tested returns corresponding after receiving and executing instruction
Address date memory module into control device, and by the accounting of " 1 " in data processing module statistics returned data, labeled as wiping
Except yield and store to memory module；
Step 10. instruction sending module sends chip selection signal, chooses next chip to be tested, repeats step 8~9, until
The last one chip to be measured completes detection；
Data processing module is according to chip initial yield to be measured, program yield and erasing yield in step 11. control device
Grade classification is carried out to chip to be measured, and exports result to display device.
It should be understood that the monitoring module is by reading the Erase mark in chip register to be measured in the present invention
Position can determine that whether chip to be measured completes Erase instruction；Described instruction collection includes all instructions that be used to test chip,
Such as: READ, Program, Erase, Suspend, Resume etc.；Data processing module is according to chip to be measured in the control device
Initial yield, program yield and erasing yield carry out grade classification to chip to be measured, and grade classification rule can be according to core to be measured
The practical use of piece carries out practical determine.
In addition, the present invention uses the multiplexing skill of chip clock interface to be measured and data transmission interface from working principle
Art, matches the decoder at the end chip CS to be measured (chip select), and decoder can be realized n io mouthfuls of control device to 2nIt is a
Chip to be measured is controlled, and once provides effective chip selection signal for a chip to be measured, is referred to for being selected chip response to be measured
It enables；Effectively overcome the problem of a large amount of I/O ports are needed in multi-chip test；Very due to chip Erase time for each instruction to be measured
It is long, in detection method of the invention, its of other chips to be measured is carried out based on the time synchronization that chip to be measured executes Erase instruction
He returns the first chip to be measured and judges whether it completes instruction execution after all chips to be measured are performed both by Erase instruction
Erase instruction, and then other instruction testings are carried out, the testing time is substantially reduced, testing efficiency is effectively improved；Also, it is entire
Test process is automatically performed by control device.
To sum up, the invention has the beneficial effects that: a kind of system and method for integrated circuit non-defective unit detection is provided, for real
The intelligence test of existing multi-chip, testing efficiency is high, testing cost is low, and effectively overcomes and need a large amount of I/O ports in multi-chip test
The problem of.
Detailed description of the invention
Fig. 1 is the system block diagram of integrated circuit non-defective unit detection system of the present invention (for Octal SPI nor flash).
Fig. 2 is the flow chart of integrated circuit non-defective unit detection method of the present invention.
Fig. 3 is that Octal SPI STR mode gives an order transmission mode schematic diagram in the embodiment of the present invention.
Specific embodiment
The following further describes the present invention with reference to the drawings.
The present embodiment provides a kind of integrated circuit non-defective unit detection systems, by taking Octal SPI nor flash as an example, system
Block diagram is as shown in Figure 1, include control device, display device, decoder and several chips to be measured；Display device connection control turns
It sets, for showing testing result；The port CS of several chips to be measured connects control device by decoder, and several are to be measured
The clock interface sclk and data transmission interface io0~io7 of chip are all made of multiplexed port, i.e., the clock of each chip to be measured connects
Mouth sclk is both connected to the same interface of control device, and data transmission interface io0~io7 of each chip to be measured respectively corresponds company
It is connected to the same interface of control device, as shown in Figure 1.
It is illustrated in figure 2 said integrated circuit non-defective unit detection system flow diagram, is included the following steps；
Instruction sending module sends chip selection signal in step 1. control device, chooses the first chip to be tested；
Step 2. instruction sending module sends READ instruction, and current chip to be tested returns corresponding after receiving and executing instruction
Address date memory module into control device, and by the accounting of " 1 " in data processing module statistics returned data, labeled as just
Beginning yield is simultaneously stored to memory module；
Step 3. instruction sending module sends Program instruction, and current chip to be tested is received and executed instruction, then,
Instruction sending module sends READ instruction, and current chip to be tested returns to appropriate address data to control after receiving and executing instruction
Memory module in device, and by data processing module statistics returned data in " 0 " accounting, labeled as program yield and store to
Memory module；
Step 4. instruction sending module sends Erase instruction, and current chip to be tested is received and executed instruction；
Step 5. instruction sending module sends chip selection signal, chooses next chip to be tested, repeats step 2~4；
Step 6. repeats step 5, until the last one chip to be measured；
Instruction sending module sends chip selection signal in step 7. control device, chooses the first chip to be tested；
Monitoring module judges whether current chip to be tested completes Erase instruction in step 8. control device, if, then into
Row step 9 carries out step 9 after if not, then waiting current chip to be tested to complete Erase instruction；
Step 9. instruction sending module sends READ instruction, and current chip to be tested returns corresponding after receiving and executing instruction
Address date memory module into control device, and by the accounting of " 1 " in data processing module statistics returned data, labeled as wiping
Except yield and store to memory module；
Step 10. instruction sending module sends chip selection signal, chooses next chip to be tested, repeats step 8~9, until
The last one chip to be measured completes detection；
Data processing module is according to chip initial yield to be measured, program yield and erasing yield in step 11. control device
Grade classification is carried out to chip to be measured, and exports result to display device.
It is illustrated in figure 3 Octal SPI STR mode to give an order transmission mode schematic diagram, the instruction of Octal SPI is
2Byte, so needing two clocks, each clock has sio0~sio7 to transmit 1Byte；Next by reference according to instruction property
Or data are directly passed, or do not pass data.As (write enable writes enabled instruction to WREN, used in the finger for writing property to chip hair
Before order, such as Program and Erase) there is no need to connect extra data and address, the digit of address also by the capacity that designs Lai
Fixed, such as the opi flash chip of 64Mbit capacity, when transmitting Read instruction, address is 23 significance bits；So shared by address
Time span according to circumstances adjust；tCLSHFor effective retention time of CS signal, tSHCHFor relative to SCLK, the guarantor of CS signal
The time is held, for the two parameters depending on each nor flash chip performance, chip the two parameters having at present are all at least
3ns。
In addition, display equipment can be all kinds of numeral method devices in the present embodiment；Decoder can according to need use
Multiple decoder parallel connections connect multiple chips；Controlling equipment is built by hardware and software, and hardware components include control
Chip, storage chip, wherein control chip can be CPU, DSP, FPGA, according to control the accessible highest frequency of chip with
And the performance of plate grade wiring, SCLK clock signal can be made to may be up to gigahertz；All kinds of storage chips can be used in storage section.
To sum up, the present invention provides a kind of system and method for integrated circuit non-defective unit detection, for realizing the intelligence of multi-chip
Test, testing efficiency is high, testing cost is low, and effectively overcomes the problem of a large amount of I/O ports are needed in multi-chip test；The present invention
It is equally applicable to: the chip of SPI system class, SRAM, DDR, the test of the chips such as radio frequency chip.
The above description is merely a specific embodiment, any feature disclosed in this specification, except non-specifically
Narration, can be replaced by other alternative features that are equivalent or have similar purpose；Disclosed all features or all sides
Method or in the process the step of, other than mutually exclusive feature and/or step, can be combined in any way.
Claims (3)
1. a kind of integrated circuit non-defective unit detection system, including control device, display device, decoder and several chips to be measured；
It is characterized in that, the display device connection controls transposition, for showing testing result；The piece of several chips to be measured selects
Signal port connects control device, and the corresponding company of the clock interface of each chip to be measured and data transmission interface by decoder
It is connected to control device same-interface.
2. by integrated circuit non-defective unit detection system described in claim 1, which is characterized in that the control device includes instruction testing
Module, monitoring module, memory module and data processing module, wherein the memory module collects for storing instruction and test number
According to described instruction sending module is for realizing test chip for sending chip selection signal and test instruction, the monitoring module
The no judgement for completing Erase instruction and system testing condition monitoring.
3. a kind of integrated circuit non-defective unit detection method, which is characterized in that include the following steps；
Instruction sending module sends chip selection signal in step 1. control device, chooses the first chip to be tested；
Step 2. instruction sending module sends READ instruction, and current chip to be tested receives and returns to appropriate address after executing instruction
Data memory module into control device, and by the accounting of " 1 " in data processing module statistics returned data, labeled as initial good
Rate is simultaneously stored to memory module；
Step 3. instruction sending module sends Program instruction, and current chip to be tested is received and executed instruction, then, instruction
Sending module sends READ instruction, and current chip to be tested returns to appropriate address data to control device after receiving and executing instruction
Middle memory module, and by the accounting of " 0 " in data processing module statistics returned data, labeled as program yield and store to storage
Module；
Step 4. instruction sending module sends Erase instruction, and current chip to be tested is received and executed instruction；
Step 5. instruction sending module sends chip selection signal, chooses next chip to be tested, repeats step 2~4；
Step 6. repeats step 5, until the last one chip to be measured；
Instruction sending module sends chip selection signal in step 7. control device, chooses the first chip to be tested；
Monitoring module judges whether current chip to be tested completes Erase instruction in step 8. control device, if, then walked
Rapid 9, step 9 is carried out after if not, then waiting current chip to be tested to complete Erase instruction；
Step 9. instruction sending module sends READ instruction, and current chip to be tested receives and returns to appropriate address after executing instruction
Data memory module into control device, and by the accounting of " 1 " in data processing module statistics returned data, it is good labeled as wiping
Rate is simultaneously stored to memory module；
Step 10. instruction sending module sends chip selection signal, chooses next chip to be tested, repeats step 8~9, until last
One chip to be measured completes detection；
Data processing module is treated according to chip initial yield to be measured, program yield and erasing yield in step 11. control device
It surveys chip and carries out grade classification, and export result to display device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811087580.7A CN109283451B (en) | 2018-09-18 | 2018-09-18 | Integrated circuit good product detection system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811087580.7A CN109283451B (en) | 2018-09-18 | 2018-09-18 | Integrated circuit good product detection system and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109283451A true CN109283451A (en) | 2019-01-29 |
| CN109283451B CN109283451B (en) | 2020-12-29 |
Family
ID=65181106
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811087580.7A Active CN109283451B (en) | 2018-09-18 | 2018-09-18 | Integrated circuit good product detection system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109283451B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112505520A (en) * | 2019-08-26 | 2021-03-16 | 比亚迪半导体股份有限公司 | Chip testing method, device and system |
| CN117686889A (en) * | 2024-01-25 | 2024-03-12 | 杭州广立微电子股份有限公司 | Addressable parallel test circuit, method, chip and system |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070168795A1 (en) * | 2005-04-19 | 2007-07-19 | Chris Martin | On-chip sampling circuit and method |
| CN101158708A (en) * | 2007-10-23 | 2008-04-09 | 无锡汉柏信息技术有限公司 | Multiple chips automatic test method based on programmable logic device |
| CN104422865A (en) * | 2013-08-22 | 2015-03-18 | 上海海尔集成电路有限公司 | Wafer-level one time programmable (OTP) chip test method and device |
| CN104751875A (en) * | 2013-12-25 | 2015-07-01 | 上海华虹宏力半导体制造有限公司 | Failure bitmap analysis method applied to NVM (Non-Volatile Memory) chip |
| CN106526454A (en) * | 2016-11-24 | 2017-03-22 | 上海精密计量测试研究所 | ATE-based method for testing FPGA configuration chip |
| CN108226751A (en) * | 2017-12-14 | 2018-06-29 | 芯海科技（深圳）股份有限公司 | A kind of multiprocessor collaboration chip performance assessment system and method |
-
2018
- 2018-09-18 CN CN201811087580.7A patent/CN109283451B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070168795A1 (en) * | 2005-04-19 | 2007-07-19 | Chris Martin | On-chip sampling circuit and method |
| CN101158708A (en) * | 2007-10-23 | 2008-04-09 | 无锡汉柏信息技术有限公司 | Multiple chips automatic test method based on programmable logic device |
| CN104422865A (en) * | 2013-08-22 | 2015-03-18 | 上海海尔集成电路有限公司 | Wafer-level one time programmable (OTP) chip test method and device |
| CN104751875A (en) * | 2013-12-25 | 2015-07-01 | 上海华虹宏力半导体制造有限公司 | Failure bitmap analysis method applied to NVM (Non-Volatile Memory) chip |
| CN106526454A (en) * | 2016-11-24 | 2017-03-22 | 上海精密计量测试研究所 | ATE-based method for testing FPGA configuration chip |
| CN108226751A (en) * | 2017-12-14 | 2018-06-29 | 芯海科技（深圳）股份有限公司 | A kind of multiprocessor collaboration chip performance assessment system and method |
Non-Patent Citations (1)
| Title |
|---|
| 唐磊: "基于FPGA的USB、Flash控制器设计", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112505520A (en) * | 2019-08-26 | 2021-03-16 | 比亚迪半导体股份有限公司 | Chip testing method, device and system |
| CN112505520B (en) * | 2019-08-26 | 2023-02-21 | 比亚迪半导体股份有限公司 | Chip testing method, device and system |
| CN117686889A (en) * | 2024-01-25 | 2024-03-12 | 杭州广立微电子股份有限公司 | Addressable parallel test circuit, method, chip and system |
| CN117686889B (en) * | 2024-01-25 | 2024-05-14 | 杭州广立微电子股份有限公司 | Addressable parallel test circuit, method, chip and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109283451B (en) | 2020-12-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105093094B (en) | Electric reliability automatic detection device and detection method on chip | |
| CN105474178B (en) | Verifying and debugging based on programmable interface | |
| US20230400513A1 (en) | Addressable test access port | |
| CN101329385B (en) | Regulation test system and method of on-chip system as well as on-chip system | |
| US7844867B1 (en) | Combined processor access and built in self test in hierarchical memory systems | |
| US6820222B2 (en) | Apparatus and method for processor power measurement in a digital signal processor using trace data and simulation techniques | |
| CN102880536A (en) | JTAG (joint test action group) debug method of multi-core processor | |
| US7451367B2 (en) | Accessing sequential data in microcontrollers | |
| CN108595298A (en) | A kind of chip test system and method | |
| CN113514759B (en) | Multi-core test processor and integrated circuit test system and method | |
| CN109061446A (en) | A kind of test method and system of single-ended port transmission chip | |
| US20130110445A1 (en) | Programmable test instrument | |
| CN114333962A (en) | Flash memory chip testing method, device and system, electronic equipment and storage medium | |
| JP4334463B2 (en) | Semiconductor integrated circuit test apparatus and method | |
| CN107290654A (en) | A kind of fpga logic test structure and method | |
| CN103675641A (en) | Chip fault positioning method, device and system | |
| CN109426594A (en) | A kind of chip debugging apparatus, method and computer readable storage medium | |
| CN109283451A (en) | A kind of integrated circuit non-defective unit detection system and method | |
| CN101545950B (en) | Scan control method and device | |
| CN100492315C (en) | Embedded signal processor simulator | |
| US20120185742A1 (en) | Test access port with address and command capability | |
| US20140380110A1 (en) | Test apparatus and operating method thereof | |
| KR101503555B1 (en) | Error catch ram support using fan-out/fan-in matrix | |
| Wang et al. | A Study on Parallel Test Approach for the Flash Burn-in Experiment in Laboratory | |
| CN117234831B (en) | Chip function test method and system based on multi-core CPU |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |