CN109061446A - A kind of test method and system of single-ended port transmission chip - Google Patents
A kind of test method and system of single-ended port transmission chip Download PDFInfo
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- CN109061446A CN109061446A CN201811177569.XA CN201811177569A CN109061446A CN 109061446 A CN109061446 A CN 109061446A CN 201811177569 A CN201811177569 A CN 201811177569A CN 109061446 A CN109061446 A CN 109061446A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
Abstract
The invention discloses the test methods and system of a kind of single-ended port transmission chip, and wherein method includes: the single port data transmission control tested host and obtain chip；Test configurations are carried out to chip interior module to be measured by single port；The test data of module to be measured is read according to test configurations, and the test data read is sent to test host by single port.The test method and system of a kind of single-ended port transmission chip of the present invention realize multiple modules to be measured while being tested, and test host may be read into the test result and state of each module to be measured, and then the testing time is greatly saved.And only need to realize by single port while multiple modules to be measured are tested, reduce chip I/O pin number, saves the production cost of chip.
Description
Technical field
The present invention relates to chip testing, the more specifically a kind of test method and system of single-ended port transmission chip.
Background technique
In current IC design, Testability Design has been used as a ring important in design cycle, chip
In integrate logic unit for example microprocessor, memory, digital signal processor (Digital Signal Processors,
DSPs) universal all to have self-built test module (BIST), and important analogue units certain to chip interior is needed to test
Etc., the method generallyd use is to set multiple-working mode to chip, is connected to chip by test pin or by JTAG
On IO, tested respectively under each mode.
These above-mentioned reasons not only result in the increase of chip I/O quantity, but also cause when testing single chip, need
The total test vector number wanted becomes increasing, and so as to cause in IC design, testing cost occupies chip cost
Ratio it is increasing.And testing cost and testing time be it is directly proportional, i.e. the single chip testing time is longer, then test at
It is originally higher.
Summary of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of test method of single-ended port transmission chip and
System.
To achieve the above object, the invention adopts the following technical scheme: a kind of test method of single-ended port transmission chip, institute
The method of stating includes:
Test the single port data transmission control that host obtains chip；
Test configurations are carried out to chip interior module to be measured by single port；
The test data of module to be measured is read according to test configurations, and the test data read is sent by single port
Give test host.
Its further technical solution are as follows: the step for carrying out test configurations to chip interior module to be measured by single port
Suddenly, specifically includes the following steps:
Corresponding module register address to be measured is inputted by single port universal serial bus；
Register address is handled；
Control command is write in input；
Data will be controlled according to control command and register address to be written in corresponding module to be measured.
Its further technical solution are as follows: described the step of register address is handled, specifically includes the following steps:
Asynchronous process；
Serioparallel exchange processing is carried out after asynchronous process.
Its further technical solution are as follows: the test data that module to be measured is read according to test configurations, and will read
Test data by single port be sent to test host the step of, specifically includes the following steps:
Carry out the read operation of chip interior bus；
It tests host and discharges single port data transmission control；
Chip obtains single-ended port transmission control；
Read the data in module register to be measured.
A kind of test macro of single-ended port transmission chip the system comprises acquiring unit, configuration unit and is read single
Member；
The acquiring unit obtains the single port data transmission control of chip for testing host；
The configuration unit, for carrying out test configurations to chip interior module to be measured by single port；
The reading unit, for reading the test data of module to be measured, and the test that will be read according to test configurations
Data are sent to test host by single port.
Its further technical solution are as follows: the configuration unit includes input module, processing module, command module and write-in
Module；
The input module, for inputting corresponding module register address to be measured by single port universal serial bus；
The processing module, for handling register address；
The command module writes control command for inputting；
Corresponding module to be measured is written for that will control data according to control command and register address in the write module
In.
Its further technical solution are as follows: the processing module includes asynchronous submodule and serioparallel exchange submodule；
The asynchronous submodule is used for asynchronous process；
The serioparallel exchange submodule, for carrying out serioparallel exchange processing after asynchronous process.
Its further technical solution are as follows: the reading unit includes read through model, release module, obtains module and read mould
Block；
The read through model, for carrying out chip interior bus read operation；
The release module, for testing host release single port data transmission control；
The acquisition module obtains single-ended port transmission control for chip；
The read module, for reading the data in module register to be measured.
Compared with the prior art, the invention has the advantages that: a kind of test method of single-ended port transmission chip of the present invention and
System carries out test configurations to chip interior module to be measured by single port, and the test number of module to be measured is read according to test configurations
According to, and the test data read is sent to test host by single port.It realizes multiple modules to be measured while being surveyed
Examination, test host may be read into the test result and state of each module to be measured, and then the testing time is greatly saved.And
It only needs to realize by single port while multiple modules to be measured is tested, reduce chip I/O pin number, save
The production cost of chip.
The above description is only an overview of the technical scheme of the present invention, can in order to better understand technical measure
It is implemented in accordance with the contents of the specification, and in order to make above and other objects of the present invention, feature and advantage brighter
Show understandable, special below to lift preferred embodiment, detailed description are as follows.
Detailed description of the invention
Fig. 1 is a kind of flow chart of the test method specific embodiment of single-ended port transmission chip of the present invention；
Fig. 2 is the flow chart of test configurations in a kind of test method specific embodiment of single-ended port transmission chip of the present invention；
Fig. 3 be in a kind of test method specific embodiment of single-ended port transmission chip of the present invention to register address at
The flow chart of reason；
Fig. 4 is the test that module to be measured is read in a kind of test method specific embodiment of single-ended port transmission chip of the present invention
Data Concurrent gives the flow chart of test host；
Fig. 5 is a kind of structure chart of the test macro specific embodiment of single-ended port transmission chip of the present invention；
Fig. 6 is the structure chart of configuration unit in a kind of test macro specific embodiment of single-ended port transmission chip of the present invention；
Fig. 7 is the flow chart of processing module in a kind of test macro specific embodiment of single-ended port transmission chip of the present invention；
Fig. 8 is the flow chart of reading unit in a kind of test macro specific embodiment of single-ended port transmission chip of the present invention；
Fig. 9 is the single-ended port transmission code pattern of the present invention.
Specific embodiment
In order to more fully understand technology contents of the invention, combined with specific embodiments below to technical solution of the present invention into
One step introduction and explanation, but not limited to this.
It should be appreciated that herein, relational terms such as first and second and the like are used merely to an entity/behaviour
Work/object is distinguished with another entity/operation/object, without necessarily requiring or implying these entity/operation/objects
Between there are any actual relationship or orders.
It is also understood that the terms "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion,
So that the process, method, article or the system that include a series of elements not only include those elements, but also including not having
The other element being expressly recited, or further include for this process, method, article or the intrinsic element of system.Do not having
In the case where having more limitations, the element that is limited by sentence "including a ...", it is not excluded that include the element process,
There is also other identical elements in method, article or system.
Picture 1-4, described in 9, the present invention provides a kind of test methods of single-ended port transmission chip, this method comprises:
S10, test host obtain the single port data transmission control of chip；
S20, test configurations are carried out to chip interior module to be measured by single port；
S30, the test data that module to be measured is read according to test configurations, and the test data read is passed through into single port
It is sent to test host.
Specifically, single port, that is, single port, in the present embodiment, the single port of chip is bidirectional linked list port, so-called " double
To ", it refers to can not only be used for input port, but also as output port.Single port one end passes through outside chip pin pio chip,
The other end be then bus marco port, it can be achieved that chip interior logic unit read-write operation.The present invention only needs a bidirectional end
Mouthful, multiple modules to be measured in chip can be tested simultaneously, reduce chip I/O pin and chip testing significantly
Time.The present invention only with 1 chip pin, and in the prior art JTAG configuration pin need 5, as in chip there are four to
It surveys module and all has JTAG, then need 20 pins in total, and 1 pin is only needed using the present invention in total；Such as four to be measured
Module distinguishes the testing time for n, then needs the 4n time in total, and mainly turns bus control logic by string, to multiple logic lists
Member is configured simultaneously, while being tested, then the time it is most short shorten to n, substantially reduce the testing time.
In certain embodiments, step S20 specifically includes the following steps:
S201, corresponding module register address to be measured is inputted by single port universal serial bus；
S202, register address is handled；
Control command is write in S203, input；
S204, it will be controlled in the corresponding module to be measured of data write-in according to control command and register address.
Specifically, corresponding module register address to be measured process is inputted by single port universal serial bus, after completing input,
Continue to write control command with the input of single port serial mode, then be write according to control command and register address by data are controlled
Enter in corresponding module to be measured (before this, to be handled register address information), host has completed module to be measured
Register configuration can then enter self-test procedure after configuration is completed.
In certain embodiments, step S202 specifically includes the following steps:
S2021, asynchronous process；
Serioparallel exchange processing is carried out after S2022, asynchronous process.
Specifically, because chip interior working frequency to be measured is different from external testing host work clock, it is therefore desirable into
Line asynchronous processing, to avoid data-signal error and avoid the metastable generation of chip.Serioparallel exchange is handled
Serial bus data is converted into parallel data, specific conversion regime is: according to the serial data order of setting, when receiving
Register address data are then sent to the storage of read/write address module；When receive write data after, be sent to read-write data module deposit
Storage；When data need to be read, then the data in data module are read, and converts parallel data into serial data output.
In certain embodiments, step S30 specifically includes the following steps:
S301, the read operation of chip interior bus is carried out；
S302, test host discharge single port data transmission control；
S303, chip obtain single-ended port transmission control；
Data in S304, reading module register to be measured.
Specifically, carrying out the read operation of chip interior bus, the control that host has discharged two-way single port is tested at this time,
Chip obtains the control of two-way single-ended port transmission, after having read the data in module register to be measured, by the number of reading
Single port series form, which exports, accordingly gives test host, and test host can read process by this, and it is to be tested to read chip interior
State of the module from survey.
Further, Fig. 9 is single-ended port transmission code pattern, wherein the single port serial transmission that number 401 is read operation is compiled
Code, when original state, single-ended port transmission signal is low level, subsequent using high level as beginning indication signal when transmission starts
Reading control instruction is low level, and subsequent includes 32 register address, and corresponding 32 bit value, as 32 bit registers
The corresponding data in location, finally terminate to transmit with low level.Number 502 is that the single port serial transmission of write operation encodes, initial shape
When state, single port serial transmission signal be low level, transmission start when, using high level as beginning indication signal, after continue control
System instruction is high level, and subsequent includes 32 register address and corresponding 32 bit value of register, finally with low level
Terminate transmission.Number 503 encodes for the data single port serial transmission read after read operation, after carrying out read operation for host, from
Data are read in machine output, and when original state, single port serial transmission signal is low level, when transmission starts, using high level as opening
Beginning indication signal, it is subsequent to follow 32 as numerical value, finally terminate to transmit with low level.
It should be understood that the size of the serial number of each step is not meant that the order of the execution order in above-described embodiment, each process
Execution sequence should be determined by its function and internal logic, the implementation process without coping with the embodiment of the present invention constitutes any limit
It is fixed.
Corresponding to a kind of test method of single-ended port transmission chip described in above-described embodiment, the present invention provides a kind of lists
The test macro of port transmission chip, as shown in figures 5-9, the system include acquiring unit 1, configuration unit 2 and reading unit
3；
Acquiring unit 1 obtains the single port data transmission control of chip for testing host；
Configuration unit 2, for carrying out test configurations to chip interior module to be measured by single port；
Reading unit 3, for reading the test data of module to be measured, and the test data that will be read according to test configurations
Test host is sent to by single port.
Specifically, single port, that is, single port, in the present embodiment, the single port of chip is bidirectional linked list port, so-called " double
To ", it refers to can not only be used for input port, but also as output port.Single port one end passes through outside chip pin pio chip,
The other end be then bus marco port, it can be achieved that chip interior logic unit read-write operation.The present invention only needs a bidirectional end
Mouthful, multiple modules to be measured in chip can be tested simultaneously, reduce chip I/O pin and chip testing significantly
Time.The present invention only with 1 chip pin, and in the prior art JTAG configuration pin need 5, as in chip there are four to
It surveys module and all has JTAG, then need 20 pins in total, and 1 pin is only needed using the present invention in total；Such as four to be measured
Module distinguishes the testing time for n, then needs the 4n time in total, and mainly turns bus control logic by string, to multiple logic lists
Member is configured simultaneously, while being tested, then the time it is most short shorten to n, substantially reduce the testing time.
In certain embodiments, configuration unit 2 includes input module 21, processing module 22, command module 23 and write-in
Module 24；
Input module 21, for inputting corresponding module register address to be measured by single port universal serial bus；
Processing module 22, for handling register address；
Command module 23 writes control command for inputting；
Corresponding module to be measured is written for that will control data according to control command and register address in writing module 24
In.
Specifically, corresponding module register address to be measured process is inputted by single port universal serial bus, after completing input,
Continue to write control command with the input of single port serial mode, then be write according to control command and register address by data are controlled
Enter in corresponding module to be measured (before this, to be handled register address information), host has completed module to be measured
Register configuration can then enter self-test procedure after configuration is completed.
In certain embodiments, processing module 22 includes asynchronous submodule 221 and serioparallel exchange submodule 222；
Asynchronous submodule 221 is used for asynchronous process；
Serioparallel exchange submodule 222, for carrying out serioparallel exchange processing after asynchronous process.
Specifically, because chip interior working frequency to be measured is different from external testing host work clock, it is therefore desirable into
Line asynchronous processing, to avoid data-signal error and avoid the metastable generation of chip.Serioparallel exchange is handled
Serial bus data is converted into parallel data, specific conversion regime is: according to the serial data order of setting, when receiving
Register address data are then sent to the storage of read/write address module；When receive write data after, be sent to read-write data module deposit
Storage；When data need to be read, then the data in data module are read, and converts parallel data into serial data output.
In certain embodiments, reading unit 3 includes read through model 31, release module 32, obtains module 33 and read mould
Block 34；
Read through model 31, for carrying out chip interior bus read operation；
Release module 32, for testing host release single port data transmission control；
Module 33 is obtained, obtains single-ended port transmission control for chip；
Read module 34, for reading the data in module register to be measured.
Specifically, carrying out the read operation of chip interior bus, the control that host has discharged two-way single port is tested at this time,
Chip obtains the control of two-way single-ended port transmission, after having read the data in module register to be measured, by the number of reading
Single port series form, which exports, accordingly gives test host, and test host can read process by this, and it is to be tested to read chip interior
State of the module from survey.
Further, Fig. 9 is single-ended port transmission code pattern, wherein the single port serial transmission that number 401 is read operation is compiled
Code, when original state, single-ended port transmission signal is low level, subsequent using high level as beginning indication signal when transmission starts
Reading control instruction is low level, and subsequent includes 32 register address, and corresponding 32 bit value, as 32 bit registers
The corresponding data in location, finally terminate to transmit with low level.Number 502 is that the single port serial transmission of write operation encodes, initial shape
When state, single port serial transmission signal be low level, transmission start when, using high level as beginning indication signal, after continue control
System instruction is high level, and subsequent includes 32 register address and corresponding 32 bit value of register, finally with low level
Terminate transmission.Number 503 encodes for the data single port serial transmission read after read operation, after carrying out read operation for host, from
Data are read in machine output, and when original state, single port serial transmission signal is low level, when transmission starts, using high level as opening
Beginning indication signal, it is subsequent to follow 32 as numerical value, finally terminate to transmit with low level.
It is apparent to those skilled in the art that for convenience of description and succinctly, only with above-mentioned each function
Can unit, module division progress for example, in practical application, can according to need and by above-mentioned function distribution by different
Functional unit, module are completed, i.e., the internal structure of the system is divided into different functional unit or module, more than completing
The all or part of function of description.Each functional unit in embodiment, module can integrate in one processing unit, can also
To be that each unit physically exists alone, can also be integrated in one unit with two or more units, it is above-mentioned integrated
Unit both can take the form of hardware realization, can also realize in the form of software functional units.In addition, each function list
Member, the specific name of module are also only for convenience of distinguishing each other, the protection scope being not intended to limit this application.Above system
The specific work process of middle unit, module, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
Those of ordinary skill in the art may be aware that list described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and algorithm steps can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are actually
It is implemented in hardware or software, the specific application and design constraint depending on technical solution.Professional technician
Each specific application can be used different methods to achieve the described function, but this realization is it is not considered that exceed
The scope of the present invention.
In embodiment provided by the present invention, it should be understood that disclosed system and method can pass through others
Mode is realized.For example, system embodiment described above is only schematical, for example, the division of the module or unit,
Only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components can be with
In conjunction with or be desirably integrated into another system, or some features can be ignored or not executed.Another point, it is shown or discussed
Mutual coupling or direct-coupling or communication connection can be through some interfaces, the INDIRECT COUPLING of device or unit or
Communication connection can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated list
Member both can take the form of hardware realization, can also realize in the form of software functional units.
If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product
When, it can store in a computer readable storage medium.Based on this understanding, the technical solution of the embodiment of the present invention
Substantially all or part of the part that contributes to existing technology or the technical solution can be with software product in other words
Form embody, which is stored in a storage medium, including some instructions use so that one
Computer equipment (can be personal computer, server or the network equipment etc.) or processor (processor) execute this hair
The all or part of the steps of bright each embodiment the method for embodiment.And storage medium above-mentioned include: USB flash disk, mobile hard disk,
Read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic
The various media that can store program code such as dish or CD.
It is above-mentioned that technology contents of the invention are only further illustrated with embodiment, in order to which reader is easier to understand, but not
It represents embodiments of the present invention and is only limitted to this, any technology done according to the present invention extends or recreation, by of the invention
Protection.Protection scope of the present invention is subject to claims.
Claims (8)
1. a kind of test method of single-ended port transmission chip, which is characterized in that the described method includes:
Test the single port data transmission control that host obtains chip；
Test configurations are carried out to chip interior module to be measured by single port；
The test data of module to be measured is read according to test configurations, and the test data read is sent to survey by single port
Try host.
2. a kind of test method of single-ended port transmission chip according to claim 1, which is characterized in that described by single-ended
The step of mouth carries out test configurations to chip interior module to be measured, specifically includes the following steps:
Corresponding module register address to be measured is inputted by single port universal serial bus；
Register address is handled；
Control command is write in input；
Data will be controlled according to control command and register address to be written in corresponding module to be measured.
3. a kind of test method of single-ended port transmission chip according to claim 2, which is characterized in that described to register
The step of address is handled, specifically includes the following steps:
Asynchronous process；
Serioparallel exchange processing is carried out after asynchronous process.
4. a kind of test method of single-ended port transmission chip according to claim 1, which is characterized in that described according to test
The test data of module to be measured is read in configuration, and the test data read is sent to the step of test host by single port
Suddenly, specifically includes the following steps:
Carry out the read operation of chip interior bus；
It tests host and discharges single port data transmission control；
Chip obtains single-ended port transmission control；
Read the data in module register to be measured.
5. a kind of test macro of single-ended port transmission chip, which is characterized in that the system comprises acquiring unit, configuration unit with
And reading unit；
The acquiring unit obtains the single port data transmission control of chip for testing host；
The configuration unit, for carrying out test configurations to chip interior module to be measured by single port；
The reading unit, for reading the test data of module to be measured, and the test data that will be read according to test configurations
Test host is sent to by single port.
6. a kind of test macro of single-ended port transmission chip according to claim 5, which is characterized in that the configuration unit
Including input module, processing module, command module and writing module；
The input module, for inputting corresponding module register address to be measured by single port universal serial bus；
The processing module, for handling register address；
The command module writes control command for inputting；
The write module is written in corresponding module to be measured for that will control data according to control command and register address.
7. a kind of test macro of single-ended port transmission chip according to claim 6, which is characterized in that the processing module
Including asynchronous submodule and serioparallel exchange submodule；
The asynchronous submodule is used for asynchronous process；
The serioparallel exchange submodule, for carrying out serioparallel exchange processing after asynchronous process.
8. a kind of test macro of single-ended port transmission chip according to claim 5, which is characterized in that the reading unit
Including read through model, release module, obtain module and read module；
The read through model, for carrying out chip interior bus read operation；
The release module, for testing host release single port data transmission control；
The acquisition module obtains single-ended port transmission control for chip；
The read module, for reading the data in module register to be measured.
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| CN111426944A (en) * | 2020-03-30 | 2020-07-17 | 普源精电科技股份有限公司 | Chip test circuit and method and chip |
| CN111426945A (en) * | 2020-03-25 | 2020-07-17 | 北京中电华大电子设计有限责任公司 | Test method for improving chip test efficiency |
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