CN102967815A - Chip testing method, automated testing equipment and system - Google Patents
Chip testing method, automated testing equipment and system Download PDFInfo
- Publication number
- CN102967815A CN102967815A CN2012104412139A CN201210441213A CN102967815A CN 102967815 A CN102967815 A CN 102967815A CN 2012104412139 A CN2012104412139 A CN 2012104412139A CN 201210441213 A CN201210441213 A CN 201210441213A CN 102967815 A CN102967815 A CN 102967815A
- Authority
- CN
- China
- Prior art keywords
- ate
- test
- command information
- chip testing
- test event
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
An embodiment of the invention discloses a chip testing method, automated testing equipment and a system. The chip testing method includes that the automated testing equipment (ATE) tests ATE test items contained by a chip test. The ATE transmits command information used for triggering a personal computer (PC) to test PC test items contained by the chip test to the PC after finishing testing of the ATE test items. The ATE receives return information containing test results of the PC test items after the PC tests according to the command information. The ATE obtains chip test results according to the return information. The method, the equipment and the system effectively utilize reduce equipment cost brought by the high-end ATE, manual cost and time cost by chip test and reduce integral chip test cost accordingly.
Description
Technical field
The present invention relates to chip automatic test field, relate in particular to a kind of chip detecting method, automatically testing machine and system.
Background technology
In chip automatic test field, use common automatically testing machine (ATE, AUTOMATIC TEST EQUIPMENT) sometimes is difficult to satisfy the test of some function of chip or be difficult to simulate real environment for use, need this moment to use more high-end automatically testing machine to test, but high-end automatically testing machine is because self price is higher, can significantly increase testing cost.For the test chip function and do not increase testing cost, Import computer (PC, PERSONALCOMPUTER) subtest by the environment for use of the testing software analog chip on the PC, is tested chip.
Use ATE that chip is carried out the test first time with regard to needs after introducing the PC subtest, then use PC that chip is carried out the test second time.The partial function test that DC test and ATE can finish is mainly carried out in for the first time test, for the second time test carries out mainly that ATE can't test and functional test part that PC can test by software, and the result according to twice test judges that whether chip is by test again.
Because introduce the PC subtest, whole chip testing process comprises twice unrelated test, this is just so that whole chip testing process more complicated, required more manually-operated.More manually-operated, not only increase chip testing cost of labor, increase the chip loss that repeatedly manually-operated causes, and increase the time cost of chip testing, affect the production capacity of chip testing, so that the testing cost that whole chip testing spends is higher.
Summary of the invention
In view of this, the embodiment of the invention provides chip detecting method, automatically testing machine and system, the chip loss and the high problem of testing cost that need more manually-operated to cause to solve existing chip testing.
On the one hand, the embodiment of the invention provides chip detecting method, and the method comprises:
Automatic test machine ATE tests the ATE test event that chip testing comprises;
Described ATE sends to computer PC and to be used for triggering the command information that PC test event that described PC comprises described chip testing is tested after test is finished to described ATE test event;
Described ATE receives described PC tests the test result of comprising of rear transmission of described PC test event according to described command information return message;
Described ATE obtains the chip testing result according to described return message.
On the other hand, the embodiment of the invention also provides the ATE that is used for chip testing, and this ATE comprises:
Test cell is used for the ATE test event that chip testing comprises is tested;
Transmitting element is used for after described test cell is finished described ATE test event test, sends to computer PC to be used for triggering the command information that PC test event that described PC comprises described chip testing is tested;
Receiving element is used for receiving described PC and tests the return message of the test result of comprising of rear transmission of described PC test event according to the command information that described transmitting element sends;
Obtain the unit, be used for obtaining the chip testing result according to the described return message that described receiving element receives.
Another aspect, the embodiment of the invention also provide chip test system, and this chip test system comprises:
ATE is used for the ATE test event that chip testing comprises is tested; After test is finished to described ATE test event, send to described PC and to be used for triggering the command information that PC test event that described PC comprises described chip testing is tested;
PC, the PC test event that is used for after the described command information that receives described ATE transmission described chip testing being comprised is tested, after described test to the PC test event is finished, send the return message of the test result that comprises described PC test event to described ATE;
ATE is used for obtaining the chip testing result according to the described return message that described PC sends.
Compared with prior art, the chip detecting method that the embodiment of the invention provides, be used for ATE and the chip test system of chip testing, twice test ATE in the prior art and PC can being carried out respectively merges becomes once test, thereby minimizing manually-operated, reduce the chip loss that repeatedly manually-operated causes, simplify the flow process of whole chip testing, improve the production capacity of chip testing, effectively reduce cost of labor and time cost, thereby reduced the cost of whole chip testing.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use among the embodiment, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.Shown in accompanying drawing, above-mentioned and other purpose of the present invention, Characteristics and advantages will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Deliberately do not draw accompanying drawing by physical size equal proportion convergent-divergent, focus on illustrating purport of the present invention.
Fig. 1 is the process flow diagram of an embodiment of chip detecting method of the present invention;
Fig. 2 is the process flow diagram of another embodiment of chip detecting method of the present invention;
Fig. 3 is the process flow diagram of another embodiment of chip detecting method of the present invention;
Fig. 4 is the process flow diagram of an embodiment of chip detection ATE of the present invention;
Fig. 5 is the process flow diagram of another embodiment of chip detection ATE of the present invention;
Fig. 6 is an embodiment block diagram of embodiment of the invention chip detecting system;
Fig. 7 is another embodiment block diagram of embodiment of the invention chip detecting system.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is carried out clear, complete description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, the every other embodiment that those of ordinary skills obtain under the prerequisite of not paying creative work belongs to the scope of protection of the invention.
Referring to Fig. 1, be the process flow diagram of an embodiment of chip detecting method of the present invention, the method comprises the steps:
Step 101, automatic test machine ATE tests the ATE test event that chip testing comprises.
Optionally, the test that ATE carries out described ATE test event also comprises before, receives the command information of the described chip testing of beginning; ATE tests the ATE test event that chip testing comprises after receiving described command information.
Optionally, described ATE carries out the test of described ATE test event, is ATE after a front chip testing obtains the chip testing result, and the ATE test event that automatically begins chip testing is comprised is tested.
Step 102, described ATE sends to computer PC and to be used for triggering the command information that PC test event that described PC comprises described chip testing is tested after test is finished to described ATE test event.
Optionally, whether ATE can pass through the test of ATE test event all to PC transmission command information by chip after the test of ATE test event is finished.
Optionally, ATE can only just send command information to PC after chip passes through the test of ATE test event, when chip does not pass through the test of ATE test event, directly assert chip not by chip testing, does not send command information to PC.
ATE can directly send command information to PC, also can send command information to PC by other devices.The content of command information and form can be set as required in advance, when receiving the information of predetermined content and form, PC just begins to carry out the test of PC test event, to prevent causing PC when not needing to carry out the test of PC test event, still to carry out the test of PC test event because of other information interference.
Step 103, described ATE receives described PC tests the test result of comprising of rear transmission of described PC test event according to described command information return message.
Can being one group and representing that chip passes through the data of the test of PC test event of the return message that PC sends afterwards in the test of chip by the PC test event, the return message that PC does not send during the test by the PC test event at chip can be other data.
Optionally, the generation that can't draw the test result situation because communication ATE not smooth or that other reasons causes can't receive return message for a long time in order to prevent, can set a waiting time for ATE receives PC transmission return message, ATE receives the return message that PC sends within waiting time, do not receive return messages that PC sends and determine that then described chip testing do not pass through within waiting time.
Step 104, described ATE obtains the chip testing result according to described return message.
After ATE receives the return message of PC transmission, content to described return message is analyzed, if return message is the information of expression chip by the test of PC test event, and chip has also passed through the test of ATE test event, then can draw chip by the test result of chip testing, if the content of return message is not the information that represents the test of chip by the PC test event, then can draw the not test result by chip testing of chip.
Can find out from above-described embodiment, the present invention merges by twice test that ATE and PC are carried out respectively becomes once test, thereby minimizing manually-operated, reduce the chip loss that repeatedly manually-operated causes, simplified the flow process of whole chip testing, improve the production capacity of chip testing, effectively reduced cost of labor and time cost, thereby reduced the cost of whole chip testing.
Referring to Fig. 2, be an embodiment process flow diagram of chip detecting method of the present invention, this embodiment shows in detail the method for chip testing of the present invention, and the method comprises the steps:
Step 201, ATE receives the command information that begins to test.
The command information that begins to test can be the command information that the technician directly sends to ATE, also can be the command information that the technician sends to ATE by other equipment.
Step 202, ATE carries out the test of the ATE test event that chip testing comprises.
The test of ATE test event can comprise carries out the test of ATE test event to a chip, also can comprise the test of a plurality of chips being carried out the ATE test event.For each chip, if this chip comprises a plurality of ATE test events, then one by one each ATE test event is tested; If a plurality of chips comprise ATE test event of the same race, then can carry out simultaneously the test to this ATE test event of the same race.
Step 203, ATE by after the test of ATE test event, uses PATTERN functional simulation serial ports at chip, sends to level converter to be used for the command information that order PC begins the test of PC test event.
ATE can utilize PATTERN functional simulation serial communication mode and computing machine to communicate, adopt default baud rate and data layout, serial ports to PC sends the command information that begins the test of PC test event for PC, but because ATE adopts PATTERN functional simulation serial ports, and be not real serial equipment, so the level of the command information that ATE sends is not the serial ports level of PC, ATE can't directly send command information by serial ports to PC, therefore needs the level reforming unit that the level of command information is converted into the serial ports level.
Need to prove that at this when chip did not pass through the test of ATE test event, described ATE can directly draw test chip not by the test result of chip testing, no longer sends command information to PC.
Step 204, level converter carries out level conversion to the command information that receives, and is PC serial ports level with the level conversion of command information.
Level converter can be the serial ports level transferring chip that links to each other with ATE, also can be the single supply level transferring chip.
Step 205, level converter sends through the command information after the level conversion to the serial ports of PC.
Step 206, PC brings into use testing software to carry out the test of the PC test event that chip testing comprises receive the command information that level converter sends by serial ports after.
The test of PC test event can comprise carries out the test of PC test event to a chip, also can comprise the test of a plurality of chips being carried out the PC test event.For each chip, if this chip comprises a plurality of PC test events, then one by one each PC test event is tested; If a plurality of chips comprise PC test event of the same race, then can carry out simultaneously the test to this PC test event of the same race.
Step 207, after the test of described PC test event was finished, PC sent the return message that comprises described PC test event test result by serial ports to level converter.
PC adopts baud rate baud rate and the data layout identical with data layout that adopts when PC sends command information with ATE to send return message to ATE by serial ports after the test of PC test event is finished, because ATE adopts PATTERN functional simulation serial ports to receive return message, and be not real serial equipment, what therefore PC sent the return message employing is the serial ports level of PC, rather than the level of ATE reception information employing, PC can't directly send to ATE with return message by serial ports, needs the level reforming unit that the level of return message is converted into the ATE level.
Step 208, level converter carries out level conversion to the return message that receives, and is that ATE passes through PATTERN functional simulation serial ports and receives the needed level of information with the level conversion of return message.
Level converter can be the serial ports level transferring chip that links to each other with ATE, also can be other active level converter.
Step 209, level converter sends through the return message after the level conversion to ATE.
Step 210, ATE obtains the chip testing net result according to described return message.
ATE analyzes the test result that the content of return message comprises, when returning test result and be the data of the chip test of passing through the PC test event, can draw chip by the test result of chip testing, if test result is not the data that chip passes through the test of PC test event, then can draw the not test result by chip testing of chip.
Can find out from above-described embodiment, the present invention is by realizing the serial communication between ATE and the PC, the twice test operation merging that needs the technician to carry out respectively become test operation one time, thereby reduced the manually-operated of the requirements of process of whole chip testing, reduce the loss that chip is caused because of manually-operated repeatedly, effectively reduce cost of labor and time cost, improve the chip testing production capacity, thereby reduced the cost of whole chip testing.
Below in conjunction with a specific embodiment chip detecting method of the present invention being done one specifies.
Referring to Fig. 3, be an embodiment process flow diagram of chip detecting method of the present invention, the method comprises the steps:
Step 301, the command information that begins to test that ATE reception technique personnel directly send.
Step 302, ATE carries out the test of ATE test event.
Step 303, ATE is after chip passes through the test of ATE test event, use PATTERN functional simulation serial ports, using baud rate is 115200, data layout is the information sender formula of 8 data bit, 1 position of rest, no parity position, sends to level converter to be used for the serial data 0xXX that order PC begins the test of PC test event.
Wherein, 0xXX is the hexadecimal data that ATE and PC arrange in advance, and particular content can be selected as required.
Step 304, level converter is PC serial ports level with the level conversion of the serial data 0xXX that receives.
Step 305, level converter sends through the 0xXX after the level conversion to the serial ports of PC.
Step 306 when the serial data that PC receives by serial ports is 0xXX, brings into use testing software to carry out the test of PC test event.
Step 307, PC is after the test of PC test event is finished, using baud rate is 115200, and data layout is the information sender formula of 8 data bit, 1 position of rest, no parity position, sends the expression chip by the serial data 0xYY of PC test event to level converter.
Wherein, 0xYY is the hexadecimal data that ATE and PC arrange in advance, and particular content can be selected as required.
Step 308, level converter carries out level conversion to the serial data 0xYY that receives, and is that ATE passes through PATTERN functional simulation serial ports and receives the needed level of information with the level conversion of serial data 0xYY.
Step 309, level converter sends through the serial data 0xYY after the level conversion to ATE.
Step 310, ATE draws chip by the final testing result of chip testing according to 0xYY.
Can find out from above-described embodiment, the present invention is by realizing the serial communication between ATE and the PC, the twice test operation merging that needs the technician to carry out respectively become test operation one time, thereby reduced the manually-operated of the requirements of process of whole chip testing, reduce the chip loss that repeatedly manually-operated causes, effectively reduce cost of labor and time cost, thereby reduced the cost of whole chip testing, improve the production capacity of chip testing; In addition, adopt the particular data of set form when ATE and PC communicate, can effectively prevent because signal disturbs or the signal mistake is sent out the test crash that causes.
Corresponding with the enforcement of chip detecting method of the present invention, the present invention also provides the embodiment that is used for the ATE of chip testing.
Referring to Fig. 4, be the embodiment block diagram of ATE of the present invention.
This ATE comprises: test cell 401, and transmitting element 402, receiving element 403 obtains unit 404.
Wherein, described test cell 401 is used for the ATE test event that chip testing comprises is tested.
Optionally, described test cell 401, concrete being used for tests the described ATE test event that chip testing comprises after a front chip testing obtains the chip testing net result.
Described transmitting element 402 is used for after finishing in 401 pairs of described ATE test events tests of described test cell, sends to PC to be used for triggering the command information that PC test event that described PC comprises described chip testing is tested.
Optionally, described transmitting element 402, concrete being used for after 401 pairs of described ATE test event tests of test cell are finished, utilize PATTERN functional simulation serial ports, adopt default baud rate and default data layout, send to described PC and to be used for triggering the command information that PC test event that described PC comprises described chip testing is tested, described command information sends to described PC through after the level conversion.
Described receiving element 403 is used for receiving described PC and tests the return message of the test result of comprising of rear transmission of described PC test event according to the command information that described transmitting element 402 sends.
Optionally, described receiving element 403, receives described PC and tests the return message of the test result of comprising of rear transmission of described PC test event according to the command information that described transmitting element 402 sends concrete being used within the waiting time of setting.
Optionally, described receiving element 403, concrete for utilizing PATTERN functional simulation serial ports, after receiving command information that described PC sends according to described transmitting element 402 and testing, adopt baud rate and the data layout identical with described default data layout with described default baud rate, the return message of the test result that comprises described PC test event that sends by serial ports, described return message sends to described receiving element 403 through after the level conversion.
Described acquisition unit 404 is used for obtaining the chip testing result according to the described return message that described receiving element receives.
Optionally, described acquisition unit 404, when failing to receive the described return message that described PC sends, determines that described chip testing do not pass through at concrete being used within the waiting time that described receiving element 403 is being set.
Can find out from above-described embodiment, the invention provides a kind of ATE for chip testing, not only can carry out the test of the ATE test event that chip testing comprises, and can order PC to carry out the test of the PC test event that chip testing comprises, and draw the final test result of chip according to the test result of PC, not only reduced the manually-operated of the requirements of process of whole chip testing, reduce the loss that chip is caused because of manually-operated repeatedly, effectively reduce cost of labor and time cost, thereby reduced the cost of whole chip testing, improve the production capacity of chip testing, and reduced the probability of the appearance mistake of bringing because of manually-operated.
Referring to Fig. 5, be another embodiment block diagram of ATE of the present invention.
This ATE comprises: command information receiving element 501, and test cell 502, transmitting element 503, receiving element 504 obtains unit 505.
Wherein, described command information receiving element 501 is used for receiving the command information that begins chip testing.
Described test cell 502 is used for after command information receiving element 501 receives the command information of described beginning chip testing the ATE test event that chip testing comprises being tested.
Optionally, described test cell 502, concrete being used for tests the described ATE test event that chip testing comprises after a front chip testing obtains the chip testing net result.
Described transmitting element 503 is used for after 502 pairs of described ATE test events tests of described test cell are finished, and sends to PC to be used for triggering the command information that PC test event that described PC comprises described chip testing is tested.
Optionally, described transmitting element 503, concrete being used for after 502 pairs of described ATE test event tests of described test cell are finished, utilize PATTERN functional simulation serial ports, adopt default baud rate and default data layout, send to described PC and to be used for triggering the command information that PC test event that described PC comprises described chip testing is tested, described command information sends to described PC through after the level conversion.
Described receiving element 504 is used for receiving described PC and tests the return message of the test result of comprising of rear transmission of described PC test event according to the command information that described transmitting element 503 sends.
Optionally, described receiving element 504, receives described PC and tests the return message of the test result of comprising of rear transmission of described PC test event according to the command information that described transmitting element 503 sends concrete being used within the waiting time of setting.
Optionally, described receiving element 504, concrete for utilizing PATTERN functional simulation serial ports, after receiving command information that described PC sends according to described transmitting element 503 and testing, adopt baud rate and the data layout identical with described default data layout with described default baud rate, the return message of the test result that comprises described PC test event that sends by serial ports, described return message sends to described receiving element 504 through after the level conversion.
Described acquisition unit 505 is used for obtaining the chip testing result according to the described return message that described receiving element receives.
Optionally, described receiving element 505, when failing to receive the described return message that described PC sends, determines that described chip testing do not pass through at concrete being used within the waiting time that described receiving element 504 is being set.
Can find out from above-described embodiment, the invention provides a kind of ATE for chip testing, can after receiving instruction, begin chip testing, also can after finishing, a front chip testing automatically carry out new test, not only reduced the manually-operated of the requirements of process of whole chip testing, reduce the loss that chip is caused because of manually-operated repeatedly, effectively reduce cost of labor, and can reduce because the time cost that manually-operated brings, improve the production capacity of chip testing, thereby reduced the cost of whole chip testing, and reduced the probability of the appearance mistake of bringing because of manually-operated.
Corresponding with the enforcement of chip detecting method of the present invention and ATE, the present invention also provides the embodiment of chip test system.
Referring to Fig. 6, be an embodiment block diagram of chip test system of the present invention.
The system that realizes method of testing of the present invention comprises ATE 601 and PC 602.
Wherein, described ATE 601 is used for the ATE test event that chip testing comprises is tested; After test is finished to described ATE test event, send to described PC 602 and to be used for triggering the command information that PC test event that 602 pairs of described chip testings of described PC comprise is tested; When not testing by the ATE test event, chip determines that chip is not by test.
The PC test event that described PC 602 is used for after the described command information that receives described ATE 601 transmissions described chip testing being comprised is tested, after described test to the PC test event is finished, send the return message of the test result that comprises described PC test event to described ATE 601.
Described ATE 601 is used for obtaining the chip testing result according to the described return message that described PC 602 sends.
Can find out from above-described embodiment, the present invention is combined into a test macro by ATE and the PC that will originally independently test separately, chip is tested, thereby simplify the flow process of whole chip testing, reduce the loss that chip is caused because of manually-operated repeatedly, effectively reduce cost of labor and time cost, improve the production capacity of chip testing, thereby reduced the cost of whole chip testing.
Referring to Fig. 7, be another embodiment block diagram of chip test system of the present invention.
The system that realizes method of testing of the present invention comprises ATE 701, level converter 702 and PC 703.
Wherein, described ATE 701 is used for the ATE test event that chip testing comprises is tested; After described ATE test event test is finished, utilize PATTERN functional simulation serial ports, adopt default baud rate and default data layout, send to described level converter 702 and be used for triggering the command information that PC test event that 703 pairs of described chip testings of described PC comprise is tested; When not testing by the ATE test event, chip determines that chip is not by test.
Described level converter 702, the level conversion that is used for described command information that ATE 701 is sent is the required level of PC 703 serial ports, and sends to PC 703.
Described PC 703, the PC test event that is used for after the described command information that receives described level converter 702 transmissions described chip testing being comprised is tested, after described test to the PC test event is finished, adopt baud rate and the data layout identical with described default data layout with described default baud rate, comprise the return message of the test result of described PC test event by serial ports to described level converter 702 transmissions.
Described level converter 702 is used for the required level of level conversion ATE 701 of return message that described PC 703 is sent, and sends to ATE 701.
Described ATE 701 is used for obtaining the chip testing result according to the described return message that described level converter 702 sends.
Can find out from above-described embodiment, the present invention is combined into a test macro by ATE and the PC that will originally independently test separately, can utilize the auxiliary serial communication that carries out of level converter between ATE and the PC, realization is controlled the test that PC begins the PC test event automatically by ATE, no longer need the technician manually to begin the test of PC test event, reduce the loss that chip is caused because of manually-operated repeatedly, and effectively reduce cost of labor and time cost, improve the production capacity of chip testing, thereby reduced the cost of whole chip testing.
The professional can also further should be able to recognize, unit and the algorithm steps of each example of describing in conjunction with embodiment disclosed herein, can realize with electronic hardware, computer software or the combination of the two, for the interchangeability of hardware and software clearly is described, composition and the step of each example described in general manner according to function in the above description.These functions are carried out with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.The professional and technical personnel can specifically should be used for realizing described function with distinct methods to each, but this realization should not thought the scope that exceeds the embodiment of the invention.
The method of describing in conjunction with embodiment disclosed herein or the step of algorithm can directly use the software module of hardware, processor execution, and perhaps the combination of the two is implemented.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the embodiment of the invention.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and General Principle as defined herein can in the situation of the spirit or scope that do not break away from the embodiment of the invention, realize in other embodiments.Therefore, the embodiment of the invention will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
The above only is the preferred embodiment of the embodiment of the invention; not in order to limit the embodiment of the invention; all within the spirit and principle of the embodiment of the invention, any modification of doing, be equal to replacement, improvement etc., all should be included within the protection domain of the embodiment of the invention.
Claims (13)
1. a chip detecting method is characterized in that, described method comprises:
Automatic test machine ATE tests the ATE test event that chip testing comprises;
Described ATE sends to computer PC and to be used for triggering the command information that PC test event that described PC comprises described chip testing is tested after test is finished to described ATE test event;
Described ATE receives described PC tests the test result of comprising of rear transmission of described PC test event according to described command information return message;
Described ATE obtains the chip testing result according to described return message.
2. the method for claim 1 is characterized in that,
Before the ATE test event that described ATE comprises chip testing is tested, also comprise: the command information that receives the described chip testing of beginning;
Described ATE tests the ATE test event that chip testing comprises, and is specially: described ATE tests the ATE test event that chip testing comprises after receiving described command information.
3. the method for claim 1 is characterized in that,
The ATE test event that described ATE comprises chip testing is tested and is specially: after a front chip testing obtained the chip testing result, the ATE test event that ATE begins chip testing is comprised was automatically tested.
4. such as the described method of claims 1 to 3 any one claim, it is characterized in that,
Described ATE receives described PC and tests the return message of the test result of comprising of rear transmission of described PC test event according to described command information, is specially:
Within the waiting time of setting, described ATE receives described PC tests the test result of comprising of rear transmission of described PC test event according to described command information return message;
Described method also comprises: if described ATE does not receive described return message within the waiting time of setting, then definite described chip testing is not passed through.
5. such as the described method of claim 1 to 4 any one claim, it is characterized in that,
Described ATE sends to computer PC and to be used for triggering the command information that PC test event that described PC comprises described chip testing is tested after test is finished to described ATE test event, is specially:
Described ATE is after finishing described ATE test event test, utilize PATTERN functional simulation serial ports, adopt default baud rate and default data layout, send to described PC and to be used for triggering the command information that PC test event that described PC comprises described chip testing is tested, described command information sends to described PC through after the level conversion;
Described ATE receives described PC and tests the return message of the test result of comprising of rear transmission of described PC test event according to described command information, is specially:
Described ATE utilizes PATTERN functional simulation serial ports, after receiving described PC and testing according to described command information, adopt baud rate and the data layout identical with described default data layout with described default baud rate, the return message of the test result that comprises described PC test event that sends by serial ports, described return message sends to described ATE through after the level conversion.
6. method as claimed in claim 5 is characterized in that,
Described default baud rate is specially: 115200;
Described default data layout is specially: 8 data bit, 1 position of rest, no parity position;
Described command information is specially: the command information of hexadecimal format;
Described return message is specially: the return message of hexadecimal format.
7. ATE who is used for chip testing is characterized in that described ATE comprises:
Test cell is used for the ATE test event that chip testing comprises is tested;
Transmitting element is used for after described test cell is finished described ATE test event test, sends to computer PC to be used for triggering the command information that PC test event that described PC comprises described chip testing is tested;
Receiving element is used for receiving described PC and tests the return message of the test result of comprising of rear transmission of described PC test event according to the command information that described transmitting element sends;
Obtain the unit, be used for obtaining the chip testing result according to the described return message that described receiving element receives.
8. ATE as claimed in claim 7 is characterized in that,
Also comprise: the command information receiving element is used for receiving the command information that begins chip testing;
Described test cell, concrete being used for tests the ATE test event that chip testing comprises after the command information receiving element receives the command information of described beginning chip testing.
9. ATE as claimed in claim 8 is characterized in that,
Described test cell, concrete being used for tests the described ATE test event that chip testing comprises after a front chip testing obtains the chip testing net result.
10. such as the described ATE of claim 7 to 9 any one claim, it is characterized in that,
Described receiving element, receives described PC and tests the return message of the test result of comprising of rear transmission of described PC test event according to the command information that described transmitting element sends concrete being used within the waiting time of setting;
Described acquisition unit, determines that described chip testing do not pass through at concrete being used for when described receiving element does not receive described return message within the waiting time of setting.
11. such as the described ATE of claim 7 to 10 any one claim, it is characterized in that,
Described transmitting element, concrete being used for after test cell is finished described ATE test event test, utilize PATTERN functional simulation serial ports, adopt default baud rate and default data layout, send to described PC and to be used for triggering the command information that PC test event that described PC comprises described chip testing is tested, described command information sends to described PC through after the level conversion;
Described receiving element, concrete for utilizing PATTERN functional simulation serial ports, after receiving command information that described PC sends according to described transmitting element and testing, adopt baud rate and the data layout identical with described default data layout with described default baud rate, the return message of the test result that comprises described PC test event that sends by serial ports, described return message sends to described ATE through after the level conversion.
12. a chip test system is characterized in that described system comprises ATE and PC,
Described ATE is used for the ATE test event that chip testing comprises is tested; After test is finished to described ATE test event, send to described PC and to be used for triggering the command information that PC test event that described PC comprises described chip testing is tested;
Described PC, the PC test event that is used for after the described command information that receives described ATE transmission described chip testing being comprised is tested, after described test to the PC test event is finished, send the return message of the test result that comprises described PC test event to described ATE;
Described ATE is used for obtaining the chip testing result according to the described return message that described PC sends.
13. system as claimed in claim 12 is characterized in that,
Also comprise level converter,
Described ATE, concrete being used for after described ATE test event test is finished, utilize PATTERN functional simulation serial ports, adopt default baud rate and default data layout, send to described level converter and be used for triggering the command information that PC test event that described PC comprises described chip testing is tested;
Described level converter, the level conversion that is used for described command information is the required level of described PC serial ports, and sends to described PC;
Described PC, the concrete PC test event that is used for after the described command information that receives described level converter transmission described chip testing being comprised is tested, after described test to the PC test event is finished, adopt baud rate and the data layout identical with described default data layout with described default baud rate, comprise the return message of the test result of described PC test event by serial ports to described level converter transmission;
Described level converter is used for the required level of the described ATE of the level conversion of described return message, and sends to described ATE.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210441213.9A CN102967815B (en) | 2012-11-07 | 2012-11-07 | Chip testing method, automated testing equipment and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210441213.9A CN102967815B (en) | 2012-11-07 | 2012-11-07 | Chip testing method, automated testing equipment and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102967815A true CN102967815A (en) | 2013-03-13 |
| CN102967815B CN102967815B (en) | 2014-10-29 |
Family
ID=47798093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210441213.9A Active CN102967815B (en) | 2012-11-07 | 2012-11-07 | Chip testing method, automated testing equipment and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102967815B (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105004985A (en) * | 2015-06-30 | 2015-10-28 | 深圳市芯海科技有限公司 | Chip automatic test method used for multi-temperature test |
| CN105761760A (en) * | 2016-02-16 | 2016-07-13 | 上海华虹宏力半导体制造有限公司 | Method for testing memory chip capable of realizing redundant function |
| CN106021056A (en) * | 2016-05-31 | 2016-10-12 | 四川九洲空管科技有限责任公司 | Automatic testing system and method for Arinc429 communication chip |
| CN106094804A (en) * | 2016-07-18 | 2016-11-09 | 中国电子信息产业集团有限公司第六研究所 | A kind of cross-platform PLC plate level frock based on QT test system and method for testing thereof |
| CN108802601A (en) * | 2018-06-21 | 2018-11-13 | 记忆科技(深圳)有限公司 | Chip detecting method, device and the computer equipment of loop transfer |
| CN109061446A (en) * | 2018-10-10 | 2018-12-21 | 记忆科技(深圳)有限公司 | A kind of test method and system of single-ended port transmission chip |
| CN109782153A (en) * | 2019-01-14 | 2019-05-21 | 大唐微电子技术有限公司 | A kind of method, apparatus of chip testing, chip and computer storage medium |
| CN110376503A (en) * | 2019-06-27 | 2019-10-25 | 福州数据技术研究院有限公司 | A kind of AI accelerates chip performance test method and its device |
| CN111273153A (en) * | 2020-01-21 | 2020-06-12 | 广芯微电子（广州）股份有限公司 | Automatic testing method, device and system for chip |
| CN112799887A (en) * | 2020-12-17 | 2021-05-14 | 珠海泰芯半导体有限公司 | Chip FT test system and test method |
| CN113359014A (en) * | 2021-08-11 | 2021-09-07 | 深圳英集芯科技股份有限公司 | Fool-proof method and system for chip test |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1756960A (en) * | 2003-03-31 | 2006-04-05 | 爱德万测试株式会社 | Test device and test method |
| US20060248425A1 (en) * | 2005-04-29 | 2006-11-02 | Stimson Randall B | Delayed processing of site-aware objects |
| US20070245188A1 (en) * | 2006-03-31 | 2007-10-18 | Eudyna Devices Inc. | Testing system, testing system control method, and test apparatus |
-
2012
- 2012-11-07 CN CN201210441213.9A patent/CN102967815B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1756960A (en) * | 2003-03-31 | 2006-04-05 | 爱德万测试株式会社 | Test device and test method |
| US20060248425A1 (en) * | 2005-04-29 | 2006-11-02 | Stimson Randall B | Delayed processing of site-aware objects |
| US20070245188A1 (en) * | 2006-03-31 | 2007-10-18 | Eudyna Devices Inc. | Testing system, testing system control method, and test apparatus |
Non-Patent Citations (2)
| Title |
|---|
| 张凯虹: "一种FPGA验证与测试的方法介绍", 《计算机与数字工程》, vol. 38, no. 9, 20 September 2010 (2010-09-20), pages 70 - 72 * |
| 赵志诚 等: "微型计算机控制的芯片自动测试系统", 《仪器制造》, no. 2, 1 May 1983 (1983-05-01), pages 1 - 5 * |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105004985A (en) * | 2015-06-30 | 2015-10-28 | 深圳市芯海科技有限公司 | Chip automatic test method used for multi-temperature test |
| CN105761760B (en) * | 2016-02-16 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | The method for realizing redundancy feature storage core built-in testing |
| CN105761760A (en) * | 2016-02-16 | 2016-07-13 | 上海华虹宏力半导体制造有限公司 | Method for testing memory chip capable of realizing redundant function |
| CN106021056A (en) * | 2016-05-31 | 2016-10-12 | 四川九洲空管科技有限责任公司 | Automatic testing system and method for Arinc429 communication chip |
| CN106021056B (en) * | 2016-05-31 | 2018-07-13 | 四川九洲空管科技有限责任公司 | A kind of Arinc429 communication chips Auto-Test System and test method |
| CN106094804A (en) * | 2016-07-18 | 2016-11-09 | 中国电子信息产业集团有限公司第六研究所 | A kind of cross-platform PLC plate level frock based on QT test system and method for testing thereof |
| CN108802601A (en) * | 2018-06-21 | 2018-11-13 | 记忆科技(深圳)有限公司 | Chip detecting method, device and the computer equipment of loop transfer |
| CN109061446A (en) * | 2018-10-10 | 2018-12-21 | 记忆科技(深圳)有限公司 | A kind of test method and system of single-ended port transmission chip |
| CN109782153A (en) * | 2019-01-14 | 2019-05-21 | 大唐微电子技术有限公司 | A kind of method, apparatus of chip testing, chip and computer storage medium |
| CN110376503A (en) * | 2019-06-27 | 2019-10-25 | 福州数据技术研究院有限公司 | A kind of AI accelerates chip performance test method and its device |
| CN110376503B (en) * | 2019-06-27 | 2021-07-27 | 福州数据技术研究院有限公司 | AI acceleration chip performance test method and device |
| CN111273153A (en) * | 2020-01-21 | 2020-06-12 | 广芯微电子（广州）股份有限公司 | Automatic testing method, device and system for chip |
| CN112799887A (en) * | 2020-12-17 | 2021-05-14 | 珠海泰芯半导体有限公司 | Chip FT test system and test method |
| CN113359014A (en) * | 2021-08-11 | 2021-09-07 | 深圳英集芯科技股份有限公司 | Fool-proof method and system for chip test |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102967815B (en) | 2014-10-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102967815B (en) | Chip testing method, automated testing equipment and system | |
| CN101789889B (en) | Method and system for automatic testing communication equipment | |
| CN101782778B (en) | Multifunctional testing platform of vehicle-mounted information system and control structure of main controller | |
| CN101499937A (en) | Software and hardware collaborative simulation verification system and method based on FPGA | |
| CN104483959A (en) | Fault simulation and test system | |
| CN111339731B (en) | FPGA (field programmable Gate array) verification platform and method for SoC (System on chip) | |
| CN104348673A (en) | Debugging and testing method, main control board and business boards | |
| CN103631688A (en) | Method and system for testing interface signal | |
| CN106649021A (en) | Testing device for PCIe slave device | |
| CN111064449A (en) | Digital down-sampling filter verification platform and method based on UVM platform | |
| CN103309784B (en) | Test system and method for testing | |
| CN102223452A (en) | Method and system for testing text telephone (TTY) of mobile terminals | |
| CN108173713A (en) | A kind of more network interface card parallel test methods of list PC | |
| CN103809051B (en) | The detection method of switch matrix, Auto-Test System and switch matrix therein | |
| CN103838664A (en) | Pressure testing method and device | |
| CN107632910A (en) | A kind of method of testing and device | |
| CN106936658A (en) | The method of testing and test platform of test case, simulation test equipment | |
| CN202481100U (en) | Rail transit guiding and dispatching system | |
| CN107368063A (en) | A kind of former car simulated-bus software and its system for vehicle electronics product debugging test | |
| CN104581147B (en) | HDMI and MIPI functions mutually testing method and device | |
| CN103544108A (en) | System and method for testing embedded software integration strength | |
| CN203243346U (en) | Command system network tester | |
| CN103759951B (en) | The method of testing of the brake performance tester of multiple stage agricultural vehicle can be measured simultaneously | |
| CN107404731A (en) | The test system and method for testing of wireless communication module | |
| CN113835946B (en) | Pressure test method for data exchange |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |