CN101499937A - Software and hardware collaborative simulation verification system and method based on FPGA - Google Patents
Software and hardware collaborative simulation verification system and method based on FPGA Download PDFInfo
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Abstract
The invention relates to a software and hardware co-emulation verification system based on FPGA and a method thereof. The system comprises a network tester, a software system part which is arranged on an user PC terminal and a hardware system part used for simulating an integrated circuit chip; wherein, the software system part comprises a controlling platform of the network tester and an embedded system interface module; the hardware system part comprises a CPU interface module, an interface converter logic module in FPGA, a virtual waiting-for-testing module and a network interface module which can be used for realizing data exchanging between the interface converter logic module and the controlling platform of the network tester. The method is formed on the basis of the systems. The software and hardware co-emulation verification system based on FPGA and the method thereof have the advantages of being capable of carrying out high-speed emulation, greatly saving the time consumption for testing, realizing the whole-chip and whole-function verification and supporting the testing of a plurality of varieties of chips; simultaneously, the invention also has good physical expandability, adopts good debugging tools and further increases the emulation verification efficiency.
Description
Technical field
The present invention relates to the simulation checking system and the method for a kind of integrated circuit (IC) chip, relate in particular to a kind of software and hardware co-emulation verification system and method based on FPGA.
Background technology
High speed development along with large scale integrated circuit technology and network service, Ethernet switching chip has obtained using widely in network service, and because its applied environment more and more widely and complicated, make that also the function that Ethernet switching chip comprised becomes increasingly complex, capacity is increasing, and the emulation difficulty of chip is also increasing day by day fast.Therefore, how to accelerate the development rate of Ethernet switching chip, the cycle that shortens checking just becomes the present important topic that we face.
In existing integrated circuits (IC) the chip emulation checking field, mainly adopt dual mode to carry out chip emulation/checking: a kind of is the software simulation emulation mode, and another kind is based on the hardware simulator emulation mode of field programmable gate array (FPGA).The a large amount of experiment shows that in carrying out integrated circuit (IC) design process, existing needs to use the situation that surpasses abundant test of 1,000,000 clock cycle and proofing chip systemic-function.If the software simulation emulation mode of utilizing prior art to provide, the testing authentication performance of chip will drop to 1-5HZ, and this will cause the sharp increase of testing time and error probability.If use software to add hardware accelerator emulation mode, though the hardware emulator operation is very fast, but produce and to finish by software because also have a large amount of analog computations or encourage, so the raising of whole simulation system speed is limited, usually between several times to tens times.Yet, if use is carried out emulation mode based on the FPGA hardware emulator and is verified, though can realize other high-speed simulation of MHz level, the also real time execution of support software simultaneously,, it but has some open defects, for example, lack and friendly human-computer interaction interface and input-output system the input of inconvenient emulation excitation and the collection of response, can only support the description of RTL level, can not carry out emulation high-level behavior description module; Simultaneously the value of the leg signal of FPGA inside and register can not Direct observation, exchanges trial work and has brought very big inconvenience.However, utilize the high speed performance of FPGA hardware emulator, still foot improves the effective measures of verification efficiency, therefore, how to adopt new method to improve the subject matter that its shortcoming has just become current chip checking emulation field to face.Just under this background, be suggested based on the notion of the software and hardware cooperating simulation of FPGA.
This main design concept based on the software and hardware cooperating simulation system of FPGA is: with the function complexity, need a large amount of hardware designs modules of calculating to download to test in the FPGA hardware platform and verify, other module sections that will design simultaneously and test and excitation signal generator module and response results analysis module are arranged in PC or the work station, thereby have realized that soft, hardware designing two portions carries out simultaneously.The emulation that so not only can utilize the high speed performance of FPGA hardware platform to come accelerating module, and simultaneously owing to combine work with software simulator on PC or the work station, also overcome hardware platform and do not had good human-computer interaction interface, can't observe quickly and easily shortcomings such as excitation and response, improve simulation efficiency greatly, shortened the cycle of design, proving time and launch products.
This groundwork flow process based on the software and hardware cooperating simulation system of FPGA is as follows:
Excitation input process: at first generate test vector at software section (on PC or the work station), with these test vectors by certain conversion after by connecting on the message sink module of FPGA simulator that bottom physical channel soft, hardware is sent to hardware components, after last transceiver module is analyzed the information of receiving and is recovered, excitation is input on the input port of corresponding design chips to be measured (DUT) according to certain time sequence, uses for the DUT operation;
The response processing procedure: after the excitation input, DUT begins operate as normal, and its output port output response signal after the information receiving and transmitting module of hardware components receives these message, carries out exporting to software section after certain format conversion.
Existing software and hardware cooperating simulation method based on FPGA does not have special Ethernet interface, connects ethernet device if desired, then needs to increase in addition transducer, and a large amount of the participating of user also wanted in test and excitation signal and interpretation of result.Reduced simulation efficiency inevitably.
Summary of the invention
At the deficiency of above present analogue system, the objective of the invention is to propose a kind of improved and software and hardware co-emulation verification system and the method that can expand, improved the efficient of emulation, shortened the research and development of products cycle.
In order to achieve the above object, the present invention has adopted following technical scheme:
A kind of software and hardware co-emulation verification system based on FPGA, comprise network tester, be arranged at software systems part in the user PC end and the hardware system part that integrated circuit (IC) chip is simulated, software systems partly comprise the controlling platform and the embedded system interface module of network tester, hardware system partly comprises the cpu i/f module, the chip of realizing in interface conversion logic module in the FPGA and the FPGA virtual to be tested, it is characterized in that, described hardware system also comprises Network Interface Module, and this Network Interface Module can be realized the data interaction between the controlling platform of interface conversion logic module and network tester.
Particularly, in the described software systems part ShowForwarding (flow process virtual emulation) instrument is set also, this instrument can directly extract virtual chip emulation result to be tested, and compares with the emulation of the computer software result, and then the part that do not match of quick positioning design and realization.
At least 24 Ethernet interfaces are set on the described Network Interface Module.
Described Network Interface Module also is connected with at least one expansion board, and the Ethernet interface more than 48 is set on this expansion board.
Described hardware system is arranged on the printed circuit board (PCB), and described printed circuit board (PCB) is more than three, and it stacks setting each other, and on each printed circuit board (PCB) at least 24 Ethernet interfaces is set all.
The FPGA debugging acid also is set in the described hardware system, and this FPGA debugging acid can extract fpga logic service data in the analogue system, thus orientation problem.
A kind of software and hardware cooperating simulation verification method based on FPGA is characterized in that this method is:
Controlling platform Control Network tester by network tester produces the test and excitation signal, and this controlling platform is arranged in user PC end or the work station;
Network Interface Module acceptance test pumping signal in the hardware system part, and the interface conversion logic module of delivering FPGA inside is converted to and the corresponding data-signal of virtual chip operating frequency;
Virtual chip to be tested receives data-signal and carries out simulation calculating, operation result is after the conversion of interface conversion logic module, send to the controlling platform of network tester again through Network Interface Module, carry out interpretation of result by network tester and/or user PC end or work station;
According to analysis result, software systems partly determine next step test target, and repeat above-mentioned steps, to the simulating, verifying of finishing whole chip to be tested.
This method is specially:
According to test request definition test and excitation signal format, compile script language, Control Network tester produce corresponding test and excitation signal on the controlling platform of network tester.The test and excitation signal sends to the Network Interface Module of hardware system part by the interface of network tester;
After Network Interface Module receives the test and excitation signal of network tester transmission, send the data to FPGA, interface conversion logic module in the FPGA receives this data, carry out corresponding rate-matched, send the data to the chip virtual to be tested in the FPGA at last, chip to be tested carries out corresponding simulation calculating, and final result is returned to network tester by interface conversion logic module and Network Interface Module again, carries out analytical test;
Interpretation of result software in the network tester is analyzed the analytical test result, the analysis result of the software systems extracting section network tester on PC or the work station, carry out analyzing synchronously and further, according to the final analysis result, software systems partly determine next step test target;
Repeat above-mentioned steps, until the simulating, verifying of finishing whole chip to be tested.
The present invention can obtain following beneficial effect:
One, the proving time is saved in high-speed simulation.The emulation module of this system is based on the devices at full hardware environment of FPGA, and all functions of chip to be measured and performance test can both be carried out emulation with the speed of FPGA, and large-scale regression test also can be finished at short notice, has reduced the time of checking greatly.
Two, full chip global function checking.This system not only can emulation chip to be measured the repertoire logic, more can directly dock with network tester and other network equipments, whole system is used as actual chip to be connected in the target application system, proofing chip function in real applied environment, thereby also realized the synchronous of software debugging and chip checking, shortened the time of later stage system development greatly.
Three, support the polytype chip checking.Though optimal design has been done to the emulation of network exchanging chip by this system, but by hardware system FPGA being write different interface conversion (Shim) logic, can realize the function corresponding conversion, the results analyses module of cooperation software section can realize the high-speed simulation to the other types chip.
Four, good physics extensibility.Veneer can provide 24 10/100M network interfaces, and by the additional extension plate, single board interface can reach 48; Can realize that at most three sheetpiles change, not only expand the capacity of system, more can make system's external interface extend to 72; FPGA on the veneer can replace with the more jumbo FPGA of compatibility encapsulation, realizes that easily the system emulation capacity is double.
Five, good debugging acid.
A) ShowForwarding instrument: in other analogue system, the result of software emulation can't be directly and the chip emulation result compare, but in this analogue system, by the ShowForwarding instrument, can directly extract the result of chip emulation on the analogue system and compare with the result of emulation of the computer software, moment just can positioning design and the part that do not match of realization;
B) FPGA debugging acid: can extract fpga logic service data in the analogue system, with RTL emulation mode orientation problem equally easily.
Description of drawings
Fig. 1 is based on the structured flowchart of the software and hardware co-emulation verification system of FPGA in the embodiment of the invention.
Fig. 2 is based on the hardware system structure schematic diagram in the software and hardware co-emulation verification system of FPGA in the embodiment of the invention.
Fig. 3 is based on the structural representation of the interface conversion logic module of the hardware system in the software and hardware co-emulation verification system of FPGA in the embodiment of the invention.
Fig. 4 is for utilizing the flow chart that carries out the step 1 of simulating, verifying based on the software and hardware co-emulation verification system of FPGA in the embodiment of the invention.
Fig. 5 is for utilizing the flow chart that carries out the step 2 of simulating, verifying based on the software and hardware co-emulation verification system of FPGA in the embodiment of the invention.
Fig. 6 is for utilizing the flow chart that carries out the step 3 of simulating, verifying based on the software and hardware co-emulation verification system of FPGA in the embodiment of the invention.
Embodiment
Below in conjunction with the drawings and the specific embodiments, technical scheme of the present invention is further elaborated.
With reference to figure 1, Fig. 2 and Fig. 3, Fig. 1 have shown in the embodiment of the invention software and hardware co-emulation verification system based on FPGA; Fig. 2 has shown in the embodiment of the invention structure based on hardware system in the software and hardware co-emulation verification system of FPGA; Fig. 3 has shown in the embodiment of the invention logical construction based on the interface conversion (Shim) of the hardware system in the software and hardware co-emulation verification system of FPGA.
As depicted in figs. 1 and 2, should comprise two parts based on the software and hardware co-emulation verification system of FPGA: software systems part 1 and hardware system part 2.The software systems part mainly is meant controlling platform, embedded system interface module, the ShowForwarding debugging acid of network tester, and the software section of FPGA debugging acid; The hardware system part mainly comprises Shim logic 23 and the interior virtual chip of realizing 24 of FPGA in cpu i/f module 21, Network Interface Module 22, the FPGA.
As shown in Figure 3, the test and excitation signal is produced by the network tester 3 of PC or work station (wherein comprising software systems part 1) control, Network Interface Module 22 by network tester 3 and hardware system part 2 is directly inputted to hardware system part 2, the Network Interface Module 22 of hardware system part 2 receives the test and excitation signal of tester 3, Shim logic 23 by FPGA inside is transformed into the operating frequency of virtual chip 24 with it, virtual chip 24 just begins to receive these data and carries out simulation calculating, final result by sending to tester 3 after 23 conversions of Shim logic, carries out interpretation of result by tester 3 and user PC again.
The basic thought that utilizes this software and hardware co-emulation verification system based on FPGA to carry out simulating, verifying is: realize a virtual chip of equal value fully with the DUT logic function on hardware system, abundant 10/100M Ethernet interface (24 of veneers are provided, can reach 48 behind the additional extension plate, three sheetpiles repeatedly more can reach 72), in order to coupling DUT network interface and external testing instrument or other network interfaces.These interfaces can directly dock with the Ethernet interface of network tester or other network switching equipment, not only saved the trouble of interface conversion, reduced the difficulty of simulating, verifying conceptual design, improved simulation performance, more can be used as actual chip to whole system is connected in the target application system, proofing chip function in real applied environment, thus the integrality and the validity of functional verification improved greatly.Its verifying speed can reach hundreds of KHz to several megahertzes.Owing to can directly dock with network testing instrument, the work of man-machine interaction can be finished by network tester fully, does not have the disagreeableness problem of man-machine interaction.Simultaneously, because ready-made application platform has been arranged, the user can also promptly begin exploitation and debugging software before throwing sheet, carry out software and hardware combined checking.
Described emulation/the proof procedure of present embodiment mainly comprises three steps, and concrete step is with reference to figure 4, Fig. 5 and Fig. 6.Fig. 4 has shown and has utilized the flow process of carrying out the step 1 of emulation/checking based on the software and hardware co-emulation verification system of FPGA in the present embodiment; Fig. 5 has shown and has utilized the flow process of carrying out the step 2 of emulation/checking based on the software and hardware co-emulation verification system of FPGA in the present embodiment; Fig. 6 has shown and has utilized the flow process of carrying out the step 3 of emulation/checking based on the software and hardware co-emulation verification system of FPGA in the present embodiment.
Step 1: 1 control of software systems part produces input stimulus.Its handling process as shown in Figure 4.
According to test request definition test and excitation signal format, the compile script language, Control Network tester 3 produces corresponding test and excitation signal.The interface of test and excitation signal by tester 3 sends to the Network Interface Module 22 on the hardware system part 2.
Step 2: hardware system part 2 receives excitation, and the output response.Its handling process as shown in Figure 5.
The Network Interface Module 22 of hardware system part 2 sends the data to FPGA after receiving the test and excitation signal of tester 3 transmissions.Shim logic 23 in the FPGA receives these data, carries out corresponding rate-matched, sends the data to the chip to be measured (DUT) in the FPGA at last.DUT carries out corresponding simulation calculating, and final result is returned to network tester 3 by Shim logic 23 again.
Step 3: network tester 3 and software systems part 1 receive and analyzing responding, and its handling process as shown in Figure 6.
The response results of hardware system part 2 sends to network tester 3 by Network Interface Module 22, tester interpretation of result software is analyzed the result, software systems part 1 on PC or the work station is extracted the result of tester 3, carries out analyzing synchronously and further.According to final analysis result, software systems part 1 determines next step test target.
Step 4: repeating step 1 is to step 3, until emulation/checking of finishing whole DUT.
Need to prove that the hardware system part 2 of present embodiment also provides the network interface of a CPU, the excitation of network exchanging chip to be measured and result also can by this interface directly and software systems part 1 transmit.When handling than low rate as a result, whole simulation is finished in the participation that can need not network tester.In addition,, so, only need to carry out corresponding modification, just can carry out emulation and checking producing the software section relevant with interpretation of result with the test and excitation signal if chip to be measured is not a network exchanging chip.
The foregoing description only is explanation technical conceive of the present invention and characteristics, and its purpose is to allow the personage who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.All equivalences that spirit is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.
Claims (10)
1. software and hardware co-emulation verification system based on FPGA, comprise network tester, be arranged at software systems part in the user PC end and the hardware system part that integrated circuit (IC) chip is simulated, software systems partly comprise the controlling platform and the embedded system interface module of network tester, hardware system partly comprises the cpu i/f module, the chip of realizing in interface conversion logic module in the FPGA and the FPGA virtual to be tested, it is characterized in that, described hardware system also comprises Network Interface Module, and this Network Interface Module can be realized the data interaction between the controlling platform of interface conversion logic module and network tester.
2. a kind of software and hardware co-emulation verification system according to claim 1 based on FPGA, it is characterized in that, in the described software systems part flow process virtual emulation instrument is set also, this instrument can directly extract virtual chip emulation result to be tested, and compare, and then the part that do not match of positioning design and realization fast with the emulation of the computer software result.
3. a kind of software and hardware co-emulation verification system based on FPGA according to claim 1 is characterized in that, at least 24 Ethernet interfaces are set on the described Network Interface Module.
4. according to claim 1 or 3 described a kind of software and hardware co-emulation verification system, it is characterized in that described Network Interface Module also is connected with at least one expansion board, can realize the Ethernet interface more than 48 based on FPGA.
5. a kind of software and hardware co-emulation verification system according to claim 1 based on FPGA, it is characterized in that, described hardware system is arranged on the printed circuit board (PCB), and described printed circuit board (PCB) can maximum three sheetpiles stacks to be put, and 24 Ethernet interfaces all are provided on each printed circuit board (PCB).
6. a kind of software and hardware co-emulation verification system according to claim 1 based on FPGA, it is characterized in that, the FPGA debugging acid also is set in the described hardware system, and this FPGA debugging acid can extract fpga logic service data in the analogue system, thus orientation problem.
7. software and hardware cooperating simulation verification method based on FPGA is characterized in that this method is:
Controlling platform Control Network tester by network tester produces the test and excitation signal, and this controlling platform is arranged in user PC end or the work station;
Network Interface Module acceptance test pumping signal in the hardware system part, and the interface conversion logic module of delivering FPGA inside is converted to and the corresponding data-signal of virtual chip operating frequency;
Virtual chip to be tested receives data-signal and carries out simulation calculating, operation result is after the conversion of interface conversion logic module, send to the controlling platform of network tester again through Network Interface Module, carry out interpretation of result by network tester and/or user PC end or work station;
According to analysis result, software systems partly determine next step test target, and repeat above-mentioned steps, to the simulating, verifying of finishing whole chip to be tested.
8. the software and hardware cooperating simulation verification method based on FPGA according to claim 7 is characterized in that this method is specially:
According to test request definition test and excitation signal format, compile script language, Control Network tester produce corresponding test and excitation signal on the controlling platform of network tester.The test and excitation signal sends to the Network Interface Module of hardware system part by the interface of network tester;
After Network Interface Module receives the test and excitation signal of network tester transmission, send the data to FPGA, interface conversion logic module in the FPGA receives this data, carry out corresponding rate-matched, send the data to the chip virtual to be tested in the FPGA at last, chip to be tested carries out corresponding simulation calculating, and final result is returned to network tester by interface conversion logic module and Network Interface Module again, carries out analytical test;
Interpretation of result software in the network tester is analyzed the analytical test result, the analysis result of the software systems extracting section network tester on PC or the work station, carry out analyzing synchronously and further, according to the final analysis result, software systems partly determine next step test target;
Repeat above-mentioned steps, until the simulating, verifying of finishing whole chip to be tested.
9. the software and hardware cooperating simulation verification method based on FPGA according to claim 8, it is characterized in that, software systems on described PC or the work station are partly extracted the interior partial results of hardware simulation system by flow process virtual emulation instrument, and it is compared with the emulation of the computer software result, with the part that do not match of quick positioning design and realization.
10. the software and hardware cooperating simulation verification method based on FPGA according to claim 7, it is characterized in that, described Network Interface Module also is connected with at least one expansion board, Ethernet interface more than 48 is set on this expansion board, described hardware system is arranged on the printed circuit board (PCB), described printed circuit board (PCB) can maximum three sheetpiles stacks to be put, and 24 Ethernet interfaces all are provided on each printed circuit board (PCB).
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