CN116028292A - Simulation verification system and method for remote direct memory access simulation verification - Google Patents
Simulation verification system and method for remote direct memory access simulation verification Download PDFInfo
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Abstract
The application provides a simulation verification system and a simulation verification method for remote direct memory access simulation verification. The system comprises: the design to be tested is used for providing remote direct memory access hardware logic; the simulator is used for simulating an operating system to run remote direct memory access software and providing simulation equipment, the remote direct memory access software is used for simulating software and hardware interactions associated with remote direct memory access hardware logic, and the simulation equipment is used for interacting with the design to be tested so as to perform simulation verification of the remote direct memory access hardware logic in cooperation with the design to be tested; and the network card is used for interacting with the design to be tested to realize the network card interoperation test. The system generates a joint simulation verification result of the remote direct memory access hardware logic and the remote direct memory access software based on the observation results of the simulator and the network card. Therefore, the software and hardware interaction problem can be found and the verification efficiency can be improved by carrying out verification together with the software in the logic verification process.
Description
Technical Field
The application relates to the technical field of computers, in particular to the technical field of Internet, and especially relates to a simulation verification system and method for remote direct memory access simulation verification.
Background
Remote direct memory access (Remote Direct Memory Access, RDMA) refers to direct access from the memory of one computer to the memory of another computer, without involving either party's operating system in the process. RDMA technology is applied to the related field of computer networks, realizes a high-throughput and low-delay network, and is beneficial to building a massive parallel computer cluster. The basic working principle of RDMA is that data is directly copied from a physical line to a memory of an application program through a network adapter, or the data is directly copied from the memory of the application program to the physical line, in the process, the data is not required to be copied between the memory of the application program and a data buffer zone of an operating system, so that the data transmission does not occupy resources and cache of a central processing unit (central processing unit, a CPU), context switching is not involved, and the like, and the data transmission and other system operations can be performed in parallel. Network adapters supporting RDMA technology, such as network interface cards (Network Interface Card, NIC) or network cards, etc., have different hardware implementations and may also support different network protocols. Thus, the RDMA technology-based product solution often considers both hardware implementation details and software drivers, such as providing support for RDMA core protocol stacks at the software level and providing an optimal design at the hardware level.
Functional verification of chip design is helpful for verifying whether chip design meets requirements such as correctness of logic time sequence before chip production, and is beneficial for improving stream efficiency and development efficiency. However, in the prior art, RDMA software driver and RDMA logic validation are separately test validated. Moreover, RDMA software cannot participate in logic verification before RDMA logic verification is completed; and in the logic verification process, the verification can not be performed together with the software. Therefore, the method is not beneficial to discovering the interaction problem of software and hardware in advance and is also not beneficial to improving the verification efficiency.
Based on the technical problems in the prior art, a simulation verification system and a method for remote direct memory access simulation verification are provided, which are used for solving the problems in the prior art.
Disclosure of Invention
The embodiment of the application provides a simulation verification system and a simulation verification method for remote direct memory access simulation verification, which are used for solving the problems in the prior art.
In a first aspect, the present application provides a emulation verification system for remote direct memory access emulation verification. The simulation verification system comprises: the design to be tested is used for providing remote direct memory access hardware logic; a simulator for simulating an operating system to run remote direct memory access software for simulating software and hardware interactions associated with the remote direct memory access hardware logic and providing at least one simulation device for interacting with the design to be tested to perform simulated verification of the remote direct memory access hardware logic in coordination with the design to be tested; and the network card is used for interacting with the design to be tested to realize the network card interoperation test. And the simulation verification system generates a joint simulation verification result of the remote direct memory access hardware logic and the remote direct memory access software based on the observation results of the simulator and the network card.
According to the first aspect of the application, the joint simulation verification result of the remote direct memory access hardware logic and the remote direct memory access software is achieved, so that verification can be performed together with the software in the logic verification process, the software and hardware interaction problems, the software problems, the hardware problems and the problems in the logic are found in time and corrected, and the verification efficiency is improved.
In a possible implementation manner of the first aspect of the present application, the observation result includes an interaction feature between the design to be tested and the network card and feedback received by the simulator from the design to be tested.
In a possible implementation manner of the first aspect of the present application, the simulation verification system generates an excitation signal through the remote direct memory access software simulation, and generates the joint simulation verification result by comparing the observation result with a reference observation result corresponding to the excitation signal.
In a possible implementation form of the first aspect of the present application, the incentive signal is based on product delivery requirements and user preferences.
In a possible implementation manner of the first aspect of the present application, the joint simulation verification result includes a simulation verification result of the remote direct memory access hardware logic and a correctness verification result of the remote direct memory access software.
In a possible implementation manner of the first aspect of the present application, the joint simulation verification result is used to locate and repair errors in the remote direct memory access hardware logic and the remote direct memory access software.
In a possible implementation manner of the first aspect of the present application, the emulator is a fast emulator, the network card is a standard remote direct memory access network card, and the standard remote direct memory access message is transmitted between the design to be tested and the standard remote direct memory access network card.
In a possible implementation manner of the first aspect of the present application, the at least one simulation device is configured to interact with the design to be tested to perform simulation verification of the remote direct memory access hardware logic in coordination with the design to be tested, including: the at least one simulation device cooperates with the design to be tested for at least one of: direct memory access operation, interrupt operation, base address register space read-write and shortcut peripheral interconnection standard equipment configuration space read-write.
In a possible implementation manner of the first aspect of the present application, the at least one simulation device includes one or more shortcut peripheral interconnection standard devices for performing configuration space reading and writing of the shortcut peripheral interconnection standard device in coordination with the design to be tested.
In a possible implementation manner of the first aspect of the present application, the at least one simulation device includes one or more storage media for performing the direct memory access operation in coordination with the design to be tested.
In a possible implementation manner of the first aspect of the present application, the interaction between the at least one simulation device and the design to be tested is implemented by a transmission control protocol socket.
In a possible implementation manner of the first aspect of the present application, the base address register space read-write and the shortcut interconnect standard device configuration space read-write are implemented by a configuration parameter socket, and the direct memory access operation and the interrupt operation are implemented by a direct memory access socket.
In a possible implementation manner of the first aspect of the present application, the design to be tested is configured to parse the data packets of the configuration parameter socket and the direct memory access socket, and the design to be tested is further configured to send a remote direct memory access message to the network card through a message socket and receive a message from the network card through the message socket.
In a possible implementation manner of the first aspect of the present application, the simulator processes the message from the design to be tested through the direct memory access socket and uploads the processing result through the remote direct memory access software.
In a possible implementation manner of the first aspect of the present application, the simulation verification system further includes: the first adaptation module is used for converting interaction between the design to be tested and the at least one simulation device into input and output of a design format to be tested; and the second adapting module is used for converting interaction between the design to be tested and the network card into input and output of the design format to be tested. The first adaptation module, the second adaptation module and the design to be tested together form a logic verification platform.
In a possible implementation manner of the first aspect of the present application, the emulation verification system is a remote direct memory access emulation verification system, and the joint emulation verification result generated by the remote direct memory access emulation verification system is a remote direct memory access software and hardware joint emulation verification result.
In a possible implementation manner of the first aspect of the present application, the remote direct memory access hardware logic provided by the design to be tested corresponds to a logic function of a remote direct memory access chip, where the remote direct memory access chip is a field programmable gate array chip or an application specific integrated circuit chip or a data processor.
In a second aspect, the present application provides a method for emulation verification for remote direct memory access emulation verification. The simulation verification method comprises the following steps: providing remote direct memory access hardware logic through the design to be tested; simulating, by an emulator, an operating system to run remote direct memory access software for emulating software-hardware interactions associated with the remote direct memory access hardware logic and to provide at least one emulation device for interacting with the design to be tested to perform emulation verification of the remote direct memory access hardware logic in coordination with the design to be tested; interaction with the design to be tested is carried out through a network card so as to realize network card interoperation test; and generating a joint simulation verification result of the remote direct memory access hardware logic and the remote direct memory access software based on the observation results of the simulator and the network card.
In a possible implementation manner of the second aspect of the present application, the observation result includes an interaction feature between the design to be tested and the network card and feedback from the design to be tested received by the simulator, and the simulation verification method further includes: generating an excitation signal by the remote direct memory access software simulation, and generating the joint simulation verification result by comparing the observation with a reference observation corresponding to the excitation signal.
In a possible implementation manner of the second aspect of the present application, the at least one simulation device is configured to interact with the design to be tested so as to perform simulation verification of the remote direct memory access hardware logic in coordination with the design to be tested, including: the at least one simulation device cooperates with the design to be tested for at least one of: direct memory access operation, interrupt operation, base address register space read-write and shortcut peripheral interconnection standard equipment configuration space read-write.
In a third aspect, embodiments of the present application further provide a computer device, where the computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements a method according to any implementation manner of any one of the foregoing aspects, when the processor executes the computer program.
In a fourth aspect, embodiments of the present application also provide a computer-readable storage medium storing computer instructions that, when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.
In a fifth aspect, embodiments of the present application also provide a computer program product comprising instructions stored on a computer-readable storage medium, which when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of remote direct memory access logic verification based on a reference model;
FIG. 2 is a schematic diagram of a simulation verification system for remote direct memory access simulation verification according to an embodiment of the present application;
FIG. 3 is a schematic flow chart of a simulation verification method for remote direct memory access simulation verification according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a computing device according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
The embodiment of the application provides a simulation verification system and a simulation verification method for remote direct memory access simulation verification, which are used for solving the problems in the prior art. The method and the device provided in the embodiments of the present application are based on the same inventive concept, and because the principles of solving the problems by the method and the device are similar, the embodiments, implementations, examples or implementation of the method and the device may refer to each other, and the repetition is not repeated.
It should be understood that in the description of this application, "at least one" means one or more than one, and "a plurality" means two or more than two. In addition, the words "first," "second," and the like, unless otherwise indicated, are used solely for the purposes of description and are not to be construed as indicating or implying a relative importance or order.
FIG. 1 is a schematic diagram of remote direct memory access logic verification based on a reference model. As shown in fig. 1, stimulus signal generator 102 is used to generate a stimulus signal and send the same stimulus signal to reference model (ReferenceModel, RM) 110 and design under test (Design under Test, DUT) 120, respectively. The output of each of the reference model 110 and the design under test 120 is sent to the comparator 104 for comparison. Before chip production, it is necessary to verify whether the chip design meets the preset requirements and meets the logic timing correctness, and thus, it is necessary to perform functional verification on the chip design, for example, on a module or system related design representing one or more functions of the chip. The design under test 120 in FIG. 1 represents RDMA logic under test in an application scenario where remote direct memory Access (Remote DirectMemory Access, RDMA) logic verification is performed. RDMA, herein, refers to direct access from the memory of one computer to the memory of another computer, without involving either side of the operating system. The reference model 110 is a module that has the same logic function as the design to be tested 120 is expected to perform, by letting the stimulus signal generator 102 construct the same stimulus input to the reference model 110 and the design to be tested 120, and then checking the output results from the reference model 110 and the design to be tested 120, respectively, by the comparator 104, the whole logic verification process is completed. The RDMA logic to be tested represented by the design under test 120 generally corresponds to RDMA logic functions provided on a chip or an integrated circuit design for supporting RDMA. Therefore, after the process of remote direct memory access logic verification based on the reference model in fig. 1 is finished, the process further needs to be integrated and generate a layout through a compiler or a design tool, and then a chip with RDMA logic function is manufactured by a foundry, or a chip with programming function such as field-programmable gate array (FPGA) is implemented in hardware, and then the debug test can be performed together with related RDMA driving software. Therefore, the method for performing remote direct memory access simulation verification based on the reference model, such as remote direct memory access logic verification based on the reference model shown in fig. 1, needs to separately construct a verification environment to verify RDMA logic and perform testing together with RDMA driver software on the basis of hardware implementation, which means that RDMA software driver and RDMA logic verification are separately tested and verified. Moreover, RDMA software cannot participate in logic verification before RDMA logic verification is completed; and in the logic verification process, the verification can not be performed together with the software. Therefore, the method is not beneficial to discovering the interaction problem of software and hardware in advance and is also not beneficial to improving the verification efficiency. In addition, the stimulus signal generator 102 needs to construct a large number of stimulus signals as stimulus inputs to test RDMA logic, and input signals simulated by the stimulus inputs are originally transferred from software to hardware logic in the application scenario of RDAM, so that common software-hardware interaction applications in the application scenario of RDMA are not fully utilized to improve verification effects. How the above challenges are addressed by a system and method for remote direct memory access emulation verification provided herein is described in detail below in conjunction with the embodiments of fig. 2 and 3.
Fig. 2 is a schematic diagram of a simulation verification system for remote direct memory access simulation verification according to an embodiment of the present application. As shown in fig. 2, the simulation verification system includes: design to be tested 220 for providing remote direct memory access hardware logic; a simulator 202 for simulating an operating system to run remote direct memory access software 204 and providing at least one simulation device 210, wherein the remote direct memory access software 204 is for simulating software and hardware interactions associated with the remote direct memory access hardware logic, and the at least one simulation device 210 is for interacting with the design under test 220 to perform simulated verification of the remote direct memory access hardware logic in coordination with the design under test 220; and a network card 201 for interacting with the design to be tested 220 to realize network card interoperability test. Wherein the emulation verification system generates a joint emulation verification result of the remote direct memory access hardware logic and the remote direct memory access software based on the observation results of the emulator 202 and the network card 201. Here, the observation results of the emulator 202 and the network card 201 may include feedback data and observed waveforms. The Emulator 202 may be a Quick Emulator (QEMU) or other suitable virtualized Emulator for emulating a hardware device and running a computer system to implement an emulated operating system to run remote direct memory access software 204 and to provide at least one emulated device 210. The emulator 202 shown in fig. 2 runs a client operating system (not shown) on which remote direct memory access software 204 is then run. In addition, the simulation device 210 shown in FIG. 2 represents at least one simulation device provided by the simulator 202 that interacts with the design under test 220 and is used to simulate various devices that may exist in actual applications that interact with the remote direct memory access hardware logic represented by the design under test 220, such as a peripheral interconnect express (peripheral component interconnect express, PCIE) device. The number and type of analog devices 210 that simulator 202 can provide may be set according to actual needs, so that analog device 210 represents one or more analog devices. It should be appreciated that in some embodiments, the network card 201 is provided separately from the emulator 202 and the design to be tested 220, and the network card 201 may be a physical network card or a virtual network card such as a virtual network card emulated by a data processor (dataprocessing unit, DPU). The remote direct memory access hardware logic provided by the design under test 220 may be used for logic verification, e.g., the design under test 220 may represent RDMA logic to be tested such as RDMA logic functions on a chip or an integrated circuit design for RDMA support; the remote direct memory access software 204 is used to simulate the software and hardware interactions associated with the remote direct memory access hardware logic, so the remote direct memory access software 204 can be used for RDMA software driven emulation verification; in addition, the simulation verification system shown in fig. 2 generates the joint simulation verification result of the remote direct memory access hardware logic and the remote direct memory access software based on the observation results of the simulator 202 and the network card 201, so that the collaborative software verification in the logic verification process is realized, the problem in the aspect of software-hardware interaction is found, and a factory is not required to manufacture a chip or realize the joint simulation verification by using FPGA hardware, thereby being beneficial to improving the verification efficiency; in addition, the simulation verification system shown in fig. 2 interacts with the design to be tested 220 through the network card 201 to implement the network card interoperation test, so that the verification environment can be flexibly changed by configuring network cards with different types and different standards, and the verification efficiency is further improved. In some embodiments, the network card 201 and remote direct memory access software 204 may be enabled to support various RDMA network protocols, such as InfiniBand (IB) network protocols, ethernet-based RDMA (RDMA over Ethernet, roCE) protocols, internet wide area RDMA (iWARP) protocols, by changing the relevant configuration and parameters of the network card 201 and remote direct memory access software 204 shown in FIG. 2. Thus, the emulation verification system shown in fig. 2 can switch between different verification environments, for example, the verification environments of the corresponding RDMA protocol are provided according to actual needs, so that remote direct memory access emulation verification is better provided. In addition, the remote direct memory access software 204 can conveniently construct stimulus inputs for remote direct memory access simulation verification, and then the stimulus inputs are transmitted to hardware logic by software, namely, the stimulus inputs are transmitted to the design to be tested 220 through the simulator 202, so that no additional stimulus signal generator is needed to construct a stimulus signal, no additional reference model is needed, and software and hardware interaction application in an RDMA application scene can be fully utilized to improve verification effect.
In summary, the simulation verification system shown in fig. 2 realizes the joint simulation verification result of the remote direct memory access hardware logic and the remote direct memory access software 204, so that the verification can be performed together with the software in the logic verification process, which is beneficial to timely finding out and correcting the software-hardware interaction problem and improving the verification efficiency.
In one possible implementation, the observations include interaction characteristics between the design under test 220 and the network card 201 and feedback received by the simulator 202 from the design under test 220. In this way, by observing the interaction characteristics and the feedback received by the simulator 202, the verification is performed together with the software in the logic verification process, which is beneficial to timely finding and correcting the software-hardware interaction problem and improving the verification efficiency. In some embodiments, the simulation verification system simulates generating an excitation signal by the remote direct memory access software 204 and generates the joint simulation verification result by comparing the observation to a reference observation corresponding to the excitation signal. In this way, the remote direct memory access software 204 can conveniently construct the excitation input for remote direct memory access simulation verification, so that an excitation signal is not required to be additionally constructed through an excitation signal generator, an additional reference model is not required, and the software and hardware interactive application in the RDMA application scene can be fully utilized to improve the verification effect. In some embodiments, the incentive signal is based on product delivery requirements and user preferences. The product delivery requirements here may include the intended objectives of the chip design, such as the logic functions to be implemented, the index parameters to be achieved, etc., and thus facilitate the flexible provision of a corresponding verification environment for the specific needs. In some embodiments, the joint simulation verification results include a simulation verification result of the remote direct memory access hardware logic and a correctness verification result of the remote direct memory access software 204. This achieves both verification of the functionality of the hardware logic and verification of the correctness of the software. In some embodiments, the co-simulation verification results are used to locate and repair errors in the remote direct memory access hardware logic and the remote direct memory access software 204. By observing results such as waveform and data feedback, the method can realize quick error positioning and repair, and is beneficial to early finding out problems of software and hardware interaction, software problems, hardware problems and logic inside.
In one possible implementation, the emulator 202 is a fast emulator, the network card 201 is a standard remote direct memory access network card, i.e., a standard RDMA network card, and standard remote direct memory access messages, i.e., standard RDMA messages, are transmitted between the design to be tested 220 and the standard remote direct memory access network card. It should be understood that other types of emulators and other types of network cards and messages may be used. Thus helping to flexibly provide a verification environment according to requirements.
In one possible implementation, the at least one simulation device (represented in fig. 2 by simulation device 210) is configured to interact with the design under test 220 to perform a simulation verification of the remote direct memory access hardware logic in coordination with the design under test 220, including: the at least one simulation device cooperates with the design to be tested 220 for at least one of: direct memory access (Direct Memory Access, DMA) operations, interrupt operations, base address register (Base Address Register, BAR) space read and write, and shortcut interconnect standard device configuration space read and write. Herein, a direct memory access operation refers to copying data from one address space to another address space for data transfer, and may be used for high-speed data transfer between memories. The simulator 210 provided by the simulator 202 may perform DMA operations in conjunction with the design under test 220 to simulate DMA operations associated with RDMA functions in actual use. The interrupt operation refers to that the RDMA network card is reported to an upper layer user by an interrupt event during running, for example, abnormal data packet receiving and sending or internal error occurs in the RDMA network card. In RDMA operation, the role of interrupt is generally embodied, for example, if the RDMA network card receives a data packet and the data packet is abnormal, notifying an upper layer user through reporting the interrupt; for another example, if some error occurs in the RDMA network card running process, the upper layer user is notified through the report interrupt; for another example, an interrupt event set by an upper user and requiring the RDMA network card to report may be normal or abnormal. The simulation device 210 provided by the simulator 202 may perform interrupt operations in conjunction with the design under test 220 to simulate RDMA function related interrupt events, interrupt patterns, interrupt operations, etc. in actual applications. The base address register space read-write is also called BAR space read-write, and refers to the read-write operation performed on the base address register space. The base address register is a register for storing a base address, and the base address and the relative address are added to obtain a real address when the base address register is executed. In RDMA related practical applications, in terms of memory address application, it is necessary to identify a device memory address by means of a base address register, for example, by indicating a base address of a PCIE device in a PCIE address space by data stored in the base address register, and then obtaining the device memory address of the PCIE device by using a mapping relationship. The simulator 210 provided by the simulator 202 may cooperate with the design under test 220 to perform base address register space read and write to simulate read and write operations, mapping relationships, mapping functions, etc. associated with the base address register space for RDMA functions in actual applications. The read-write of the PCI express device configuration space, namely the read-write of the PCI express device configuration space, refers to the read-write operation of the PCI express device configuration space. The PCIE device configuration space is a configuration space (Configuration Space) corresponding to PCIE device functions. The simulator 210 provided by the simulator 202 may cooperate with the design to be tested 220 to perform the shortcut interconnect standard device configuration space read-write so as to simulate the RDMA function in actual application and related to the configuration space of the PCIE device.
In some embodiments, the at least one simulation device includes one or more shortcut interconnection standard devices for reading and writing the shortcut interconnection standard device configuration space in coordination with the design under test 220. In some embodiments, the at least one simulation device includes one or more storage media for performing the direct memory access operation in conjunction with the design under test 220. Storage media are understood herein to include the category of memory, such as main memory or RAM, e.g., DDR memory banks, also known as double rate synchronous dynamic random access memory, etc. Direct access of the RDMA network card to the memory of the host generally reads and writes to the memory of the host. Exemplary storage media include, for example, DDR or solid state disk (Solid State Driver, SSD).
In one possible implementation, the interaction between the at least one analog device and the design under test 220 is implemented by a transmission control protocol socket (TCP socket). Here, the transmission control protocol (Transmission Control Protocol, TCP) refers to a connection-oriented transport layer protocol, and in RDMA-related applications, a network based on the TCP/IP protocol may be constructed, and RDMA may be enabled to operate on top of the network, so as to implement multiple transmission types to share the same physical connection, and may implement message communication between networks, file systems, block memories, and processors, for example. Socket refers to the convention or manner in which communications are made between computers. Receiving data from or sending data to other computers may be accomplished through sockets. A socket typically has a specific data structure and indicates the type of connection and the protocol used to identify the packet's home. In some embodiments, the transmission control protocol socket includes a particular data structure, such as a quad, and indicates the IP address and interface of the source and the IP address and interface of the destination of the data packet. In some embodiments, the base address register space read-write and the shortcut interconnect standard device configuration space read-write are implemented by a configuration parameter socket (CFG socket) 212, and the direct memory access operation and the interrupt operation are implemented by a direct memory access socket (DMA socket) 214. Here, configuration parameter socket 212 and direct memory access socket 214 represent the manner in which data is received and transmitted, respectively, as defined for enabling corresponding device interactions and operations. In some embodiments, configuration parameter socket 212 and direct memory access socket 214 may both belong to a transmission control protocol socket (not shown). In some embodiments, the design under test 220 is configured to parse the data packets of the configuration parameter socket 212 and the direct memory access socket 214, and the design under test 220 is further configured to send a remote direct memory access message to the network card 201 through a packet socket (packet socket) and receive a message from the network card 201 through the packet socket. In some embodiments, the emulator 202 processes messages from the design under test 220 through the direct memory access socket 214 and uploads processing results through the remote direct memory access software 204. In this manner, messaging between the emulator 202, the design to be tested 220, and the network card 201 is achieved by defining a variety of sockets.
In one possible implementation, the simulation verification system further includes: a first adaptation module 222, configured to convert interactions between the design to be tested 220 and the at least one simulation device into input and output of a design to be tested format; a second adapting module 224, configured to convert interaction between the design to be tested 220 and the network card 201 into input and output of the design to be tested format. Wherein the first adaptation module 222, the second adaptation module 224 and the design under test 220 together constitute a logic verification platform 230. The message socket may be included in the second adaptation module 224, so that the design to be tested 220 sends a remote direct memory access message to the network card 201 through the message socket and receives a message from the network card 201 through the message socket is also completed through the second adaptation module 224. Alternatively, the second adaptation module 224 may be provided separately from the message socket. In this way, by the first adaptation module 222 and the second adaptation module 224, the construction logic verification platform 230 is implemented to verify RDMA logic represented by the design to be tested 220, and the emulator 202 and the network card 201 can be flexibly adapted, which is also beneficial to providing a more flexible verification environment.
In one possible implementation, the emulation verification system is a remote direct memory access emulation verification system, and the joint emulation verification result generated by the remote direct memory access emulation verification system is a remote direct memory access software and hardware joint emulation verification result. In one possible implementation, the remote direct memory access hardware logic provided by the design under test 220 corresponds to the logic function of a remote direct memory access chip, which is a field programmable gate array chip or an application specific integrated circuit chip or a data processor. Therefore, the software and hardware joint simulation verification of RDMA is realized, and the software and hardware interaction problem, the software problem, the hardware problem and the problem inside logic are found in the chip design stage.
Fig. 3 is a flow chart of a simulation verification method for remote direct memory access simulation verification according to an embodiment of the present application. As shown in fig. 3, the simulation verification method includes the following steps.
Step S302: remote direct memory access hardware logic is provided through the design to be tested.
Step S304: the operating system is emulated by the emulator to run remote direct memory access software and to provide at least one emulated device.
The remote direct memory access software is used for simulating software and hardware interaction associated with the remote direct memory access hardware logic, and the at least one simulation device is used for interacting with the design to be tested so as to cooperate with the design to be tested to perform simulation verification of the remote direct memory access hardware logic.
Step S306: and interacting with the design to be tested through the network card to realize the network card interoperation test.
Step S308: and generating a joint simulation verification result of the remote direct memory access hardware logic and the remote direct memory access software based on the observation results of the simulator and the network card.
The simulation verification method shown in fig. 3 realizes the joint simulation verification result of the remote direct memory access hardware logic and the remote direct memory access software 204, so that the verification can be performed together with the software in the logic verification process, which is beneficial to timely finding out and correcting the software-hardware interaction problem and improving the verification efficiency.
In a possible implementation manner, the observation result includes interaction characteristics between the design to be tested and the network card and feedback from the design to be tested received by the simulator, and the simulation verification method further includes: generating an excitation signal by the remote direct memory access software simulation, and generating the joint simulation verification result by comparing the observation with a reference observation corresponding to the excitation signal.
In one possible implementation, the at least one simulation device is configured to interact with the design to be tested to perform simulation verification of the remote direct memory access hardware logic in coordination with the design to be tested, including: the at least one simulation device cooperates with the design to be tested for at least one of: direct memory access operation, interrupt operation, base address register space read-write and shortcut peripheral interconnection standard equipment configuration space read-write.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a computing device provided in an embodiment of the present application, where the computing device 400 includes: one or more processors 410, a communication interface 420, and a memory 430. The processor 410, communication interface 420, and memory 430 are interconnected by a bus 440. Optionally, the computing device 400 may further include an input/output interface 450, where the input/output interface 450 is connected to an input/output device for receiving parameters set by a user, etc. The computing device 400 can be used to implement some or all of the functionality of the device embodiments or system embodiments described above in the embodiments of the present application; the processor 410 can also be used to implement some or all of the operational steps of the method embodiments described above in the embodiments of the present application. For example, specific implementations of the computing device 400 performing various operations may refer to specific details in the above-described embodiments, such as the processor 410 being configured to perform some or all of the steps of the above-described method embodiments or some or all of the operations of the above-described method embodiments. For another example, in the present embodiment, the computing device 400 may be configured to implement some or all of the functions of one or more components of the apparatus embodiments described above, and the communication interface 420 may be configured to implement communication functions and the like necessary for the functions of the apparatuses, components, and the processor 410 may be configured to implement processing functions and the like necessary for the functions of the apparatuses, components.
It should be appreciated that the computing device 400 of fig. 4 may include one or more processors 410, and that the processors 410 may cooperatively provide processing power in a parallelized connection, a serialized connection, a serial-parallel connection, or any connection, or that the processors 410 may constitute a processor sequence or processor array, or that the processors 410 may be separated into primary and secondary processors, or that the processors 410 may have different architectures such as heterogeneous computing architectures. In addition, the computing device 400 shown in FIG. 4, the associated structural and functional descriptions are exemplary and not limiting. In some example embodiments, computing device 400 may include more or fewer components than shown in fig. 4, or combine certain components, or split certain components, or have a different arrangement of components.
The processor 410 may have various specific implementations, for example, the processor 410 may include one or more of a central processing unit (central processingunit, CPU), a graphics processor (graphic processing unit, GPU), a neural network processor (neural-networkprocessing unit, NPU), a tensor processor (tensor processing unit, TPU), or a data processor (data processing unit, DPU), which are not limited in this embodiment. Processor 410 may also be a single-core processor or a multi-core processor. Processor 410 may be comprised of a combination of a CPU and hardware chips. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logicdevice, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complexprogrammable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL), or any combination thereof. The processor 410 may also be implemented solely with logic devices incorporating processing logic, such as an FPGA or digital signal processor (digital signal processor, DSP) or the like. The communication interface 420 may be a wired interface, which may be an ethernet interface, a local area network (local interconnect network, LIN), etc., or a wireless interface, which may be a cellular network interface, or use a wireless local area network interface, etc., for communicating with other modules or devices.
The memory 430 may be a nonvolatile memory such as a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically erasable programmable ROM (electricallyEPROM, EEPROM), or a flash memory. Memory 430 may also be volatile memory, which may be random access memory (randomaccess memory, RAM) used as external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (double data rate SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). Memory 430 may also be used to store program code and data such that processor 410 invokes the program code stored in memory 430 to perform some or all of the operational steps of the method embodiments described above, or to perform corresponding functions in the apparatus embodiments described above. Moreover, computing device 400 may contain more or fewer components than shown in FIG. 4, or may have a different configuration of components.
The bus 440 may be a peripheral component interconnect express (peripheralcomponent interconnect express, PCIe) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, a unified bus (Ubus or UB), a computer quick link (compute express link, CXL), a cache coherent interconnect protocol (cache coherentinterconnect for accelerators, CCIX), or the like. The bus 440 may be divided into an address bus, a data bus, a control bus, and the like. The bus 440 may include a power bus, a control bus, a status signal bus, and the like in addition to a data bus. But is shown with only one bold line in fig. 4 for clarity of illustration, but does not represent only one bus or one type of bus.
Embodiments of the present application also provide a system that includes a plurality of computing devices, where each computing device may have a structure that refers to the structure of the computing device described above. The functions or operations that may be implemented by the system may refer to specific implementation steps in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein. Embodiments of the present application also provide a computer-readable storage medium having stored therein computer instructions which, when executed on a computer device (e.g., one or more processors), may implement the method steps in the above-described method embodiments. The specific implementation of the processor of the computer readable storage medium in executing the above method steps may refer to specific operations described in the above method embodiments and/or specific functions described in the above apparatus embodiments, which are not described herein again. Embodiments of the present application also provide a computer program product comprising instructions stored on a computer-readable storage medium, which when run on a computer device, cause the computer device to perform the method steps in the method embodiments described above.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. The present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. The computer program product includes one or more computer instructions. When loaded or executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc. that contain one or more collections of available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, tape), optical media, or semiconductor media. The semiconductor medium may be a solid state disk, or may be a random access memory, flash memory, read only memory, erasable programmable read only memory, electrically erasable programmable read only memory, register, or any other form of suitable storage medium.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. Each flow and/or block of the flowchart and/or block diagrams, and combinations of flows and/or blocks in the flowchart and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the application can be sequentially adjusted, combined or deleted according to actual needs; the modules in the system of the embodiment of the application can be divided, combined or deleted according to actual needs. Such modifications and variations of the embodiments of the present application are intended to be included herein, if they fall within the scope of the claims and their equivalents.
Claims (22)
1. A simulation verification system for remote direct memory access simulation verification, the simulation verification system comprising:
the design to be tested is used for providing remote direct memory access hardware logic;
a simulator for simulating an operating system to run remote direct memory access software for simulating software and hardware interactions associated with the remote direct memory access hardware logic and providing at least one simulation device for interacting with the design to be tested to perform simulated verification of the remote direct memory access hardware logic in coordination with the design to be tested; and
A network card for interacting with the design to be tested to realize the network card interoperation test,
and the simulation verification system generates a joint simulation verification result of the remote direct memory access hardware logic and the remote direct memory access software based on the observation results of the simulator and the network card.
2. The simulation verification system of claim 1, wherein the observations comprise characteristics of interactions between the design under test and the network card and feedback received by the simulator from the design under test.
3. The simulation verification system of claim 2, wherein the simulation verification system simulates generation of an excitation signal by the remote direct memory access software and generates the joint simulation verification result by comparing the observation with a reference observation corresponding to the excitation signal.
4. The simulated verification system of claim 3, wherein the incentive signal is based upon product delivery requirements and user preferences.
5. The emulation verification system of claim 3 wherein the joint emulation verification result comprises an emulation verification result of the remote direct memory access hardware logic and a correctness verification result of the remote direct memory access software.
6. The emulation verification system of claim 5 wherein the joint emulation verification result is used to locate and repair errors in the remote direct memory access hardware logic and the remote direct memory access software.
7. The emulation verification system of claim 1 wherein the emulator is a fast emulator, the network card is a standard remote direct memory access network card, and standard remote direct memory access messages are transmitted between the design to be tested and the standard remote direct memory access network card.
8. The emulation verification system of claim 1 wherein the at least one simulation device for interacting with the design to be tested to perform emulation verification of the remote direct memory access hardware logic in coordination with the design to be tested comprises:
the at least one simulation device cooperates with the design to be tested for at least one of: direct memory access operation, interrupt operation, base address register space read-write and shortcut peripheral interconnection standard equipment configuration space read-write.
9. The simulated verification system of claim 8, wherein the at least one simulation device comprises one or more shortcut interconnection standard devices for reading and writing the shortcut interconnection standard device configuration space in coordination with the design to be tested.
10. The simulation verification system of claim 8, wherein the at least one simulation device comprises one or more storage mediums for performing the direct memory access operation in conjunction with the design to be tested.
11. The simulated verification system of claim 8, wherein the interaction between the at least one simulated device and the design to be tested is implemented by a transmission control protocol socket.
12. The emulation verification system of claim 11 wherein the base address register space read-write and the peripheral interconnect standard device configuration space read-write are implemented by a configuration parameter socket, and the direct memory access operation and the interrupt operation are implemented by a direct memory access socket.
13. The emulation verification system of claim 12 wherein the design to be tested is for parsing data packets of the configuration parameter socket and the direct memory access socket, the design to be tested further for sending remote direct memory access messages to the network card via a message socket and receiving messages from the network card via the message socket.
14. The simulation verification system of claim 12, wherein the simulator processes messages from the design under test through the direct memory access socket and uploads processing results through the remote direct memory access software.
15. The simulation verification system of claim 13, wherein the simulation verification system further comprises:
the first adaptation module is used for converting interaction between the design to be tested and the at least one simulation device into input and output of a design format to be tested;
a second adapting module for converting the interaction between the design to be tested and the network card into the input and output of the design format to be tested,
the first adaptation module, the second adaptation module and the design to be tested together form a logic verification platform.
16. The emulation verification system of claim 1 wherein the emulation verification system is a remote direct memory access emulation verification system, and the joint emulation verification result generated by the remote direct memory access emulation verification system is a remote direct memory access software and hardware joint emulation verification result.
17. The simulation verification system of claim 1, wherein the remote direct memory access hardware logic provided by the design under test corresponds to a logic function of a remote direct memory access chip, the remote direct memory access chip being a field programmable gate array chip or an application specific integrated circuit chip or a data processor.
18. The simulation verification method is used for remote direct memory access simulation verification, and is characterized by comprising the following steps of:
providing remote direct memory access hardware logic through the design to be tested;
simulating, by an emulator, an operating system to run remote direct memory access software for emulating software-hardware interactions associated with the remote direct memory access hardware logic and to provide at least one emulation device for interacting with the design to be tested to perform emulation verification of the remote direct memory access hardware logic in coordination with the design to be tested;
interaction with the design to be tested is carried out through a network card so as to realize network card interoperation test; and
and generating a joint simulation verification result of the remote direct memory access hardware logic and the remote direct memory access software based on the observation results of the simulator and the network card.
19. The simulation verification method of claim 18, wherein the observations comprise interaction characteristics between the design to be tested and the network card and feedback from the design to be tested received by the simulator, the simulation verification method further comprising:
generating an excitation signal by the remote direct memory access software simulation, and generating the joint simulation verification result by comparing the observation with a reference observation corresponding to the excitation signal.
20. The method of claim 18, wherein the at least one simulation device for interacting with the design to be tested to perform simulation verification of the remote direct memory access hardware logic in coordination with the design to be tested, comprises:
the at least one simulation device cooperates with the design to be tested for at least one of: direct memory access operation, interrupt operation, base address register space read-write and shortcut peripheral interconnection standard equipment configuration space read-write.
21. A computer device, characterized in that it comprises a memory, a processor and a computer program stored on the memory and executable on the processor, which processor implements the method according to any of claims 18 to 20 when executing the computer program.
22. A computer readable storage medium storing computer instructions which, when run on a computer device, cause the computer device to perform the method of any one of claims 18 to 20.
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