CN117539705A - Verification method, device and system of system on chip and electronic equipment - Google Patents
Verification method, device and system of system on chip and electronic equipment Download PDFInfo
- Publication number
- CN117539705A CN117539705A CN202410035377.4A CN202410035377A CN117539705A CN 117539705 A CN117539705 A CN 117539705A CN 202410035377 A CN202410035377 A CN 202410035377A CN 117539705 A CN117539705 A CN 117539705A
- Authority
- CN
- China
- Prior art keywords
- verification
- information
- collaborative
- verified
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012795 verification Methods 0.000 title claims abstract description 319
- 238000000034 method Methods 0.000 title claims abstract description 50
- 238000012545 processing Methods 0.000 claims abstract description 33
- 238000012544 monitoring process Methods 0.000 claims abstract description 5
- 230000006870 function Effects 0.000 claims description 44
- 238000004590 computer program Methods 0.000 claims description 3
- 238000010200 validation analysis Methods 0.000 claims description 2
- 238000004088 simulation Methods 0.000 abstract description 5
- 238000012549 training Methods 0.000 description 18
- 230000002195 synergetic effect Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 7
- 230000004044 response Effects 0.000 description 6
- 230000001360 synchronised effect Effects 0.000 description 6
- 238000013461 design Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
- 230000014616 translation Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Storage Device Security (AREA)
Abstract
The invention provides a verification method, device and system of a system on chip and electronic equipment, and relates to the field of chip verification. The verification method of the system on chip provided by the invention is applied to a central processing unit of the system on chip and comprises the following steps: receiving a chip reset release signal and information to be verified, which are sent by a verification environment; responding to a chip reset release signal, and completing initialization configuration according to information to be verified; distributing collaborative verification space in the memory of the system on chip according to the information to be verified; generating cooperative verification information according to the verification requirement and the information to be verified; and writing the collaborative verification information and a first collaborative signal for triggering the verification environment to perform collaborative verification into a collaborative verification space so as to trigger the verification environment to perform collaborative verification. The invention realizes cooperative work by writing the cooperative signals in the memory, and the central processing unit and the verification environment are convenient for writing and monitoring the cooperative signals; the verification environment is utilized to carry out complex operation, so that the simulation time is short and the efficiency is high.
Description
Technical Field
The present invention relates to the field of chip verification, and in particular, to a method, an apparatus, a system, and an electronic device for verifying a system on a chip.
Background
In a system on chip, verification of correctness of an instruction set architecture (ISA, instruction Set Architecture) in a CPU (Central Processing Unit ) is an important part of verification of CPU operation. Because of the programmability of the CPU, the verification policy for the CPU and the verification of the functional module are significantly different. Verification of a CPU in a system on a chip can typically only be confirmed by waveforms to confirm compliance with expectations. At present, the common practice is to print through UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous receiver Transmitter), so as to conveniently obtain the running state of CPU. In EDA (Electronic design automation ) verification of other functional modules in the CPU, memory configuration is required, such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory, double rate synchronous dynamic random access memory).
However, the inventors of the present invention found that the existing verification method has the following problems: the working frequency of the CPU is far higher than that of the UART, the working frequency of the CPU is tens of times different from that of the UART, and the verification efficiency by using the UART is low; when the CPU is used for EDA verification of the functional module, a lot of time is required for configuration and training of the memory.
Disclosure of Invention
According to a first aspect of the present invention, a method for verifying a system on a chip is provided, applied to a central processing unit of the system on a chip, and the method may include: receiving a chip reset release signal and information to be verified, which are sent by a verification environment; responding to a chip reset release signal, and completing initialization configuration according to information to be verified; distributing collaborative verification space in the memory of the system on chip according to the information to be verified; generating cooperative verification information according to the verification requirement and the information to be verified; and writing the collaborative verification information and a first collaborative signal for triggering the verification environment to perform collaborative verification into a collaborative verification space so as to trigger the verification environment to perform collaborative verification.
According to a second aspect of the present invention, a verification device for a system on chip is presented, the device may comprise: the receiving module can be used for receiving a chip reset release signal and information to be verified, which are sent by the verification environment; the initialization module can be used for responding to the chip reset release signal and completing initialization configuration according to the information to be verified; the space allocation module can be used for allocating collaborative verification space in the memory of the system on chip according to the information to be verified; the information generation module can be used for generating collaborative verification information according to the verification requirement and the information to be verified; the writing module can be used for writing the collaborative verification information and a first collaborative signal for triggering the verification environment to perform collaborative verification into the collaborative verification space so as to trigger the verification environment to perform collaborative verification.
According to a third aspect of the present invention, a verification system of a system on chip is presented, the system may comprise:
the system on a chip can comprise a central processing unit, a functional module and a memory; the central processing unit is used for executing the method according to the first aspect of the application; the functional module is used for receiving the control of the central processing unit and initializing and running; the memory is used for receiving the control of the central processing unit and storing cooperative verification information and a first cooperative signal in the cooperative verification space; the memory is also used for receiving the control of the verification environment and storing a second cooperative signal in the cooperative verification space;
the verification environment is used for sending a chip reset release signal and information to be verified to the central processing unit; performing function execution preparation under the condition that the verification requirement comprises a verification function module, and writing a second cooperative signal into the cooperative verification space after the function execution preparation is completed; responding to the first cooperative signal to acquire cooperative verification information in the cooperative verification space; and generating a verification result according to the execution result and a preset result under the condition that the collaborative verification information is the execution result.
According to a fourth aspect of the present invention, an electronic device is presented, which may comprise: a processor; a memory storing a computer program which, when executed by a processor, causes the processor to perform a method according to the first aspect of the invention.
According to a fifth aspect of the present invention there is provided a non-transitory computer readable storage medium having stored thereon computer readable instructions which, when executed by a processor, cause the processor to perform a method according to the first aspect of the present invention.
The method provided by the invention realizes the collaborative simulation of the CPU and the verification environment by distributing a section of address space in the memory, and verifies the memory and the complex functional module in the system on chip in a collaborative mode, and the technical effects at least comprise: the verification environment is utilized to realize operations which are difficult to realize or have lower efficiency for the CPU, including but not limited to configuration training of the memory and executing a result comparison and peer-to-peer process on the functional module, so that the time required by simulation is greatly reduced; the method has the advantages that the collaborative signal is written in the address space in the system-on-chip memory to perform collaborative work, the CPU and the verification environment can complete writing and monitoring of the collaborative signal only by one or two instructions, and the operation is convenient and the accuracy is high. The method provided by the invention can improve the efficiency of verifying the memory and the functional module in the system on chip in time and operation.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it will be apparent that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings by those skilled in the art without departing from the scope of the claimed invention.
FIG. 1 is a flow chart of a verification method 1000 of a system-on-chip applied to a CPU according to the present invention;
fig. 2 is a schematic flow chart of step S103A in step S103 included in the method 1000 in fig. 1;
fig. 3 is a flowchart of an embodiment S1031A of the step S1031 included in the step S103A in fig. 2;
fig. 4 is a flowchart of an embodiment S1031B of the step S1031 included in the step S103A in fig. 2;
FIG. 5 is a flowchart of step S104 included in the method 1000 of FIG. 1;
FIG. 6 is a schematic diagram of a verification device 2000 of the system-on-chip of the present invention;
FIG. 7 is a schematic diagram of a verification system 3000 of a system-on-chip of the present invention;
FIG. 8 is a schematic diagram of an embodiment 4000 of a verification method of a system-on-chip of the present invention;
FIG. 9 is a schematic diagram of an embodiment 5000 of a verification method of a system-on-chip of the present invention;
fig. 10 is a schematic structural diagram of an electronic device according to the present invention.
Reference numerals illustrate:
2000, a verification device of the system on chip; 201: a receiving module; 202: initializing a module; 203: a space allocation module; 204: an information generation module; 205: a write module;
3000: a verification system for the system-on-chip; 301: a system on a chip; 302: the environment is verified.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The English abbreviations and corresponding Chinese translations included in the invention are as follows:
a CPU (Central Processing Unit ); ISA (Instruction Set Architecture ); UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous receiver Transmitter); EDA (Electronic design automation ); DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory, double Rate synchronous dynamic random Access memory); IP (intellectual property); ethernet (Ethernet); PCIE (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard); UVM (Universal Verification Methodology, universal validation methodology); soC (System on Chip); SRAM (Static Random Access Memory ); SDRAM (Synchronous Dynamic Random Access Memory), synchronous dynamic random access memory).
Among them, the chip industry regards a functional module developed by a chip design engineer as an Intellectual Property (IP) and thus, IP (intellectual property) can be understood as a module that implements some functions.
Fig. 1 is a flow chart of a verification method 1000 of a system-on-chip applied to a central processing unit according to the present invention. As shown in fig. 1, the method 1000 includes steps S101-S104.
In step S101, the central processor receives a chip reset release signal and information to be verified, which are sent by the verification environment. Optionally, the chip reset release signal indicates that the current central processing unit is in an operational state capable of performing verification. In some embodiments, in step S101, the information to be verified includes function information of the central processing unit to be verified, function information of the memory or other functional modules of the system on chip to be verified, and a preset result of the memory or other functional modules to be verified.
In step S102, in response to the chip reset release signal, the central processor completes the initialization configuration according to the information to be verified. In step S102, the central processing unit completes the power-on startup according to the information to be verified, and executes the main function of the central processing unit to complete the basic configuration of the system on chip.
In step S103, the central processor allocates a collaborative verification space in a memory of the system on chip according to the information to be verified; and generating collaborative verification information according to the verification requirement and the information to be verified.
In some embodiments, in step S103, the central processor allocates a collaborative verification space in a memory of the system-on-chip according to the information to be verified. In some embodiments, the information to be verified includes a preset result of the memory or the functional module to be verified, and the central processor divides the collaborative verification space in the memory based on an address plan of the system on chip according to a size and a data format of the preset result. Optionally, the partitioned collaborative verification space satisfies the size of the preset result and conforms to the data format of the preset result. Wherein the partitioned collaborative authentication space can be read and written by the central processing unit and the authentication environment. In step S103, the central processing unit allocates a collaborative verification space in the memory only for the verification process of the system on chip, without affecting the functional implementation in use of the system on chip.
Optionally, the memory of the system-on-chip includes any one or more of registers, SRAM, SDRAM, DDRAM. In some embodiments, in step S103, the collaborative verification space includes a signal address space and a verification address space. Optionally, the signal address space is a memory space of 8 or 16 or 32 bits in memory allocated according to an address plan of the system on chip. Alternatively, the central processor takes one or more registers of 8 or 16 or 32 bits in size as the signal address space. Alternatively, the CPU takes a section of address in SRAM or SDRAM as the verification address space.
In some embodiments, in step S103, the signal address space stores the first synergistic signal written by the CPU. For example, in some embodiments, the first collaboration signal includes a functional module execution completion signal indicating that the functional module execution to be verified is complete, and the execution results are written into the verification address space. Optionally, the first synergistic signal written by the CPU to the register as the signal address space is a first identification value.
In some embodiments, in step S103, the signal address space stores a second collaboration signal written by the verification environment, the second collaboration signal indicating that the execution of the function by the verification environment is ready to complete. In some embodiments, the second cooperative signal includes a memory training completion signal indicating completion of memory training by the verification environment. Optionally, the verification context writes a second synergistic signal to a register as the signal address space as a second identification value.
In some embodiments, in step S103, the central processor generates cooperative authentication information according to the authentication requirement and the information to be authenticated. In some embodiments, the central processing unit obtains an execution result according to the verification requirement and the information to be verified, and takes the execution result as cooperative verification information.
Optionally, the authentication requirement includes an authentication memory or an authentication function. In some embodiments, in step S103, the verification requirement includes verifying the memory, and the central processor determines the memory to be verified according to the information to be verified, and reads a default memory value of the memory to be verified as an execution result.
In some embodiments, in step S103, the verification requirement includes a verification function module, and the central processor determines the verification function module according to the information to be verified. In some embodiments, in step S103, the central processor monitors the collaborative verification space after determining the functional module to be verified to obtain a second collaborative signal.
In some embodiments, in step S103, in response to the second collaboration signal, the central processor initializes and executes the functional module to be verified according to the information to be verified, so as to obtain an execution result. In some specific embodiments, in step S103, the functional module to be verified includes an IP (intellectual property) module in the chip that implements a specific function. Optionally, the functional module to be verified is an Ethernet (Ethernet) module or a PCIE (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard) module.
In some embodiments, in step S103, the central processor generates a verification result according to the execution result and the preset result, and uses the verification result as the cooperative verification information. In some embodiments, the central processor determines that the verification result is functional if the execution result and the preset result satisfy the verification condition. In some embodiments, the central processor determines that the verification result is abnormal in function if the execution result and the preset result do not satisfy the verification condition.
In step S104, the central processor writes the cooperative verification information and the first cooperative signal for triggering the verification environment to perform cooperative verification into the cooperative verification space, so as to trigger the verification environment to perform cooperative verification.
In some embodiments, the collaborative verification space includes a verification address space and a signal address space. In some embodiments, in step S104, the central processor writes the cooperative verification information into the verification address space, then generates a first cooperative signal, and writes the first cooperative signal into the signal address space to trigger the verification environment to perform cooperative verification.
In some embodiments, in step S104, the cooperative verification information is an execution result or a verification result of verifying the memory or the functional module, and the content of the cooperative verification information is long, so that the verification environment will consume more time and resources to poll and read the verification address space even if the central processor stores the cooperative verification information in the verification address space. Therefore, the signal address space is set for the central processing unit to store the information writing signal, so that the verification environment can poll the monitoring signal address space, and conveniently know that the cooperative verification information is written, and the verification environment can read the cooperative verification information.
According to the embodiment shown in fig. 1, the method provided by the invention realizes the collaborative simulation of the CPU and the verification environment by allocating a section of address space in the memory, and verifies the memory and the complex function module in the system on chip in a collaborative manner, and the technical effects at least comprise: the verification environment is utilized to realize operations which are difficult to realize or have lower efficiency for the CPU, including but not limited to configuration training of the memory and executing a result comparison and peer-to-peer process on the functional module, so that the time required by simulation is greatly reduced; the method has the advantages that the collaborative signal is written in the address space in the system-on-chip memory to perform collaborative work, the CPU and the verification environment can complete writing and monitoring of the collaborative signal only by one or two instructions, and the operation is convenient and the accuracy is high. The method provided by the invention can improve the efficiency of verifying the memory and the functional module in the system on chip in time and operation.
Fig. 2 is a schematic flow chart of step S103A in step S103 included in the method 1000 in fig. 1. As shown in fig. 2, step S103A is to generate cooperative authentication information according to the authentication requirement and the information to be authenticated, and step S103A includes steps S1031 to S1033.
In step S1031, the central processor obtains an execution result according to the authentication requirement and the information to be authenticated. In some embodiments, the authentication requirements include an authentication memory or an authentication function. In some embodiments, in step S1031, the verification requirement includes verifying the memory, and the cpu determines the memory to be verified according to the information to be verified. In some embodiments, in step S1031, the verification requirement includes a verification function module, and the central processor determines the verification function module according to the information to be verified.
In some embodiments, in step S1031, the verification request is to verify the memory, and the cpu reads the default memory value of the memory to be verified as the execution result. In some embodiments, in step S1031, the verification requirement is a verification function module, and the central processor monitors the collaborative verification space to obtain a second collaborative signal. In some embodiments, the central processing unit needs to perform preparation when executing the functional module to be verified, and the time for performing the functional preparation by using the central processing unit is long and low in efficiency. The functional preparation is thus completed using the verification environment, and the verification environment writes the second collaboration signal in the collaborative verification space after the functional preparation is completed.
In some embodiments, in step S1031, in response to the second collaboration signal, the central processor initializes and executes the functional module to be verified according to the information to be verified to obtain an execution result.
In step S1032, the central processor regards the execution result as cooperative authentication information. In step S1033, the central processor generates a verification result according to the execution result and the preset result, and uses the verification result as cooperative verification information. In some embodiments, in step S1033, the verification requirement is to verify the memory, and the preset result is a preset value of the memory included in the development document. In some embodiments, in step S1033, the verification requirement is to verify the functional module, and the preset result is a set of output values expected by the functional module after calculation.
In some embodiments, in step S1032 and step S1033, the central processor determines the execution result or the verification result as cooperative verification information according to the actual application scenario. For example, in the case that the execution result is complex, the process of determining the verification result needs to consume more resources and time, and is inefficient, the central processor uses the execution result as cooperative verification information, the verification environment reads the execution result in the cooperative verification space, and the process of determining the verification result is completed in the verification environment. Under the condition that the execution result is simpler, the central processing unit completes the process of determining the verification result, and takes the verification result as cooperative verification information, and the verification environment only needs to acquire and print the verification result in the cooperative verification space.
Fig. 3 is a flowchart of an embodiment S1031A of step S1031 included in step S103A in fig. 2. As shown in fig. 3, step S1031A includes step S311 to step S312. In some embodiments, in step S1031A shown in fig. 3, the verification requirement includes verifying the memory.
In step S311, the central processor determines the memory to be verified according to the information to be verified. In step S312, the cpu reads the default memory value of the memory to be verified as the execution result.
In some embodiments, in step S311 and step S312, the memory to be verified is a register included in the system on chip, and a default memory value of the register is a default value after the register is powered on and reset. The default value after the register is powered on and reset can affect the running state of the system on chip, so that the correctness of the default value needs to be verified.
Fig. 4 is a flowchart of an embodiment S1031B of step S1031 included in step S104 in fig. 2. As shown in fig. 3, step S1031B includes steps S313 to S315. In some embodiments, in step S1031B shown in fig. 4, the verification requirement includes a verification function module.
In step S313, the central processor determines a functional module to be verified according to the information to be verified. In some embodiments, in step S313, the functional module to be verified includes an IP module in the chip that implements a specific function. Optionally, the functional module to be verified is an Ethernet module or a PCIE module.
In step S314, the central processor monitors the collaborative verification space to obtain a second collaborative signal. In some embodiments, in step S314, the collaborative verification space includes a verification address space and a signal address space, and the central processor monitors the signal address space to obtain a second collaborative signal.
In some embodiments, the central processing unit needs to perform preparation when executing the functional module to be verified, and at this time, the central processing unit is used for performing functional preparation, which is time-consuming and inefficient, so that the functional preparation is completed by using the verification environment, and after the functional preparation is completed, the second collaboration signal is written in the collaborative verification space.
For example, a specific memory is required for the cpu to execute the functional module to be verified, and the use of the specific memory requires memory training. For example, DDR is required when the cpu verifies the functional module to be verified. In some embodiments, training of the memory is completed using the verification environment, and after training is completed, a memory training completion signal is generated as the second synergistic signal. The verification environment writes the memory training completion signal in the collaborative verification space, and the central processor can monitor the collaborative verification space to obtain the memory training completion signal.
In step S315, in response to the second collaboration signal, the central processor initializes and executes the functional module to be verified according to the information to be verified, so as to obtain an execution result. The execution result is a set of output data obtained after the function of the functional module to be verified is executed.
Fig. 5 is a flow chart of step S104 included in the method 1000 in fig. 2. As shown in fig. 5, step S104 includes steps S1041 to S1042.
In some embodiments, in step S104, the collaborative verification space includes a verification address space and a signal address space. In step S1041, the central processor writes the cooperative authentication information into the authentication address space. In step S1042, the cpu generates a first synergistic signal and writes the first synergistic signal into the signal address space.
In some embodiments, in step S1041, the central processor writes the collaborative authentication information to the authentication address space, thereby enabling the authentication environment to obtain the collaborative authentication information from the authentication address space.
In some embodiments, in step S1041, the cooperative verification information is an execution result or a verification result of verifying the memory or the functional module, and the content of the cooperative verification information is long, so that even if the cooperative verification information is stored in the verification address space, the verification environment polls to read the verification address space will consume more time and resources. Therefore, the signal address space is set for storing the information write signal in step S1042, so that the authentication environment can poll the monitor signal address space, conveniently learn that the cooperative authentication information has been written, and thus the authentication environment can read the cooperative authentication information.
Fig. 6 is a schematic structural diagram of a verification device 2000 of the system-on-chip of the present invention. As shown in fig. 6, the verification apparatus 2000 of the system-on-chip includes a receiving module 201, an initializing module 202, a space allocation module 203, an information generating module 204, and a writing module 205.
In some embodiments, the receiving module 201 receives the chip reset release signal and the information to be verified sent by the verification environment. Optionally, the chip reset release signal indicates that the current central processing unit is in an operational state capable of performing verification. In some embodiments, the information to be verified includes functional information of the central processing unit to be verified, functional information of a memory or other functional modules of the system on chip to be verified, and a preset result of the memory or other functional modules to be verified.
In some embodiments, in response to the chip reset release signal, the initialization module 202 completes the initialization configuration according to the information to be verified. In some embodiments, the initialization module 202 completes the power-on startup according to the information to be verified and executes the main function of the central processing unit to complete the basic configuration of the system on chip.
In some embodiments, the space allocation module 203 allocates the collaborative verification space in the memory of the system-on-chip according to the information to be verified. In some embodiments, the information to be verified includes a preset result of the memory or the functional module to be verified, and the space allocation module 203 divides the collaborative verification space in the memory based on the address plan of the system on chip according to the size and the data format of the preset result. Optionally, the partitioned collaborative verification space satisfies the size of the preset result and conforms to the data format of the preset result. Wherein the partitioned collaborative authentication space can be read and written by the central processing unit and the authentication environment.
Optionally, the memory of the system-on-chip includes any one or more of registers, SRAM, SDRAM, DDRAM. In some embodiments, the collaborative verification space includes a signal address space and a verification address space. Optionally, the signal address space is a storage space with a size of 8, 16 or 32 bits in the memory allocated by the space allocation module 203 according to the address plan of the system on chip. Alternatively, the space allocation module 203 takes one or more registers of 8 or 16 or 32 bits in size as the signal address space. Alternatively, the space allocation module 203 uses a section of address in SRAM or SDRAM as the verification address space.
In some embodiments, the signal address space stores a first synergistic signal written by the CPU. For example, in some embodiments, the first collaboration signal includes a functional module execution completion signal indicating that the functional module execution to be verified is complete, and the execution results are written into the verification address space. Optionally, the first synergistic signal written by the central processor to the register as the signal address space is a first identification value.
In some embodiments, the signal address space stores a second synergistic signal written by the verification environment. The second cooperative signal indicates that the preparation for the execution of the function by the authentication environment is completed. In some embodiments, the second cooperative signal includes a memory training completion signal indicating completion of memory training by the verification environment. Optionally, the verification context writes a second synergistic signal to a register as the signal address space as a second identification value.
In some embodiments, the information generation module 204 generates collaborative authentication information based on authentication requirements and information to be authenticated. In some embodiments, the information generating module 204 obtains the execution result according to the verification requirement and the information to be verified, and uses the execution result as the collaborative verification information.
Optionally, the authentication requirement includes an authentication memory or an authentication function. In some embodiments, the verification requirement includes verifying the memory, and the information generating module 204 determines the memory to be verified according to the information to be verified, and reads a default memory value of the memory to be verified as the execution result.
In some embodiments, the verification requirements include a verification function module, and the information generation module 204 determines the function module to be verified based on the information to be verified. In some embodiments, the information generation module 204 monitors the collaborative verification space after determining the functional module to be verified to obtain a second collaborative signal.
In some embodiments, in response to the second collaboration signal, the information generating module 204 initializes and executes the functional module to be verified according to the information to be verified to obtain an execution result. In some embodiments, the functional module to be verified includes an IP (intellectual property) module in the chip that implements a specific function. Optionally, the functional module to be verified is an Ethernet (Ethernet) module or a PCIE (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard) module.
In some embodiments, the information generating module 204 generates a verification result according to the execution result and the preset result, and uses the verification result as the collaborative verification information. In some embodiments, the information generation module 204 determines that the verification result is functional if the execution result and the preset result satisfy the verification condition. In some embodiments, the information generation module 204 determines that the verification result is dysfunctional in the event that the execution result and the preset result do not satisfy the verification condition.
In some embodiments, the writing module 205 writes the collaborative authentication information and the first collaborative signal for triggering the collaborative authentication by the authentication environment to the collaborative authentication space to trigger the collaborative authentication by the authentication environment.
In some embodiments, the collaborative verification space includes a verification address space and a signal address space. In some embodiments, the write module 205 writes the collaborative verification information to the verification address space, then generates a first collaborative signal, and writes the first collaborative signal to the signal address space to trigger the verification environment to collaborative verify.
In some embodiments, the collaborative authentication information is an execution result or an authentication result of authenticating the memory or the functional module, and the content of the collaborative authentication information is long, so that even if the writing module 205 stores the collaborative authentication information in the authentication address space, the authentication environment polls to read the authentication address space will consume more time and resources. Therefore, the signal address space is set for the write module 205 to store the information write signal, so that the verification environment can poll the monitor signal address space, and conveniently learn that the cooperative verification information has been written, so that the verification environment can read the cooperative verification information.
Fig. 7 is a schematic diagram of a verification system 3000 of a system-on-chip of the present invention. As shown in fig. 7, a verification system 3000 of a system-on-chip includes a system-on-chip 301 and a verification environment 302.
Referring to fig. 7, data communication is enabled between a system on a chip 301 and a verification environment 302. The system on chip 301 includes a CPU, a functional module, and a memory, where the CPU, the functional module, and the memory can all perform data communication, and the memory can be read and written with data by the CPU and the verification environment 302. In fig. 7, the verification environment 302 sends a chip reset release signal and information to be verified to the system on chip 301. The CPU in the system on chip 301 receives the chip reset release signal and the information to be verified sent by the verification environment 302, and completes the initialization configuration of the system on chip 301 according to the information to be verified.
The CPU in the system on chip 301 allocates a cooperative authentication address in the memory according to the information to be authenticated. In some embodiments, the collaborative verification address includes a signal address space and a verification address space. Alternatively, the signal address space may be a specific address interval in a register or SRAM, SDRAM. Alternatively, the verification address space may be a specific address space in SRAM, SDRAM. The CPU in the system on chip 301 generates cooperative authentication information according to the authentication requirement and the information to be authenticated, and writes the cooperative authentication information into the authentication address space. After writing the cooperative authentication information, the CPU generates a first cooperative signal and writes the first cooperative signal into the signal address space. Wherein the first cooperative signal indicates that cooperative authentication information has been written to the authentication address space, the authentication environment 302 is capable of reading.
In the case where the verification requirement is a verification function module, the verification environment 302 performs function execution preparation after transmitting the chip reset release signal and the information to be verified. Optionally, the function execution preparation includes memory training, and the second synergistic signal is written to the signal address space after the memory training is completed. After completion of the initialization configuration, the CPU monitors the signal address space and determines whether memory training of the verification environment 302 is complete based on whether a second synergistic signal is present.
After the CPU in the system on chip 301 monitors the second cooperative signal, initializing and executing the function module to be verified according to the information to be verified, and after all the functions to be verified included in the information to be verified are executed, generating an execution result. In some embodiments, the CPU in the system-on-chip 301 writes the execution result as collaborative verification information into the verification address space. In some embodiments, the CPU in the system on chip 301 generates a verification result according to the execution result and the preset result, and writes the verification result into the verification address space as cooperative verification information.
The authentication environment 302 reads the collaborative authentication information in the authentication address space. In some embodiments, the collaborative verification information is an execution result, and the verification environment 302 generates a verification result according to the execution result and a preset result. In some embodiments, the collaborative authentication information is an authentication result. The verification environment 302 prints the verification result to represent the state of the verified memory or functional module.
Fig. 8 is a schematic diagram of an embodiment 4000 of a verification method of a system-on-chip of the present invention. Referring to fig. 8, in the embodiment 4000, the verification environment is a UVM verification environment, the functional requirements of the system on a chip are verification function modules, the function module to be verified is an Ethernet module, the function execution preparation to be performed in the verification environment is memory training, and the trained memory is DDR.
In fig. 8, a chip reset release signal and information to be verified are determined in a UVM verification environment and sent to a CPU. And after receiving the chip reset release signal and the information to be verified, the CPU is powered on to complete basic configuration. The CPU allocates a register in the memory of the system on chip as a signal address space and allocates a section of fixed address interval of the SRAM as a verification address space.
In fig. 8, the authentication requirement is an authentication function module, and the function module to be authenticated included in the information to be authenticated is an Ethernet module. The CPU determines an Ethernet module according to the information to be verified, monitors a register serving as a signal address space and waits for DDR training to be completed.
After sending the chip reset release signal and the function verification information to be verified, the UVM verification environment starts DDR tracking through VIP in UVM. After completing DDR tracking, the UVM verification environment writes the value A into a register in the system-on-chip as a signal address space.
And when the value in the polling waiting register is changed to A in the process of waiting for the completion of DDR (double data rate) tracking, the CPU starts to initialize and configure an Ethernet module in a System on Chip (SoC) and starts to execute the Ethernet module. The CPU obtains the Ethernet result after executing the Ethernet module, and writes the result into the verification address space. And the UVM verification environment reads the Ethernet result in the verification address space, and compares the Ethernet result with a preset result, so that a final verification result of the module function is obtained. The UVM authentication environment prints the authentication result to represent the state of the Ethernet module in the SoC.
Fig. 9 is a schematic diagram of an embodiment 5000 of a verification method of a system-on-chip of the present invention. Referring to fig. 9, the verification environment in embodiment 5000 is a UVM verification environment, the functional requirement of the system on chip is a verification memory, and the memory to be verified is register 1.
In fig. 9, a chip reset release signal and information to be verified are determined in a UVM verification environment and sent to a CPU. And after receiving the chip reset release signal and the information to be verified, the CPU is powered on to complete basic configuration. The CPU allocates a register 2 as a signal address space in the memory of the system on chip and allocates a section of fixed address space of the SRAM as a verification address space.
In fig. 9, the verification requirement is to verify the memory, and the information to be verified includes the memory to be verified as the register 1. The CPU determines the register 1 according to the information to be verified, and reads the value of the register 1 as an execution result. The CPU compares the execution result with a memory value preset by the register 1 to generate a verification result, and writes the verification result into a verification address space. The UVM verification environment prints a verification result to represent the state of the register 1 in the SoC.
Fig. 10 is a schematic structural diagram of an electronic device according to the present invention.
Referring to fig. 10, fig. 10 provides an electronic device including a processor and a memory. The memory stores computer instructions that, when executed by the processor, cause the processor to execute the computer instructions to implement the method and refinement as shown in fig. 1.
It should be understood that the above-described device embodiments are illustrative only and that the disclosed device may be implemented in other ways. For example, the division of the units/modules in the above embodiments is merely a logic function division, and there may be another division manner in actual implementation. For example, multiple units, modules, or components may be combined, or may be integrated into another system, or some features may be omitted or not performed.
In addition, unless specifically described, each functional unit/module in each embodiment of the present invention may be integrated into one unit/module, or each unit/module may exist alone physically, or two or more units/modules may be integrated together. The integrated units/modules described above may be implemented either in hardware or in software program modules.
The integrated units/modules, if implemented in hardware, may be digital circuits, analog circuits, etc. Physical implementations of hardware structures include, but are not limited to, transistors, memristors, and the like. The processor or chip may be any suitable hardware processor, such as CPU, GPU, FPGA, DSP and ASIC, etc., unless otherwise specified. The on-chip cache, off-chip Memory, memory may be any suitable magnetic or magneto-optical storage medium, such as resistive Random Access Memory RRAM (Resistive Random Access Memory), dynamic Random Access Memory DRAM (Dynamic Random Access Memory), static Random Access Memory SRAM (Static Random Access Memory), enhanced dynamic Random Access Memory EDRAM (Enhanced Dynamic Random Access Memory), high-Bandwidth Memory HBM (High-Bandwidth Memory), hybrid Memory cube HMC (Hybrid Memory Cube), and the like, unless otherwise indicated.
The integrated units/modules may be stored in a computer readable memory if implemented in the form of software program modules and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present invention may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a memory, comprising several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned memory includes: a U-disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Embodiments of the present invention also provide a non-transitory computer storage medium storing a computer program which, when executed by a plurality of processors, causes the processors to perform the method and refinement as shown in fig. 1.
The foregoing has outlined rather broadly the more detailed description of embodiments of the invention in order that the detailed description of the principles and embodiments of the invention may be implemented in conjunction with the detailed description of embodiments of the invention that follows. Meanwhile, based on the idea of the present invention, those skilled in the art can make changes or modifications on the specific embodiments and application scope of the present invention, which belong to the protection scope of the present invention. In view of the foregoing, this description should not be construed as limiting the invention.
Claims (11)
1. A method for verifying a system on a chip, applied to a central processing unit of the system on a chip, comprising:
receiving a chip reset release signal and information to be verified, which are sent by a verification environment;
responding to the chip reset release signal, and completing initialization configuration according to the information to be verified;
distributing collaborative verification space in the memory of the system-on-chip according to the information to be verified; generating cooperative verification information according to the verification requirement and the information to be verified;
writing the collaborative verification information and a first collaborative signal for triggering the verification environment to perform collaborative verification into the collaborative verification space so as to trigger the verification environment to perform collaborative verification.
2. The method of claim 1, wherein the information to be verified comprises a preset result corresponding to the verification requirement; and distributing collaborative verification space in the memory of the system-on-chip according to the information to be verified, wherein the collaborative verification space comprises the following steps:
and dividing the collaborative verification space which meets the size and accords with the data format in the memory according to the size and the data format of the preset result.
3. The method of claim 2, wherein generating collaborative authentication information based on authentication requirements and the information to be authenticated comprises:
obtaining an execution result according to the verification requirement and the information to be verified;
taking the execution result as the collaborative verification information; or (b)
And generating a verification result according to the execution result and the preset result, and taking the verification result as the collaborative verification information.
4. The method of claim 3, wherein the validation requirement comprises validating a memory; obtaining an execution result according to the verification requirement and the information to be verified, including:
determining a memory to be verified according to the information to be verified;
and reading the default memory value of the memory to be verified as the execution result.
5. A method according to claim 3, wherein the verification requirement comprises a verification function module; obtaining an execution result according to the verification requirement and the information to be verified, including:
determining a functional module to be verified according to the information to be verified;
monitoring the collaborative verification space to obtain a second collaborative signal;
and responding to the second cooperative signal, initializing and executing the functional module to be verified according to the information to be verified, so as to obtain the execution result.
6. The method of any of claims 1-5, wherein the collaborative verification space comprises a verification address space and a signal address space.
7. The method of claim 6, wherein writing the collaborative authentication information and the first collaborative signal into the collaborative authentication space comprises:
writing the collaborative verification information into the verification address space;
the first cooperative signal is generated and written into the signal address space.
8. A verification device for a system-on-chip, comprising:
the receiving module is used for receiving the chip reset release signal and the information to be verified, which are sent by the verification environment;
The initialization module is used for responding to the chip reset release signal and completing initialization configuration according to the information to be verified;
the space allocation module is used for allocating a collaborative verification space in the memory of the system-on-chip according to the information to be verified;
the information generation module is used for generating collaborative verification information according to the verification requirement and the information to be verified;
and the writing module is used for writing the collaborative verification information and a first collaborative signal for triggering the verification environment to perform collaborative verification into the collaborative verification space so as to trigger the verification environment to perform collaborative verification.
9. A verification system for a system-on-chip, comprising:
the system on a chip comprises a central processing unit, a functional module and a memory; the central processor being adapted to perform the method of any one of claims 1-7; the functional module is used for receiving the control of the central processing unit and initializing and operating; the memory is used for receiving the control of the central processing unit, and storing the collaborative authentication information and the first collaborative signal in the collaborative authentication space; the memory is also used for receiving the control of the verification environment and storing a second cooperative signal in the cooperative verification space;
The verification environment is used for sending a chip reset release signal and information to be verified to the central processing unit; performing function execution preparation when the verification requirement comprises a verification function module, and writing the second cooperative signal into the cooperative verification space after the function execution preparation is completed; responding to the first cooperative signal, and acquiring the cooperative verification information in the cooperative verification space; and under the condition that the collaborative verification information is an execution result, generating a verification result according to the execution result and a preset result.
10. An electronic device, comprising:
a processor;
a memory storing a computer program which, when executed by the processor, causes the processor to perform the method of any of claims 1-7.
11. A non-transitory computer-readable storage medium having stored thereon computer-readable instructions that, when executed by a processor, cause the processor to perform the method of any of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410035377.4A CN117539705B (en) | 2024-01-10 | 2024-01-10 | Verification method, device and system of system on chip and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410035377.4A CN117539705B (en) | 2024-01-10 | 2024-01-10 | Verification method, device and system of system on chip and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117539705A true CN117539705A (en) | 2024-02-09 |
| CN117539705B CN117539705B (en) | 2024-06-11 |
Family
ID=89796255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410035377.4A Active CN117539705B (en) | 2024-01-10 | 2024-01-10 | Verification method, device and system of system on chip and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117539705B (en) |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0992916A1 (en) * | 1998-10-06 | 2000-04-12 | Texas Instruments Inc. | Digital signal processor |
| EP0747817B1 (en) * | 1995-06-07 | 2003-09-03 | Compaq Computer Corporation | Method and apparatus for controlling data communication flow in a fault-tolerant multiprocessor system |
| CN1609862A (en) * | 2004-11-19 | 2005-04-27 | 华南理工大学 | IP nuclear simulation confirmation platform based on PCI bus and proving method thereof |
| JP2007058813A (en) * | 2005-08-26 | 2007-03-08 | Fujitsu Ltd | Verification device and verification method |
| JP2007207120A (en) * | 2006-02-03 | 2007-08-16 | Canon Inc | System verifying apparatus and its verification method |
| JP2010118082A (en) * | 2010-03-01 | 2010-05-27 | Toshiba Corp | Information processing apparatus and program verifying method |
| CN102147760A (en) * | 2011-04-22 | 2011-08-10 | 中国电子科技集团公司第三十八研究所 | Processor co-verification platform based on network transmission and testing method of processor co-verification platform |
| US20120198284A1 (en) * | 2011-01-31 | 2012-08-02 | Fujitsu Limited | Memory correctness checking in distributed computer systems |
| CN102841837A (en) * | 2012-06-26 | 2012-12-26 | 中国科学院声学研究所 | Software and hardware co-verification method based on simulator and system thereof |
| JP2013246458A (en) * | 2012-05-23 | 2013-12-09 | Hitachi Ltd | Verification device and verification method |
| EP3321808B1 (en) * | 2016-11-10 | 2019-01-02 | Hitachi, Ltd. | Verification system and verification method |
| CN110442474A (en) * | 2018-05-02 | 2019-11-12 | 深信服科技股份有限公司 | A kind of data consistency checking method, system and data verification end |
| CN116028292A (en) * | 2023-02-28 | 2023-04-28 | 珠海星云智联科技有限公司 | Simulation verification system and method for remote direct memory access simulation verification |
-
2024
- 2024-01-10 CN CN202410035377.4A patent/CN117539705B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0747817B1 (en) * | 1995-06-07 | 2003-09-03 | Compaq Computer Corporation | Method and apparatus for controlling data communication flow in a fault-tolerant multiprocessor system |
| EP0992916A1 (en) * | 1998-10-06 | 2000-04-12 | Texas Instruments Inc. | Digital signal processor |
| CN1609862A (en) * | 2004-11-19 | 2005-04-27 | 华南理工大学 | IP nuclear simulation confirmation platform based on PCI bus and proving method thereof |
| JP2007058813A (en) * | 2005-08-26 | 2007-03-08 | Fujitsu Ltd | Verification device and verification method |
| JP2007207120A (en) * | 2006-02-03 | 2007-08-16 | Canon Inc | System verifying apparatus and its verification method |
| JP2010118082A (en) * | 2010-03-01 | 2010-05-27 | Toshiba Corp | Information processing apparatus and program verifying method |
| US20120198284A1 (en) * | 2011-01-31 | 2012-08-02 | Fujitsu Limited | Memory correctness checking in distributed computer systems |
| CN102147760A (en) * | 2011-04-22 | 2011-08-10 | 中国电子科技集团公司第三十八研究所 | Processor co-verification platform based on network transmission and testing method of processor co-verification platform |
| JP2013246458A (en) * | 2012-05-23 | 2013-12-09 | Hitachi Ltd | Verification device and verification method |
| CN102841837A (en) * | 2012-06-26 | 2012-12-26 | 中国科学院声学研究所 | Software and hardware co-verification method based on simulator and system thereof |
| EP3321808B1 (en) * | 2016-11-10 | 2019-01-02 | Hitachi, Ltd. | Verification system and verification method |
| CN110442474A (en) * | 2018-05-02 | 2019-11-12 | 深信服科技股份有限公司 | A kind of data consistency checking method, system and data verification end |
| CN116028292A (en) * | 2023-02-28 | 2023-04-28 | 珠海星云智联科技有限公司 | Simulation verification system and method for remote direct memory access simulation verification |
Non-Patent Citations (1)
| Title |
|---|
| 汪洋: "SOC软硬件协同验证平台的联合架构设计", 《中国优秀硕士学位论文全文数据库》, 15 July 2013 (2013-07-15), pages 135 - 399 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117539705B (en) | 2024-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11886355B2 (en) | Emulated endpoint configuration | |
| US9940123B1 (en) | Updating device code through a bus | |
| WO2017008675A1 (en) | Method and device for transmitting data in virtual environment | |
| US8874953B2 (en) | System and method of cloud testing and remote monitoring for integrated circuit components in system validation | |
| CN117148817B (en) | Test system | |
| TW201502992A (en) | Generic method to build virtual PCI device and virtual mmio device | |
| CN116185935A (en) | FPGA prototype verification method, system, medium and computing device of controller | |
| CN114090479A (en) | Access report system, method, device, chip and electronic equipment | |
| TW201732635A (en) | Data transfer method and server using the same | |
| CN115080479B (en) | Transmission method, server, device, bare metal instance and baseboard management controller | |
| CN114444422A (en) | Chip verification system, method and storage medium | |
| US10496422B2 (en) | Serial device emulator using two memory levels with dynamic and configurable response | |
| CN117539705B (en) | Verification method, device and system of system on chip and electronic equipment | |
| CN114513436B (en) | SDIO device transmission rate detection method, system and storage medium | |
| Gouk et al. | Enabling realistic logical device interface and driver for nvm express enabled full system simulations | |
| CN116932451A (en) | Data processing method, host and related equipment | |
| CN112612424A (en) | NVMe submission queue control device and method | |
| CN108292264B (en) | Method for managing the availability of memory pages and memory availability management module | |
| CN111475437A (en) | DDR (double data Rate) verification device and method for SOC (System on chip) chip FPGA prototype of solid state disk, computer equipment and storage medium | |
| US20240004750A1 (en) | Remote scalable machine check architecture | |
| US12093528B2 (en) | System and method for managing data access in distributed systems | |
| JP2019016101A (en) | Information processing system, information processing apparatus, and control method of information processing system | |
| CN117194388B (en) | Data management method, device, electronic equipment and storage medium | |
| CN111459867B (en) | Method, device, converter and storage medium for converting USB (Universal Serial bus) into SMI (SMI) | |
| JP4780333B2 (en) | Data prefetch device, data prefetch method and data prefetch program |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |