CN112612424A - NVMe submission queue control device and method - Google Patents
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Abstract
The application discloses NVMe submission queue control device and method, and the device comprises: the submitting queue command state detection circuit is used for detecting whether the current state of each submitting queue is non-empty or not; the first-level shared cache management circuit is used for distributing corresponding first-level cache units in the same first-level shared cache for different submission alignments which are not empty in the current state; and the submitted column-aligning command acquisition circuit is used for sending a submitted column-aligning command acquisition request to the host end so that the NVMe controller can write the submitted queue command returned by the host end into the corresponding first-level cache unit. Therefore, the utilization rate of the submission queue cache can be improved, cache resources can be saved, and the difficulty of hardware circuit layout and wiring of the submission queue cache can be reduced.
Description
Technical Field
The application relates to the technical field of storage, in particular to an NVMe submission queue control device and method.
Background
With the rapid development of cloud computing, artificial intelligence and the internet of things, the storage requirements of terminal products and servers are increasing, and in the process, NVMe (Non-Volatile Memory express) SSD (Solid State Disk) gains more and more attention in the field of storage technology due to the advantages of low delay, low power consumption, high bandwidth and the like, and becomes a new wind direction for the development of storage devices.
In the prior art, different SQ (i.e., Submission queues) of NVMe have different SQ SRAM (i.e., Static Random-Access Memory) cache resources, which causes SQ SRAM resource waste and increases chip area, especially when the number of SQ supported by NVMe is large, and at the same time, the difficulty of layout and wiring of a rear-end hardware circuit is increased and timing convergence is difficult due to the large number of SQ SRAMs.
Disclosure of Invention
In view of this, an object of the present application is to provide an NVMe submission queue control apparatus and method, which can improve the utilization rate of the submission queue cache, save cache resources, and reduce the difficulty of hardware circuit layout and wiring of the submission queue cache, thereby facilitating timing convergence. The specific scheme is as follows:
in a first aspect, the present application discloses an NVMe submission queue control device, including:
the submitting queue command state detection circuit is used for detecting whether the current state of each submitting queue is non-empty or not;
the first-level shared cache management circuit is used for distributing corresponding first-level cache units in the same first-level shared cache for different submission alignments which are not empty in the current state;
and the submitted column-aligning command acquisition circuit is used for sending a submitted column-aligning command acquisition request to the host end so that the NVMe controller can write the submitted queue command returned by the host end into the corresponding first-level cache unit.
Optionally, the apparatus further comprises:
a commit queue enabling circuit for enabling the commit queue;
a commit queue halting circuit to halt the commit queue command to acquire the commit queue.
Optionally, the first-level shared cache management circuit is specifically configured to:
and if any one of the commit queues is not empty, enabled and not suspended, allocating a corresponding first-level cache unit in the first-level shared cache for the commit queue.
Optionally, the apparatus further comprises:
the PRP detection circuit is used for detecting whether a memory corresponding to the submission queue at the host end supports a physical discontinuous function, if the memory supports the physical discontinuous function, detecting whether a physical address submitting a queue command at the current host end is available, if the physical address is available, using the physical address as a target physical address, if the physical address is unavailable, sending a request for obtaining PRP data of the submission queue to the host end before reading the submission queue command from the host end, and then analyzing the returned PRP data to obtain the available physical address submitting the queue command, so as to obtain the target physical address.
Optionally, the submit pairing-column command obtaining circuit is specifically configured to:
and sending a request for submitting the alignment command acquisition to the host side based on the target physical address.
Optionally, the apparatus further comprises a first-level shared cache detection circuit and a second-level shared cache management circuit, wherein,
the first-level shared cache detection circuit is used for detecting whether the first-level shared cache is non-empty, and if the first-level shared cache is non-empty, sending a request for acquiring a second-level shared cache unit to the second-level shared cache management circuit;
correspondingly, the second-level shared cache management circuit is used for allocating the second-level shared cache units.
Optionally, the apparatus further comprises:
and the submission queue command writing buffer circuit is used for writing the submission queue command in the first-level shared buffer into the corresponding second-level shared buffer unit.
Optionally, the apparatus further comprises:
and the submission queue command detection circuit is used for carrying out validity detection on the submission queue command in the first-level shared cache.
Optionally, the apparatus further comprises:
and the command detection result write cache circuit is used for writing the detection result of the submitted queue command into the detection result shared cache.
In a second aspect, the application discloses a NVMe submission queue control method, including:
detecting whether the current state of each submission queue is non-empty through a submission queue command state detection circuit;
distributing corresponding first-level cache units in the same first-level shared cache for different submitted alignments which are not empty in the current state through a first-level shared cache management circuit;
and sending a submitted column-aligning command acquisition request to the host end by the submitted column-aligning command acquisition circuit, so that the NVMe controller writes a submitted queue command returned by the host end into the corresponding first-level cache unit.
It can be seen that the NVMe submission queue control device disclosed in the present application includes: the submitting queue command state detection circuit is used for detecting whether the current state of each submitting queue is non-empty or not; the first-level shared cache management circuit is used for distributing corresponding first-level cache units in the same first-level shared cache for different submission alignments which are not empty in the current state; and the submitted column-aligning command acquisition circuit is used for sending a submitted column-aligning command acquisition request to the host end so that the NVMe controller can write the submitted queue command returned by the host end into the corresponding first-level cache unit. That is, the same first-level shared cache is provided for different submission queues, and the submission queue commands of different submission queues are written into the first-level shared cache, so that the utilization rate of the submission queue caches can be improved, cache resources can be saved, and the difficulty of hardware circuit layout and wiring of the submission queue caches can be reduced.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an NVMe submission queue control device disclosed in the present application;
fig. 2 is a schematic structural diagram of a specific NVMe submission queue control device disclosed in the present application;
FIG. 3 is a flowchart illustrating operation of a first state machine for automatically fetching SQ commands to a first level SQ cache according to the present disclosure;
fig. 4 is a schematic structural diagram of a specific NVMe submission queue control device disclosed in the present application;
FIG. 5 is a hardware circuit diagram illustrating an exemplary automatic SQ command acquisition to a second level cache according to the present disclosure;
FIG. 6 is a flowchart illustrating operation of a second state machine for automatically fetching SQ commands to the secondary cache according to the present disclosure;
fig. 7 is a flowchart of an NVMe submission queue control method disclosed in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the prior art, different SQs of NVMe have different SQ SRAM cache resources, which causes SQ SRAM resource waste and increases the area of a chip to a certain extent, particularly when the number of SQs supported by NVMe is large, and meanwhile, the SQ SRAM with a large number causes difficulty in layout and wiring of a rear-end hardware circuit and difficulty in timing sequence convergence. Therefore, the embodiment of the application discloses an NVMe submission queue control scheme, which can improve the utilization rate of submission queue cache, save cache resources and reduce the difficulty of hardware circuit layout and wiring of the submission queue cache.
Referring to fig. 1, an embodiment of the present application discloses an NVMe submission queue control device, including:
a submission queue command state detection circuit 11 for detecting whether the current state of each submission queue is non-empty;
the first-level shared cache management circuit 12 is configured to allocate corresponding first-level cache units in the same first-level shared cache for different commit queues that are not empty in the current state;
the submit-to-column command acquiring circuit 13 is configured to send a submit-to-column command acquiring request to the host, so that the NVMe controller writes a submit queue command returned by the host into the corresponding first-level cache unit.
In a specific implementation manner, in this embodiment, the corresponding first-level cache unit may be written in according to a start address of the first-level cache unit.
It can be seen that the NVMe submission queue control device disclosed in the embodiment of the present application includes: the submitting queue command state detection circuit is used for detecting whether the current state of each submitting queue is non-empty or not; the first-level shared cache management circuit is used for distributing corresponding first-level cache units in the same first-level shared cache for different submission alignments which are not empty in the current state; and the submitted column-aligning command acquisition circuit is used for sending a submitted column-aligning command acquisition request to the host end so that the NVMe controller can write the submitted queue command returned by the host end into the corresponding first-level cache unit. That is, the same first-level shared cache is provided for different submission queues, and the submission queue commands of different submission queues are written into the first-level shared cache, so that the utilization rate of the submission queue caches can be improved, cache resources can be saved, and the difficulty of hardware circuit layout and wiring of the submission queue caches can be reduced.
In a specific embodiment, the apparatus further comprises: a commit queue enabling circuit for enabling the commit queue; a commit queue halting circuit to halt the commit queue command to acquire the commit queue. Correspondingly, the first-level shared cache management circuit is specifically configured to: and if any one of the commit queues is not empty, enabled and not suspended, allocating a corresponding first-level cache unit in the first-level shared cache for the commit queue.
Further, the apparatus further comprises:
a PRP (Physical Region Page) detection circuit, configured to detect whether a memory corresponding to the submission queue at the host supports a Physical discontinuous function, and if the memory supports the Physical discontinuous function, detect whether a Physical address of a current host submitting the alignment command is available, if the Physical address is available, use the Physical address as a target Physical address, and if the Physical address is not available, send a request for obtaining PRP data of the submission queue to the host before reading the submission queue command from the host, and then analyze returned PRP data to obtain an available Physical address of the submission queue command, so as to obtain the target Physical address.
The corresponding submitting column command acquiring circuit is specifically configured to:
and sending a request for submitting the alignment command acquisition to the host side based on the target physical address.
For example, referring to fig. 2, fig. 2 is a specific NVMe commit queue control apparatus disclosed in the embodiment of the present application, which includes an SQ doorbell detection circuit, an SQ enable and SQ pause circuit, an SQ level-one shared cache management circuit, an SQ PRP detection and management circuit, an SQ command acquisition circuit, and an SQ level-one shared cache SRAM, wherein:
SQ doorbell detection circuitry: detecting an SQ head doorbell pointer and a tail doorbell pointer to judge whether the current SQ is non-null or not;
SQ enable and SQ halt circuit: SQ is divided into Admin SQ (management commit queue) and IO SQ; after the host issues the created IO SQ, a CPU (central processing unit) of the solid state disk keeps an enable register of the SQ close to 1, the IO SQ is enabled, an IO SQ command can be received, an enable signal of the Admin SQ comes from an NVMe CC. The SQ pause circuit is from an SQ pause register bit written by the CPU, and indicates that the CPU does not allow the NVMe to submit the queue control device to continue acquiring an SQ command, and the signal is used for the scenes of an NVMe reset processing flow, an NVMe low-power consumption processing flow, chip NVMe problem positioning and the like.
SQ first level shared buffer management circuit: when the SQ enabling condition, the SQ non-suspension condition and the SQ non-empty condition are all satisfied, it indicates that the NVMe commit queue control device can obtain an SQ command from the host, the first-level shared cache management circuit allocates 1 SQ shared cache unit (one unit is 64 bits long and can store one SQ command) for the corresponding SQ, the SQ first-level shared cache management circuit grants the start address of one SQ shared cache unit to the SQ after arbitration, so as to store the SQ command of the SQ, and the SQ first-level shared cache management circuit allocates SQ shared cache units for different SQ.
SQ PRP detection and management circuit: the method is used for detecting whether the SQ is a physical discontinuous function supported by an SQ memory of a host end, if the physical discontinuous function is supported, the circuit detects whether a physical address of an SQ command of the host end is available, if the physical discontinuous function is available, the SQ command acquisition circuit directly initiates a request for acquiring the SQ command, if the SQ command acquisition circuit is unavailable, the SQ command acquisition circuit initiates a request for acquiring an SQ PRP before a submitted queue command is read from the host end, and returned PRP data are analyzed to obtain the available physical address of the SQ command. If the host end does not support the physical address discontinuous function of the SQ memory, the SQ PRP detection is not needed, and the physical address of the SQ command is available all the time.
SQ command acquisition circuit: the method comprises the steps that a request for obtaining an SQ command from a host is initiated through an SQ, the request is transmitted to the host through a PCIe bus, the host returns the SQ command to the SQ, an NVMe (network video recorder) controller writes the SQ command into an authorized SQ first-level shared cache unit, and specifically, the SQ command returned from the host is directly routed and written into the authorized SQ first-level shared cache unit.
In some embodiments, the SQ level-one shared buffer management circuit is in RR (Round Robin) arbitration mode, and in other embodiments, if the SQ level-one shared buffer management circuit is in WRR (Weighted Round Robin) arbitration mode, the corresponding buffer unit is allocated to the commit queue through arbitration.
Further, the primary shared cache management circuit 12 specifically includes a first state machine, as shown in fig. 3, fig. 3 is a first state machine operation flow diagram of automatically acquiring an SQ command to the primary SQ cache disclosed in the embodiment of the present application, where (i) indicates that the SQ command is not empty, SQ is enabled and SQ is not suspended, after the condition is satisfied, the state machine jumps to an SQ _ BUF _ REQ state, applies for a start address of an SQ shared cache unit to store a 64-bit SQ command in the state, after authorization is obtained, determines whether an SQ memory address of a host end is available at this time, and if available, satisfies a condition (ii), jumps to an SQ _ REQ state, transmits an initiation request to the host through a PCIe bus, and the host returns the SQ command to the SQ and writes the SQ command into the authorized primary shared cache unit. If the data is not available, the condition (c) is met, the data jumps to the PRP _ REQ state, a request for obtaining SQ PRP is initiated, the data jumps to the PRP _ WAIT state, the usable SQ memory physical address returned by the host is obtained in the state, the returned PRP data is analyzed to obtain the usable SQ command physical address, and if the data returned by the host has errors, the data meets the condition (c), the data jumps to the IDLE state. If the data returned by the host end is normal, the condition is met, the SQ _ REQ state is jumped to, an SQ acquisition command is initiated in the SQ _ REQ state, and the IDLE state is jumped to after the data is written into the SQ first-level shared cache memory, and the execution is finished.
Referring to fig. 4, an embodiment of the present application discloses a specific NVMe submission queue control device, including:
a commit queue command state detection circuit 21, configured to detect whether the current state of each commit queue is non-empty.
And the primary shared cache management circuit 22 is configured to allocate corresponding primary cache units in the same primary shared cache for different commit queues that are not empty in the current state.
The submit-to-column command acquiring circuit 23 is configured to send a submit-to-column command acquiring request to the host, so that the NVMe controller writes a submit queue command returned by the host into the corresponding first-level cache unit.
The primary shared cache detection circuit 24 is configured to detect whether the primary shared cache is non-empty, and send a request for obtaining a secondary shared cache unit to the secondary shared cache management circuit if the primary shared cache is non-empty.
And a second-level shared cache management circuit 25, configured to allocate the second-level shared cache unit.
And the submission queue command writing buffer circuit 26 is configured to write the submission queue command in the first-level shared buffer into the corresponding second-level shared buffer unit.
A submission queue command detection circuit 27, configured to perform validity detection on the submission queue command in the first-level shared cache.
And a command detection result write buffer circuit 28, configured to write the detection result of the commit queue command into the detection result shared buffer.
For example, referring to fig. 5, fig. 5 is a circuit diagram of a specific second-level cache hardware for automatically acquiring an SQ command according to an embodiment of the present disclosure, where the circuit diagram includes:
SQ first-level shared cache detection circuit: the cache unit is used for detecting whether the first-level cache is non-empty, and if the first-level cache is non-empty, a request for acquiring an initial address of an SQ second-level shared cache unit is initiated to an SQ second-level shared cache management circuit;
SQ second level shared cache management circuit: and processing the requests corresponding to the SQs for acquiring the initial addresses of the SQ secondary shared cache units, and authorizing the requests to the initial addresses of the corresponding SQ shared cache units after arbitration.
The SQ command writes to the cache circuit: for writing SQ commands into the SQ level two shared cache memory.
SQ command detection circuit: for detecting an SQ command read from an SQ level-one shared cache, the detection may include: whether namespace is legal, whether the number of the IO read-write logic blocks is legal, whether the initial address of the IO read-write is legal, LBA out-of-bounds detection and the like.
The SQ command detection result writes to the cache circuit: the detection result of the SQ command detection circuit is written into the SQ command detection result shared cache, the SQ command detection result is composed of two double words, the first double word is used for storing the cache start address of the SQ command written into the second-level shared cache, and the second double word is used for storing each detection result of the SQ command, and the detection result can be changed flexibly according to design requirements.
In a specific implementation, the secondary shared cache management circuit 25 includes a second state machine, as shown in fig. 6, fig. 6 is a second state machine operation flowchart for automatically acquiring an SQ command to the secondary cache disclosed in the embodiment of the present application, and if the SQ primary shared cache is not empty, the operation jumps to the DEST _ REQ state, applies an SQ shared storage unit for storing a corresponding SQ command to the SQ secondary shared cache management circuit, and when DEST _ ack is high after the authorization of the SQ secondary shared cache management circuit, the operation jumps to the WREQ state, where a request for writing the SQ secondary shared cache memory is initiated, and dev _ wr _ ack is high, which indicates that the secondary shared cache bus is ready to perform a write operation, and jumps to the WWAIT state to wait for the command data to be written into the secondary shared cache memory. After the writing is finished, the dev _ wr _ done signal is in a high level, the state machine jumps to a CPLD state, a request for writing an SQ command detection result shared cache component is initiated in the state, dev _ wr _ ack is in the high level and indicates that an SQ command detection result shared cache bus is ready, the write operation can be performed, the state machine jumps to the CPLD _ WAIT state, the data of the SQ command detection result is waited to be written into the SQ command detection result shared cache, and when the dev _ wr _ done signal is in the high level and indicates that the data is written, the state machine jumps to an IDLE state, and the execution of the state machine is finished. And generating an interrupt signal when the CPLD Q _ WAIT state and the dev _ wr _ done signal is high level so as to inform the CPU that an SQ command is written into the SQ second-level shared cache memory. And the solid state disk CPU receives the state signal, reads the shared detection result cache memory to obtain the detection result of the SQ command and the initial address of the SQ command in the SQ secondary shared cache, and reads the SQ command according to the initial address.
Therefore, sharing of SRAM first-level cache resources and SRAM second-level cache resources among different SQs (Transmission Queue commit) of the NVMe is achieved through a hardware circuit, so that the utilization rate of an SQ cache is improved, the SQ SRAM cache resources are saved, the difficulty of layout and wiring of the SQ is reduced at the rear end, timing sequence convergence is facilitated, and meanwhile, the SQ command acquisition performance is improved through the hardware circuit.
Referring to fig. 7, the present application discloses an NVMe submission queue control method, including:
step S11, detecting whether the current state of each submission queue is non-empty by the submission queue command state detection circuit;
step S12, distributing corresponding first-level cache units in the same first-level shared cache for different submitted alignments which are not empty in the current state through a first-level shared cache management circuit;
and step S13, sending a request for obtaining the submitted column-aligning command to the host end by the circuit for obtaining the submitted column-aligning command, so that the NVMe controller writes the submitted queue command returned by the host end into the corresponding primary cache unit.
It can be seen that, in the embodiment of the present application, the status detection circuit of the submitted queue command detects whether the current status of each submitted queue is non-empty, and then the first-level shared cache management circuit allocates corresponding first-level cache units in the same first-level shared cache for different submitted alignment columns of which the current status is non-empty; and sending a submitted column-aligning command acquisition request to the host end by the submitted column-aligning command acquisition circuit, so that the NVMe controller writes a submitted queue command returned by the host end into the corresponding first-level cache unit. That is, the same first-level shared cache is provided for different submission queues, and the submission queue commands of different submission queues are written into the first-level shared cache, so that the utilization rate of the submission queue caches can be improved, cache resources can be saved, and the difficulty of hardware circuit layout and wiring of the submission queue caches can be reduced.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The method disclosed by the embodiment corresponds to the device disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the description of the method part.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The NVMe submission queue control device and method provided by the present application are described in detail above, and a specific example is applied in the present application to explain the principle and the implementation manner of the present application, and the description of the above embodiment is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. An NVMe submission queue control device, comprising:
the submitting queue command state detection circuit is used for detecting whether the current state of each submitting queue is non-empty or not;
the first-level shared cache management circuit is used for distributing corresponding first-level cache units in the same first-level shared cache for different submission alignments which are not empty in the current state;
and the submitted column-aligning command acquisition circuit is used for sending a submitted column-aligning command acquisition request to the host end so that the NVMe controller can write the submitted queue command returned by the host end into the corresponding first-level cache unit.
2. The NVMe submission queue control device of claim 1, further comprising:
a commit queue enabling circuit for enabling the commit queue;
a commit queue halting circuit to halt the commit queue command to acquire the commit queue.
3. The NVMe submission queue control device according to claim 2, wherein the first-level shared cache management circuit is specifically configured to:
and if any one of the commit queues is not empty, enabled and not suspended, allocating a corresponding first-level cache unit in the first-level shared cache for the commit queue.
4. The NVMe submission queue control device of claim 1, further comprising:
the PRP detection circuit is used for detecting whether a memory corresponding to the submission queue at the host end supports a physical discontinuous function, if the memory supports the physical discontinuous function, detecting whether a physical address submitting a queue command at the current host end is available, if the physical address is available, using the physical address as a target physical address, if the physical address is unavailable, sending a request for obtaining PRP data of the submission queue to the host end before reading the submission queue command from the host end, and then analyzing the returned PRP data to obtain the available physical address submitting the queue command, so as to obtain the target physical address.
5. The NVMe submission queue control device according to claim 4, wherein the submission queue command acquiring circuit is specifically configured to:
and sending a request for submitting the alignment command acquisition to the host side based on the target physical address.
6. The NVMe commit queue control apparatus of claim 1, further comprising a level one shared cache detection circuit and a level two shared cache management circuit, wherein,
the first-level shared cache detection circuit is used for detecting whether the first-level shared cache is non-empty, and if the first-level shared cache is non-empty, sending a request for acquiring a second-level shared cache unit to the second-level shared cache management circuit;
correspondingly, the second-level shared cache management circuit is used for allocating the second-level shared cache units.
7. The NVMe submission queue control device of claim 6, further comprising:
and the submission queue command writing buffer circuit is used for writing the submission queue command in the first-level shared buffer into the corresponding second-level shared buffer unit.
8. The NVMe submission queue control device of claim 6, further comprising:
and the submission queue command detection circuit is used for carrying out validity detection on the submission queue command in the first-level shared cache.
9. The NVMe submission queue control device of claim 8, further comprising:
and the command detection result write cache circuit is used for writing the detection result of the submitted queue command into the detection result shared cache.
10. An NVMe submission queue control method, comprising:
detecting whether the current state of each submission queue is non-empty through a submission queue command state detection circuit;
distributing corresponding first-level cache units in the same first-level shared cache for different submitted alignments which are not empty in the current state through a first-level shared cache management circuit;
and sending a submitted column-aligning command acquisition request to the host end by the submitted column-aligning command acquisition circuit, so that the NVMe controller writes a submitted queue command returned by the host end into the corresponding first-level cache unit.
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